JPH03205680A - Memory device having a plurality of memory cell of matrix arrangement - Google Patents

Abstract

PURPOSE: To lower the cache error rate occurring in multiple set association by providing the storage device with a connector connected to latches associated with the respective amplifiers in a second set and a column decoder for selecting one latch within a first set or one latch within the second set with respect to an external access. CONSTITUTION: A set selection signal SSA, when driven, transfers the contents of the local sense amplifier 14 for the line selected by a suitable line selection signal RL to a main sense amplifier 16A through a path transistor(TR) 18A. Similarly when a set selection signal SSB is driven, a path transistor 18B conducts and the contents of the local sense amplifier 14 associated with the selected line are transferred to the main sense amplifier 16B. The set selection signals SSA and SSB are transferred to the column decoder 20. The quadratic set associations of the storage device are respectively controlled by the set selection signals SSA and SSB associated with the sets of the path TRs 18A and 18B. As a result, the cache error rate is lowered.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the field of semiconductor memory devices, and particularly to a semiconductor memory device having cache capability on a chip.

BACKGROUND OF THE INVENTION A continuing trend in the semiconductor field is an increase in the density of storage bits per chip in semiconductor memory devices such as dynamic constant read memory (DRAM). Over the past decade, each new generation of DRAM has achieved storage capacity increases four times faster than its predecessor, with the latest generation of DRAM chips containing 4 megabits per chip. This rapid increase in the density of storage devices has resulted in a demand for increasing storage bandwidth, ie, the speed at which a user can access the bits within the storage device. Without the increase in storage bandwidth associated with increased storage density, the additional bits provided by new generations of storage devices result in lower utilization for users.

A variety of systematic techniques aim to improve storage bandwidth in addition to simply improving access time.

Modern DRAMs are built with dynamic column decode accessibility, where separate bits within an accessed row do not require a row address or column address strobe signal to be transferred; Accessed simply by forwarding the column address. An example of a DRAM with static column decoding capability is the Texas Instruments
TMS4C1027 DRAM manufactured and sold by Incorporated), and 198
There is a DRAM described in U.S. Pat. For video and graphics purposes, there is a video DRAM, U.S. Pat. U.S. Patent Nos. 4,636,986 and 19
U.S. Patent No. 4,807,1 issued February 21, 1989
No. 89, the DRAM includes a register into which a number of bits from an accessed row are loaded asynchronously to and independently of a constant access to a storage array, and Output in series.

A common technique used within data processing systems to improve storage utilization in such systems is the use of caches. Cache storage is a relatively small and fast storage that stores data from several main storage locations surrounding an addressed storage location. The theory of cache operation is that the system central processing unit (CPU) will immediately address adjacent or nearby memory locations (in terms of address values) and recently addressed memory locations. Each group of data stored in the cache is associated with a "tag", i.e. a portion of a storage address that is common to the data stored in this cache, and a comparator is associated with a storage address transferred by the central processing unit. , with one or more tags stored in the cache. If the desired storage address matches the tag value (i.e., a cache "hit" occurs), this cache will transfer the desired data much faster than it would if main memory were addressed. can be accessed, thereby increasing the effective storage bandwidth of the system.

When the appropriate portion of the desired storage address does not match the data stored in the cache (i.e., on a cache "miss", main memory must be accessed, resulting in a and generally the portion of the cache is then refilled with data from main memory in the vicinity of the newly addressed main memory location. The additional time required plus the additional time required to refill the cache with new data from addresses adjacent to the new storage address is called the "miss penalty."

Note that the time required to refill the cache, as well as the initial access to main memory for the desired storage address, depends on the main memory cycle time and the number of bits (or cache "lines") in the cache. (usually directly proportional to the portion of the cache associated with a given tag that is called). As a result, if the mistake penalty increases,
Even with a low miss rate, the effective storage bandwidth of this system will be reduced. In improving system performance by increasing cache storage bandwidth, it is therefore important to not only reduce the cache miss rate, but also to reduce the miss penalty associated with each cache miss.

DRAMs with static column decoding features such as those described above are used in cache organizations.

Regarding this, please refer to the following. J. Goodman and M-C. Zhang, “Static column RAM as a memory scale.
11th Annual Computer Symposium (
Institute of Electrical and Electronics Engineers Computer Section Press, 1984), pages 167-174 (J, Goodma
n and M-C. Chiang. “The
Use of Static Column RAM a
s a Memor7 Hierarchb7. The
lIfbAnnual Sytnpositivm on
CompIIter^rchitecjure (I
EEE Computer Sosiel7 Pres
s, 1984) pp. 167-174). However, such storage devices store an entire row of storage in a static column buffer, so a cache hit requires the address to be within a single row. Although the dimensions of the rows stored in the static column buffer (e.g., if a large number of ordinal addresses are to be addressed) will allow for a large number of cache hits, the probability of a cache hit is , is lower than would be possible if a large number of row addresses were at least partially stored in the buffer.

[Problems to be Solved by the Invention] An object of the present invention is to provide a storage device that reduces cache miss rates due to multi-set association within on-chip cache storage.

Another object of the invention is to provide such a storage device that can be efficiently incorporated into a DRAM chip.

Yet another object of the present invention is to provide a storage device that requires a minimum of off-chip logic elements to utilize cache capabilities.

Still another object of the present invention is to provide a storage device that allows array data to be refreshed without disturbing the contents of the cache.

Yet another object of the invention is to provide such a storage device in which data in this storage can be refreshed while parts of the cache are being updated.

Still another object of the present invention is to provide a system that utilizes such a storage device.

Additionally, numerous other objects of the invention will become apparent to those skilled in the art upon reference to the following description in conjunction with the accompanying drawings.

SUMMARY OF THE INVENTION The present invention is implemented within a semiconductor storage device by providing a number of latches associated with each column of a storage array, each of which has a sense amplifier for that column. can be selectively connected to.

These latches are grouped into sets, which correspond to sets of columns of the storage array. Data from the selected row of the storage array is loaded into the selected set of latches into which the data is to be read and written. Selection of multiple latches associated with each set of columns is accomplished by multiple column address strobe signals.

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 illustrates the set-associative organization of a storage array 2 of the present invention and is intended to illustrate the improvement in caching performance achieved by the present invention.

Array 2 is a rectangular arrangement of storage cells, these cells being one transistor, one capacitor storage cells used in modern DRAMs, with such storage cells arranged in rows and columns. To explain the operation, array 2 is 0 to 31.
Contains 32 rows numbered up to . Array 2 is divided into four groups of columns, so each row contains a column within each of the four groups. Therefore, array 2 is subarray 6.

Including 63 from. Of course, it should be noted that fewer or more than four sub-arrays 6 can alternatively be used, depending on the desired architecture of the array and cache performance.

Associated with array 2 are registers 4A and 4B. The number of bits contained within each of registers 4A and 4B is equal to the number of columns in array 2. Registers 4A and 4B also have four sub-registers 4A to 4A3 and 4, respectively.
BO is divided into 4B3, each sub-register being associated with one of the sub-arrays 6. Each sub-array 6 therefore has a pair of sub-registers 4A and 4B associated with it.

Improved cache performance is obtained according to the invention by the availability of a large number of secondary registers 4A and 4B for array 2. A system in which the contents of two rows of the subarray 6 are cached separately is called binary association. It is obvious, of course, that if an additional sub-register 4 can be provided for each sub-array 6, an rnJ element set association can be realized, where n is the number of rows of the sub-array. This is the number of sub-registers that can store their contents.

The multiple sub-registers 4A and 4B storing data from different rows within each sub-array 6 increases the probability of cache hits and thereby improves cache performance.

Referring to FIG. 1, subarray 6. has rows 4 and 21 with highlighted diagonal stripes, and these two rows are in register 4.
Indicates that it is stored in A and 4B. In this example, the contents of row 4 of subarray 6 are stored in subregister AAD O and the contents of row 21 are stored in subregister A B o
stored within. Therefore, if this storage array receives an address for one bit in either row 4 or row 21 for a column in the group associated with subarray 6o, a cache "hit" occurs and the data is transferred to row The address can be decoded and read or written without energizing this row, ie, in the cache cycle time of this storage array.

Other sub-arrays 6 to 63 can store data from different rows in their respective sub-registers 4A1 and 4B. For example, the contents of row 7 in subarray 61 are stored in subregister 4A, and the contents of row 13 in subarray 6 are stored in subregister 4A.
The contents of are stored in sub-register 4B. It should be noted that each of these rows is stored in either sub-register 4A or 4B, and that the upper of the two rows, as shown in FIG. 1 for sub-array 61, That is, the row (row 7 for subarray 61) is stored in the lower subregister 4B. Subarray? Referring to (2), the contents of row 4 are stored in subregister 4 B 2 and, as noted above, the contents of row 4 from subarray 6o are stored in subregister A A o. Therefore, the contents of the same row in different subarrays 6 are stored in different ones of registers 4A and 4B.

With reference to FIG. 2, the two described above in connection with FIG.
Let us now explain the operation of the storage array 10 configured with original set associations. Array 10 is a rectangular arrangement of storage cells, such as dynamic storage cells arranged in rows and columns as is well known in the art. Row decoder 12 receives the row address portion of the address signal transferred from the outside via address line Xn, decodes the row address, and energizes the row in array 10 corresponding to the row address value. .

Things to be careful of are the clock circuit, read/write control circuit,
Input/output circuits and other circuitry required and conventionally included in a DRAM are, of course, present even though they are not shown in FIG.

As in conventional DRAM, each column in array 10 is associated with a local sense amplifier 14. row decoder 1
One of the local sense amplifiers 14 for each storage cell of array 10 in the row selected by 2 senses the stored data state (read recycle or unwritten) in a conventional manner. During a write cycle to a column), the sensed data state is restored back to its re-storage cell. However, to implement the n-way set association of the present invention, the set of local sense amplifiers 14 cannot be used as a cache, since selecting a row would destroy the data state stored within this row. It is. Therefore, a set of latches is arranged in the storage device according to the invention, which set is capable of storing the states of n sets of data stored in cache mode. Furthermore, such a latch arrangement allows for partitioning of array 10 without partitioning array 10, since a set of cache lines allows access to only the data portion of a physical row. It is. By using this latch arrangement, more storage cells than are associated with a single cache segment can be refreshed by energizing one row.

Note that although a single line is shown connecting between each local sense amplifier 14 and array 10, a pair of conjugate bit lines connect each local sense amplifier 14 and its associated within array 10. It is important to understand that there are connections between columns. Such transfers are performed for modern DRAMs, in which sense amplifiers typically sense the differential charge between a pair of bit lines, and one of the lines in the pair is selected. One line is connected to a storage cell and the other line is connected to a pseudo or reference cell. Further, in FIG. 2, although other lines for transferring data are also shown as single lines, a pair of conjugate lines is used for such transfer as well, and the present invention is equally applicable to this case. It should be understood that

A main sense amplifier 16 is used in the embodiment of FIG. 2 to perform the n-way (in this case, binary) set association according to the present invention. Each local sense amplifier 14 is associated with a pair of main sense amplifiers 16 (ie, 16A and 16B) and transfers thereto via pass transistor 5 and one of pass transistors 8A or 18B. The pass transistor 5 is controlled by a line select signal RL derived from the column address applied to the storage device to select the desired cache line, which cache line was discussed above in connection with FIG. as part of one row within a particular subarray. In the example shown in FIG. 2, each line has an order (R
It is related to the line selection signal RL separated into L, RL1, . . . 0 RL. When the associated line select signal RL is high, the pass transistor 5 connected thereto conducts and transfers the data state of its associated local sense amplifier 14 through it. In the example of FIG. 2, line select signal RLo is applied to local sense amplifiers 14o. 14,. 142. Thus, via the selection signal RL and the pass transistor 5, the partitioning of the array 10 into sub-arrays associated with cache lines is effected, while all physical rows of the array 10 are divided into sub-arrays by the row decoder 12. Refreshed by selecting one row.

The binary set association of the storage device of the FIG. 2 embodiment is controlled by set selection signals SSA and SSB associated with sets of pass transistors 18A and 18B, respectively. As explained below, the set select signals SSA and SSB are preferably clock signals applied to this memory device in a manner similar to the way conventional column address strobe CAS-clock signals are applied to conventional DRAMs. derived from the signal. Set selection signal SSA, when driven, transfers the contents of local sense amplifier 14 to pass transistor 18 for the line selected by the appropriate line selection signal RL.
A to the main sense amplifier 16A. Similarly, when set select signal SSB is driven, pass transistor 18B conducts and transfers the contents of local sense amplifier 14 associated with the selected line to main sense amplifier 16B.

The set selection signals SSA and SSB are also applied to the column decoder 20
will be forwarded to. Column decoder 20 also receives the column address portion of the address n presented to the storage device, indicated by address line V 1 . In this embodiment, column decoder 20 causes data from local sense amplifiers 14 in a selected line to be received by a desired one of main sense amplifiers 16 when a cache line is to be loaded, and A selected one of the main sense amplifiers 16 is connected to the data lines DA and DB for reading data from or writing data to them, as in the case of accessing a particular bit therein.

In this embodiment, column decoder 20 has two sections: least significant bit LSB section 20a
and the most significant bit MSB section 20b. Bottom section 20
a of main sense amplifier 16A or 16B to decode set select signals SSA and SSB to sense the data state on the lines that are transferred to the main sense amplifier via pass transistors 18A and 18B, respectively. Select which set should be enabled. The top section 29B decodes the column address and sends it to the data line D.
to select one (or more) of the main sense amplifiers 16 for transfer to A or DB (data line DA for the set of main sense amplifiers 16A and data line DB for the set of main sense amplifiers 16B). Indicates which bits within a cache line should be accessed.

Of course, as will be apparent to those skilled in the art, other alternative embodiments are also available for the organization of column decoder 20 to enable the use of a set of main sense amplifiers 16 corresponding to a selected line. .

An alternative embodiment for controlling the operation of the storage device according to the state of set selection signals SSA and SSB is shown in FIG. In this embodiment, set selection signals SSA and SSB are not forwarded to column decoder 20, but instead to output enable circuit 21. Output enable circuit 21 also connects data line DA from main sense amplifier 16 to
and DB connection. Which of the set selection signals SSA and SSB (selects set A or B of the main sense amplifiers 16 in the selected cache line)
In response to activation, output enable circuit 21 connects either data line DA or DB to data line D for transfer with external circuitry. This alternative embodiment provides improved cache read performance over the embodiment of FIG. 2, where column decoder 20 is responsive to the state of set select signals SSA and SSB. Conversely, set select signals SSA and SSB are not needed within a cache hit read operation until a point within the store cycle following decoding of the column address by column decoder 20. The cache controller connected to the storage device of FIG. additional time will be required to determine whether a cache hit has occurred (by

Here, referring to FIG. 3, a fourth embodiment including the present invention is shown.
The layout of a megabit storage device 100 is shown. The storage device in this embodiment physically has 4.096 rows Xi
．． 024 columns, with 32 storage cells.
is contained within the array 10 of . Each array 10 has two storage cells.
It has 56 physical rows and 512 physical columns. The row decoder 12 is divided into two parts, one for each storage device 10.
Select one of the 2,048 rows at each end of 0 that are associated with it. The two More rows will be made available and selected within each cycle. In this embodiment, one row is selected by each of the sections of row decoder 12, in which case the most significant column address bits indicate which of the two selected rows the row is selected for input/output. or make further selections. The embodiments of the invention described herein are also applicable to other rectangular configurations of rows and columns with "square" arrays or other various addressing schemes.

Between each array 10 is a bank of local sense amplifiers 14. In this embodiment, local sense amplifier 14 is
It is shared between adjacent arrays 10 as described in U.S. Patent Application No. 265.112 filed October 31, 1988 and assigned to Texas Instruments Corporation. Local sense amplifier 14 in this configuration is preferably a folded bit line or as described in U.S. Pat. A quasi-folded bit line is used. Of course, other arrangements of local sense amplifiers may alternatively be used as are well known to those skilled in the art.

Each bank of local sense amplifiers 14 is adapted to communicate with two banks of main sense amplifiers 16A and 16B as explained above, with selected transfers to the latter as explained below. controlled in a certain way. A pair of banks of main sense amplifiers 16A and 16B have memory devices ffi
Associated with eight arrays 10 in one quadrant of lE100. As shown in FIG.
Each bank of main sense amplifiers 16A and 16B associated with one group is divided into four sections.

These sections correspond to cache lines within storage device 100. In this embodiment, the storage device 100
has two sets of main sense amplifiers for each of the 16 cache lines, each set storing 128 consecutive bits from a selected row within an array 10. 1st
As explained above in connection with the figure, each of the two sets of main sense amplifiers for each of the 16 cache lines has 128
bits can be stored, which means that in the embodiment of FIG. 3, one set for each adjacent cache line, as well as one set for the same cache line in array 10 that is different from each other. 128 from the line
It means that bits can be stored. In the embodiment of FIG. 3, the cache lines are grouped into quadrants so that the eight sets within each quadrant can store data associated only with the eight arrays 10 within that quadrant. Various alternative arrangements for the set of main sense amplifiers 16A and 16B will be apparent to those skilled in the art, but such arrangements do not add to the cache line array 10 at the expense of layout and interconnect complexity. flexibility in allocation.

Column decoder 20 decodes array 10 on the same side of storage 100.
The main sense amplifiers 16A and 16 associated with the two quadrants of
B is placed between opposing banks. The column decoder 20 in this embodiment is divided into two sections and selects one of the columns of the entire storage device (if the storage device iiioo has a single power and a single output). Of course, other conventional decoding schemes can also be used to select the desired columns for the desired layout. The configuration shown in Figure 3 is a large-capacity DRA such as a 4 megabit storage device.
It is particularly suitable for M.

Referring now to FIG. 4, the transfer from each bank of local sense amplifiers 14 to main sense amplifiers 16A and 16B for one quadrant of storage device 100 shown in FIG. 3 will now be described.

For clarity, array 10 is not shown in FIG. 4, but it is assumed that array 10 is located between each horizontal group of local sense amplifiers 14, as shown in FIG. do.

In the embodiment of FIG. 3, there are eight arrays 10 associated with a bank of main sense amplifiers 16A and 16B for one quadrant, and the bank of main sense amplifiers 16A and 16B is divided into four cache lines; Each of the lines receives data from each of the eight arrays 10.

Referring to FIG. 5, the address map for the 4 megabit storage device of FIGS. 3 and 4 is shown in the case of a by-one (single bit input and single output) storage organization. In order to address all 4 megabits (222 bits), 22 address bits are naturally required, i.e. the most significant 11 bits are the row address part and the least significant 11 bits are the column address part. The row address portion of such an address signal selects two rows, one on each side of column decoder 20 as explained above;
Therefore, one row is selected within each quadrant of storage device 100.

The three most significant bits of the row address signal select which of the eight arrays in each quadrant contains the selected row, and the eight least significant bits determine which row within the selected array 10 is to be selected. do. For the column address portion of the address signal, its most significant 4 bits determine which of the 16 cache lines to select (i.e., to generate line select signals RLO to RL15 in this example) and the column address The least significant seven bits of the portion select the desired bit within the selected cache line.

Referring back to FIG. 4, the selection of the group of local sense amplifiers 14 to be transferred with the main sense amplifier will now be described. Line select signals RLO through RLn, described above in connection with FIG. 2, are used to transfer the contents of the local sense amplifiers in the selected line to main sense amplifiers 16A and 16B. Since multiple groups of local sense amplifiers are used in this embodiment, the row address selects which group of local sense amplifiers 14 is to communicate with its associated main sense amplifier 16. Therefore, the gates of the bus transistors 15 receive the decoded signals that select the appropriate array (such decoded signals are shown in FIG. 4 as available for the eight arrays 10 associated with a given cache line). It is controlled by a logic AND with the line selection signals RLO to RLn (designated as ARO to AR7) and the line selection signals RLO to RLn. Such a logic AND is, of course, performed in a conventional manner.

It should be noted that due to the shared sense amplifier concept as shown in the layout of FIG.
There are no eight banks of local sense amplifiers 14 representing a one-to-one correspondence of two arrays 10; instead, there are nine physical banks. The description here is not of the physical arrangement of local sense amplifiers 14, but rather of the eight arrays 10 within each quadrant.
It is intended to correspond to a memory location within.

In a write operation, if the cache line associated with the line select signal RLO is selected by the four most significant bits of the column address, the pass transistor 15 associated with the local sense amplifier 14 for the selected row is enabled. I'm sure it will be done.

If, for example, the selected row is in the second array from the top of the quadrant, the logical AND of the enable signal ARI and the line select signal RLO is enabled, and therefore 12
8 pass transistors 15 receive this signal (two of these are shown in FIG. 4 as receiving, namely in columns 0 and 1), and these are A second set of local sense amplifiers 14 will be associated and enabled. The contents of these local sense amplifiers 14 are then placed on main data lines 24 and 24o- to transfer all 128 bits in this memory line to main sense amplifiers 16A and 1.
Transfer to the desired set of 8B.

As discussed above, set selection signals SSA and SSB are clock signals that determine which of the sets associated with a desired cache line receives data from local sense amplifier 14. Set selection signals SSA and SSB
is also used as a column address slottobe signal conventionally used on multiplexed address DRAMs, where the desired one of set select signals SSA and SSB is needed to select the desired cache line. is transferred during column decoding. One of the associated bus transistors 18A or 18B is therefore enabled for each column in the addressed cache line, and therefore the state of the main data lines 24o and 24o is passed through these pass transistors. Transferred into the desired set of cache line main sense amplifiers 16A and 16B.

To complete a read operation, column decoder 20 receives column address signals and connects main data lines 24 and 24o.
- the main sense amplifiers 16A and 16B in the desired set to receive and store the state of the main sense amplifiers 16A and 16B in the desired set;
be made available. This function is determined from the logical operation of set selection signals SSA and SSA to the four most significant column address bits. Such enable signals cause the main sense amplifiers 16A and 16B1 in unselected cache lines and the main sense amplifiers 16A and 16B associated with unselected sets in selected cache lines to communicate on their associated main data lines 24. required to avoid detecting the (undetermined) data state of

Such detection may, of course, destroy data stored in the main data line.

Main sense amplifier 16 is constructed according to conventional design. An example of such a main sense amplifier is described in U.S. Pat. No. 4,716,320, issued December 29, 1987 and assigned to Texas Instruments Corporation. The main sense amplifier includes active pull-up and pull-down devices to enable these sensing operations and also to latch the state of the main sense amplifier according to sensed data as long as these devices are in the on state. Additionally, the main sense amplifier includes an equalization transistor;
This transistor is turned on during precharging in order to equalize the sensing node to a common potential before the sensing operation.

In the storage device 100 according to this embodiment, the operation of the main sense amplifier 16 is such that the column decoder 2o adjusts the voltages at the gates of the pull-up, pull-down and equalization transistors according to whether the associated cache line is selected or not. By controlling, be controlled. For clarity, the lines connecting column decoder 20 to main sense amplifier 16 are not shown in FIG. For the main sense amplifiers 16 associated with cache lines and sets selected to be loaded with new data during a read operation, the column decoder 20 turns on the pull-up and pull-down transistors in the main sense amplifiers 16. and turns on the equalization transistors so that these main sense amplifiers 16 are precharged to receive new data states.

When new data is to be transferred onto the main data lines 24 for these main sense amplifiers 16, the column decoders 20 perform pull-up and pull-down operations at appropriate cycle times to sense and latch the associated data state. The transistor can be turned on and the equalization transistor turned off.

For the main sense amplifiers 16 associated with unselected cache lines during a read operation, and for the main sense amplifiers 16 associated with unselected sets of selected cache lines.
6, the column decoder 20 maintains the active pull-up and pull-down transistors in their amplifiers on and the equalization transistors in them off, so that the data is Latched within the amplifier.

Column decoder 20 also performs the function of selecting desired bits within the selected cache line and
In order to output to the outside of 100, a pass transistor 22
A and 22A connect one of the main sense amplifiers 16A and 16B in the selected set of selected cache lines to data line DA or DB.

In a write operation, data DA and DB associated with a desired set are driven and stored in storage device 100 with a desired data state. After column decoding is complete, the driven data state on data lines DA and DB is, as the case may be, for the selected column in the selected cache line.
The write data is transferred to the main sense amplifier 16A or 16B, where the write data is stored in the desired set of cache lines. In a write-back operation, an entire cache line is written into the local sense amplifier 14 for this selected line; therefore, in a write-back operation where a cache line is written into a storage cell within the selected row. , depending on the case, pass transistor 18A or 18
B is enabled so that the main sense amplifier 16A
or 16B are transferred to the main data lines 24 and 24- for the selected set, respectively.

The pass transistor 15 for the group of local sense amplifiers 14 in the selected cache line is enabled as in a read operation, and the local sense amplifier 14 receives the data state on the main data lines 24 and 24--; As a result, as in conventional DRAMs, storage cells in a selected row receive all local sense amplifiers 14 (rather than just local sense amplifiers 14 in the selected cache line).
Receive the data state at.

Other alternative embodiments for controlling the response of main sense amplifiers 16 in a selected set of selected cache lines and for maintaining previously stored data in other main sense amplifiers 16 include: , will be clear to those skilled in the art.

One such alternative embodiment, which may be suitable for reducing power consumption at the expense of silicon area, particularly in write-back operations, is shown in FIG. In this embodiment, pass transistor 18A
and 18B are controlled not only by the set selection signals SSA and SSB, but also by the cache line address. The pass transistor 18A associated with the main sense amplifier 16 in cache line O has its gate connected to the set select signal SSA, which is a clock signal, rather than simply by the set select signal SSA as in the embodiment of FIG.
and cache line selection signal RLO. Similarly, pass transistor 18A associated with main sense amplifier 16 in cache line 1 has its gate set to set select signal SSA and cache line select signal RL.
Controlled by a logical AND of I. Similarly, logical AN
D controls pass transistor 18B associated with other cache lines and set select signal SSB. Such control of pass transistor 18 does not require control of the internal transistors of main sense amplifier 16 by column decoder 20 as described above. The same set that is in an unselected cache line but is enabled for the selected cache line (i.e., the set selection signal SSA
In this arrangement, the main sense amplifiers 16 associated with the sets selected by SSB and SSB will not unnecessarily drive the full capacitive load of the main data lines 24 during writeback of that selected cache line. active power is saved during write-back operations.

Now, with reference to FIG. 6, a system including the storage device 100 having the configuration described above in connection with FIGS. 3 and 4 and its operation will be described. Central processing unit W (
CPU 50 performs conventional data processing operations including storage accesses through an address bus that includes an X address portion and a Y address portion, as shown in FIG. Enable the peripheral in the conventional manner to drive a signal on the REQUEST line and receive a signal on the ACKNOWLEDGE from a peripheral that receives this signal on the REQUEST line. The handshaking control request signal (REQUE)
ST) and an acknowledgment signal (ACKNOWLEDGE) are sent by the central processing unit 50.

In the system of FIG. 6, the peripheral device is the storage controller 6.
It is 0. Storage controller 60 in this embodiment performs the control operations known in the art necessary to control cache operations and, if storage device 100 is a dynamic storage device, as previously described. Control operations are also performed that are useful for controlling the operation of the storage device. Controller 60 therefore includes a block of integrated circuits that performs the functions described below, or is a custom integrated circuit (or set of circuits) that performs these functions. It is believed that one skilled in the art would be able to configure controller 60 given the functional requirements specified below.

A controller 6 for controlling cache access and operation.
0 includes the cache tag comparator functionality, which is
Specific part of the address that specifies the row address and storage device 1
A cache line corresponding to a row address known to be currently stored in a plurality of cache lines of 00 is compared. In the embodiment described above, the cache line is specified by Y1, the four most significant bits of the column address (see FIG. 5). Such a comparison is made with the SN74ACT2151, SN74ACT, manufactured and sold by Texas Instruments.
2152, SN74ACT2153, SN74ACT2
154 is performed by controller 60 in a conventional manner.

Other cache control functions included within controller 60 include stack circuitry or other arbitrary ordering circuitry to determine which of the cache lines should be replaced in the event of a cache miss. A variety of known techniques can be used to make permutation decisions. One such technique is the least recently used (LRU) stacking method, in which the circuitry maintains tracks in a predetermined order in which cache lines are accessed, thus reducing misses. In some cases, a long-unused cache line becomes the line to be replaced. 6th
A preferred replacement algorithm for the illustrated system is described in detail below. Other techniques, including random replacement, may be used alternatively, as is well known in caching technology. Other control functions performed by controller 60 are flags, commonly referred to as "dirty bit" flags, that indicate whether a write operation has been performed to a particular cache line. The setting of the dirty bit flag is set by controller 60.
one bit of this set corresponds to each cache line of the storage device.

In connection with the DRAM control function, the controller 60 is a SN74ALS2967, SN74ALS2968, manufactured and sold by Texas Instruments, Inc.
It is operable to control access to storage device 100 as RAM in a manner similar to the SN74ALS6301, SN74ALS6302, and THCT4502B dynamic storage controllers. Such storage control functions include the transfer of clock signals RASB, SASIB, CAS2B to storage device 100, where signals SASIB and CA32B generate set select signals SSA and SSA discussed above with respect to storage device 100. Controller 60 further receives a read/write signal R/W from central processing unit 50 and transfers a corresponding signal WRITEB on line WRITEB to storage device 100 . It should be noted that for the purpose of this explanation, the signals listed above will be referred to with the last letter rBJ (i.e., RASB, SA
SIB, CAS2B and WRITEB) are considered active at logic low levels. The controller 60 also controls an address multiplexer 52 via a control line 51 to combine the X address sent by the controller 60 itself and the Y address transferred by the central processing unit 50.
A selection is made between the addresses and the result is transferred onto an address bus connected to the storage device 100. It should be noted that the functionality of the multiplexer 52 is similar to that of the THC referenced above.
It is integrated into the controller 60 in a manner similar to that in the T4 5 0 2 BDRAM controller.

Similarly, the controller 60 controls the data multiplex converter 54 via the control line 53 to control the read/write signal R/W transferred by the central processing unit 50 to read/write data from the storage device 100. Either the data output bus DATA OUT or the data input bus DATAIN connected to the output terminal Q and the input terminal D, respectively, is connected to a bidirectional data path DATAB BUS connected to the central processing unit 50.

Additionally, controller 60 preferably performs the function of determining when refresh of storage device 100 is necessary;
And such refresh is performed by generating necessary signals to the storage device 100. T referred to above
The HCT4502B controller includes circuitry to accomplish such a refresh and also includes a timer to determine when a refresh is required. In the system of this embodiment, the refresh of the storage device 100 is preferably performed in a distributed manner rather than in bursts, since cache accesses continue during refresh unless a cache miss is encountered. As is well known, distributed refresh is performed by periodically refreshing a single row of storage, the period of which is a specified refresh time (e.g. 4 milliseconds) when the refresh cycle is to be performed. (eg, once every 15.625 microseconds) divided by the number of refresh cycles (eg, 256) required to refresh the entire storage device to reach the frequency. In contrast, a burst refresh is performed by successively performing all required refresh cycles as the refresh time elapses (e.g., 256 consecutive refreshes are performed before 4 milliseconds elapse). ). Since the probability of a cache miss is extremely high during the time it takes to perform a full refresh cycle consecutively and extremely low during the time it takes to perform a single refresh cycle, if a distributed refresh is performed rather than a burst refresh; It is believed that the cache performance of the system of FIG. 6 is better. Thus, controller 6o in this embodiment periodically issues requests during a single refresh cycle, the period of which depends on the specified refresh time of storage device W100 and the number of refresh cycles required for a full refresh.

The storage device 100 according to this embodiment preferably has an on-chip refresh address counter, which stores the row address corresponding to the next row to be refreshed. Upon completion of Flesh Theil, mnemonic
ioo increments the contents of the on-chip counter and prepares it for the next refresh operation. The inclusion of such on-chip counters in dynamic storage is described in U.S. Pat. No. 4,207,618, issued June 10, 1980 and assigned to Texas Instruments Corporation. . Such on-chip storage eliminates the need for controller 60 to preset the refresh address on the address bus to storage device 100, and instead continuously operates storage device 100 in cache mode unless a cache miss occurs. This is preferable because it can be accessed.

Another advantage of the on-chip refresh address counter is that the controller 60 does not need to include the additional circuitry required to store and increment the contents of the counter; Knowledge of the actual values stored within the controller is not critical to the system as long as the timer within controller 60 ensures that all required refresh cycles are initiated within the specified refresh time. be.

In the system of FIG. 6, it should be noted that each of the multiple storage devices 100 has an output terminal Q and an input terminal D, and each storage device 100 receives a clock signal and an address signal in parallel. It is. A number of storage devices 100 are each associated with one line of the data input line DATA IN and data output line DATA OUT, the number of storage devices 100 corresponding to the width of the data on the data path DATA BUS. It should be obvious to those skilled in the art that a number of banks of storage ffiloO are provided and that control of the selection of the desired bank is accomplished in a conventional manner by means of a decoding clock signal.

These control functions in the system of FIG.
0 and separate from either central processing unit 50 or storage 100. The controller functionality may alternatively be incorporated within the memory device 100, as described in U.S. Patent Application No. 175.875, filed March 31, 1988 and assigned to Texas Instruments. It will be done.

However, if multiple storage devices 100 are used for a data word width, or additionally for multiple banks as explained above, then for each storage device 100 It is believed that it is much more difficult to incorporate controller functionality into a single circuit for all storage devices than it is to duplicate the circuitry. Of course, this increase in storage 11100 to its multiple bank storage arrangement is not only due to the complexity of address decoding and selection, but also due to the storage and bus complexity that such a system would require. will have an adverse effect on system performance due to the physical length of the conductor connecting the . Such adverse effects must be considered for the particular desired application. It should be noted that in yet another alternative embodiment, the functionality of controller 60 may be incorporated within the same integrated circuit as central processing unit 50, if desired.

Now, with reference to Table 1, a truth table for the operation of the system of the embodiment shown in FIG. 6 will be explained. Each of the storage devices 100, in addition to the example circuitry described above with respect to FIG.
r refresh)). Flag bit C assumes the state “0” on cache misses and during operations performed for write-backs and cache loads;
And the state is "1" during the cache hit cycle. The flag bit R takes the state "0" during both the cache hit cycle and the refresh miss cycle in which no refresh operation is performed, and takes the state "1" during the refresh hit cycle in which the refresh operation is performed. In this embodiment, flag bit R cannot assume the state "1" while flag bit C is in the state "0", as will be explained below with respect to the operation of the system of FIG. That's right. It should be noted that in this embodiment, flag bits C and R are
Furthermore, it should be noted that in this embodiment, the flag bit C and R are generated internally to storage 100 and cannot be directly read or set except through the cycles described herein.

Of course, other alternative embodiments for controlling cache and refresh operations (and their states) will be apparent to those skilled in the art, and such alternative embodiments may include storing such bits in controller 60 and This includes providing additional lines to and from the storage device 100 to control its operation. Internal storage and setting of flag bits C and R within storage device 100 is preferred from the standpoint of operational performance and integration.

The general operation of the system shown in FIG. 6 will now be explained in detail with reference to Table 1 and FIGS. 7a to 7C. Figure 7a shows the order of operation for this system in cache hit and no refresh mode. In this case, the flag bit C in the storage device 100 is in the state “1”.
, and flag bit R is in state "0". In this mode, at the beginning of operation, at decision block 700 in FIG. 7a, controller 60 determines whether a refresh is required. As is well known in the art, conventional dynamic storage controllers are operable to determine the need for refresh cycles and cause associated storage devices to perform refreshes. Such functionality is
As explained above, it is preferably included within the functionality of controller 60. When it is determined that a refresh cycle is necessary, controller 60 lowers all three signals RASB, CASIB and CA32B to all connected storage devices 100 as shown in FIG. (signals RASB, CASIB, CAS
The low state of 2B is indicated as "O/O/0" in FIG. 7a, and this convention for indicating the state of these three signals driven by controller 60 remains unchanged in FIGS. 7b and 7c. , inherited). In response to these three signals going low in this mode, storage device 100 in this embodiment sets its internal flag bit R to state "1" (block 702) and is in cache hit and refresh mode. (Figures 7a and 7
(via connector C of Figure 7C), which is described below with respect to Figure 7C.

When the controller 60 determines that a refresh operation has not been performed, the controller 60 inputs the most significant 4 bits of the X address and Y address (hereinafter collectively referred to as in this embodiment, controller 60 controls multiplexer 52 so that the Y address portion of the address transferred by central processing unit 50 ( That is, the cache address portion of the address and the address of the desired bit) are transferred onto the address bus (processing block 704 in FIG. 7a).

Controller 60 also determines whether the address desired by central processing unit 50 is within the cache portion of storage device 1100 (i.e., a cache "hit"), as indicated at decision block 706. , cache "misses"). This determination is made in accordance with the well-known method of operation of the cache tag comparator referenced above, in which the X address received from central processing unit 50 is
7 for the cache line indicated by the most significant 4 bits of the Y address of the storage device 100 having the storage arrangement shown in the figure.
and compares it with the X address stored in the cache tag memory.

In the event of a cache miss, controller 60 outputs signal RASB
, CASIB, and CAS2B are all driven to a high state (ie, "1/1/1" in FIG. 7a). This indicates that a cache miss has occurred on storage device fil00, and storage devices 100 each drive this flag bit C to state "0" (block 708), indicating that the storage device's operation in cache miss mode is This is performed (as described below with respect to Figure 7b).

In the event of a cache hit, controller 60 also:
It must be determined which set associated with the addressed cache line should be made available (Section 7a).
decision block 710).

For a storage device 100 configured as described above in a binary set associative scheme, decision block 710 determines whether main sense amplifier 16A or 16B is enabled. This determination is made by a cache tag comparison operation since two sets of cache tags (ie, the X address) are stored for each cache line address (ie, the four most significant bits of the Y address). Depending on which set is desired, the signal C
The appropriate one of ASIB or CA82B is driven by controller 60 to assume its low state while the other signal maintains its high state.

For example, if set A (i.e., main sense amplifier 16
A) is to be accessed for the desired cache line, controller 60 drives signal CASIB low and signal CAS2B high, causing set B (i.e., main sense amplifier 16B) to be accessed. Access is enabled by the controller driving signal CAS2B low and signal CASIB high. The desired set of accesses to the addressed cache line is
Therefore, achieved (processing blocks 712a and 7
12b). It should be noted that the state of signal WRITEB on line originating from controller 60 enables either read or write operations and connects multiplexer 54 via control line 53 in a conventional manner. Control and data human power bus DA
TA IN (1 bit of data input bus is memory device 1)
00) or the data output bus DATAOUT (one bit of the data output bus is connected to one output terminal Q of the storage device 100) to the central processing unit 11E50. Connect to the data path DATA BUS. Storage device 10
0 is then responsive to the driven signal in a conventional manner;
Accomplishing either a read or write operation on a selected set of addressed cache lines.

It should be further noted that the system of FIG. 6, when storage device 100 is configured as described above, provides the desired set of addresses for the addressed cache line upon a write access to storage device 100. This means that the data is only written to, and is not "written through" to the array within the storage device 100.

Set updates to cache lines therefore require write-back operations, as explained below.

It should be noted that the advantages of the system of FIG. 6 would hold even if the storage device 100 was configured for write-through, i.e., the advantages of the system of FIG. considerations will determine which of these two schemes is suitable for the required application.

In this preferred embodiment, storage device 100 is configured in a "write-back" manner, as described above.

After the desired access is completed, the system maintains the cache hit and no refresh mode and performs the next cache address refresh and comparison via connector A, as shown in Figure 7a. Start making decisions again.

The operation of the system of FIG. 6 in cache miss mode will now be described with reference to FIG. 7b. In this mode, flag bits C and R of storage device 100
are both in state "0".

It should be noted that when the system enters cache miss mode, at connector B of FIG.
2B are all driven high (Figures 7a and 7).
(See Figure C). At this time, memory device! 1100 enters conventional row precharging for their operating cycles at processing block 720. As described above, this preferred embodiment of the system and storage device 100 is configured in a write-back manner. Accordingly, after determining a cache miss (decision block 706 of FIG. 7a), controller 60 determines which of the cache lines and their associated sets should be erased from the cache of storage device 100. .

As explained above, there are a number of conventional methods for arbitrating which set of cache lines should be removed from a storage device's cache.

The preferred method for the system of FIG. 6 is to use the most significant four bits of the Y address as the cache line address,
Among the related sets A and B, the one that has not been used for the longest time is replaced. This method uses the same Y by the central processing unit 50 to address the cache line upon writeback (if necessary), upon loading new data, and upon the first cache access from the central processing unit 50. Allows you to transfer addresses. This method also does not require the additional step of translating the four most significant bits of the Y address from central processing unit 50 into a different address when addressing a cache line. At processing block 720, the determination of whether set A or set B should be substituted for the cache line addressed during the cache miss is preferably made by controller 60 during row precharging of the storage device. .

After controller 60 determines which set of addressed cache lines should be replaced with new data, controller 60 interrogates the "dirty" bit flag DBIT and
Determine whether a write operation has been performed on the set to be replaced. If no writes have taken place (i.e.
If the dirty bit flag DBIT is clear), then no write-back operation is performed and a write operation of new data to this set is performed (processing block 73 of Figure 7b).
2). If a write has occurred (i.e., if the dirty pit flag is set), then the set of cache lines to be replaced is The set for must first be written to that location in array 2 of storage device 100. If such a writeback is not performed, data written to the replaced set for the cache line will be lost. As is clear from this description, the storage device 100 in this embodiment cannot be written to except via cache hit mode, and therefore has write-back (or alternatively write-through capability).
Without it, the written data cannot be loaded into array 2.

Writeback is performed by controller 60 placing the X address (the "old" X address) on the address bus via multiplexer 52 and controlling multiplexer 52 via control line 51, This is accomplished by having the old X address transferred to it by 60 selected and transferred onto the address bus. This old
, controller 60 then drives signal RASB low in accordance with the conventional row address portion of the DRAM cycle;
Keep signals CASIB and CAS2B high. Controller 60 then directs multiplexer 52 to central processing unit 5.
0 transfers the stored value of the most significant four bits of the Y address (i.e., cache line address) onto the Y address bus, and selects these four bits via control line 51 to multiplexer 52. and transfer it to the address bus. Note that the least significant bits other than the four most significant bits are "don't care" for this operation. However, since during this time all Y addresses are maintained transferred by central processing unit 50, the easiest configuration for multiplexer 52 is to transfer either all X addresses or all Y addresses to the address bus. would be to choose.

At decision block 728, controller 60 determines whether set A or B should be enabled to perform the writeback operation and, based thereon, sets signal CA.
82B or CA 82B and associated signal WRITEB low to accomplish writing data to array 10 (processing blocks 730a and 730a for sets A and B, respectively). 730b)
. In cache miss mode, the write-back operation is
This is how it is accomplished.

If the writeback operation is complete or if decision block 722
If a write-back operation is not necessary because the dirty bit flag DBIT is clear, the cache of the storage device 100 can be updated.

The controller 60 controls the multiplex converter 52 to transfer the desired address X address transferred from the central processing unit 50 onto the address bus. Controller 60 then outputs signal R
Drive ASB low and signal CASIB and CAS2
Driving B high (ie, "O/1/0") allows storage device 100 to perform conventional row decode and enable operations. In the processing program 734, the controller 6o controls the multiplex converter 52 to
Transfers the Y address transferred by 0 onto the address bus. This Y address is the same Y address that was additionally transferred by the central processing unit 50. The most significant four bits determine which cache line is to be updated with new information, and the least significant bits specify the bit within this cache line that is to be accessed.

Controller 60 then determines the desired set A or B (
i.e., the selection of the main sense amplifier 16A or 16B), and following this, the signal WRITB being high.
in conjunction with driving the appropriate one of signal CASIB (for set A) or signal CA32B (for set B) low, processing blocks 738a and 738b.
Array 2 into the addressed cache line via
Achieve read availability. After the set for the addressed cache line has been loaded with the addressed data, an access of the desired bit specified by the least significant bit of the Y address occurs, with signal ERITEB remaining high. A read operation is performed when the set is updated, or a write operation is performed by driving the signal WRITEB low after sufficient time has elapsed for updating this set. Storage devices 100 each then drive flag bit C to state "1" at processing block 740. Controller 6
0 then enters cache hit mode via connector A of the block of FIGS. 7a and 7b, and asserts signal RA.
Drive SB high.

The operation of the system of FIG. 6 in cache hit and refresh mode will now be described with reference to FIG. 7C. In this mode, both flag bit C and flag bit R within each of storage devices 100 are in state "1". This mode is entered from cache mode when controller 60 determines that a refresh operation is required (decision block 700 in FIG. 7a). As explained below, the preferred refresh operation is a distributed refresh, where single refresh cycles are periodically distributed depending on the refresh time specified for the storage device 100 and the number of refresh cycles required for a full refresh. will be started on. Also, as noted above, the storage device 100 preferably has an on-chip refresh address counter, so that the controller 60 stores the refresh address and stores the refresh address at the beginning of a refresh cycle. There is no need to transfer to 100. To initiate the refresh operation, the controller 60
drives all three signals RASB, CASIB, and CA32B low (operation block 702 of FIG. 7a).
) and then maintains signal RASB active low.

Signals CASIB and CA82B are then output to controller 60.
(Action Block 75Q)
, initiates the row decoding, enabling, sensing, and recovery operations conventionally performed within a DRAM to restore storage device 100.
Refreshes the contents in the row of the memory corresponding to the contents of the on-chip refresh address counter in the memory.

In this embodiment, the local sense amplifiers 14 of the storage device 100 are used to sense data and restore the sensed data into selected rows within the selected array 10, and so on. Data cached in the main sense amplifier 1 is buffered by a local sense amplifier 14.
6, it is possible and preferred to continue the cache operation during the time the storage device 100 is in the refresh operation. Therefore, the controller 60
After initiating a refresh operation by transferring the contents of the on-chip refresh address counter onto the address bus, controller 60 can initiate the next cache access operation.

Therefore, as long as the system continues to have cache hits, the cache accesses described above with respect to FIG. 7a proceed as described above. 4 things to be careful about
That is, in conventional DRAM, refresh cycles occur on the order of 150 to 20 nanoseconds, whereas cache accesses may be accomplished much faster, e.g., on the order of 25 to 50 nanoseconds. It is.

Therefore, multiple cache accesses could be made during the time when one row in each of the stores 1floo is refreshed at the same time. However, if one row is selected for update or writeback during a time when a refresh operation on a different row is being performed, a collision may occur on the local sense amplifier 14. Therefore, it is desirable that refreshes continue undisturbed in the event of a cache miss. In this embodiment, as explained below, the system of FIG. 6 may "lock out" cache miss (i.e., row) accesses during such times that a refresh operation is in progress. Dew.

Processing block 752 of FIG. 7c indicates that after refresh is enabled by controller 60, the controller sends a new cache address (i.e.,
address, and the most significant 4 bits of the Y address), and controls the multiplexer 52, so that the central processing unit 5
The Y address portion of the address transferred by 0 is transferred to the address bus. In the same manner as in the cache hit mode described above, controller 60:
A cache tag comparison is performed at decision block 754 to determine if a cache hit or cache miss has occurred.

In the event of a cache miss, controller 60 drives signal RASB low and signals CASIB and CAS2B high until the time required for the refresh operation is exceeded (decision block 756). As is well known,
Dynamic storage has a specified refresh cycle time during which appropriate signals are maintained active.

Once the refresh cycle time is complete, controller 60:
Drive signal RASB high. Although driving signal RASH high is shown as a decision block (blocks 756 and 768 in FIG. 7c) for purposes of explanation, the completion of the refresh operation is independent of the cache access, so controller 60 preferably drives signal RASB high at the end of the refresh cycle time in a synchronous manner with respect to cache hit or cache miss operations.

High signal RAS indicating end of refresh operation
Upon receiving B, the storage devices 100 then each clear their flag bits R to state "O" to indicate that the refresh operation is complete. At decision block 754, since a cache miss was detected by controller 60, storage devices 100 each also clear their flag bit C to state "0" (processing block 760), and with respect to FIG. 7b. The cache miss mode described above is entered via connector B.

At decision block 754, when a cache hit is detected by controller 60, controller 60 (via decision block 762) sets A to the cache line determined by the four most significant bits of the Y address.
or determine which of set B (ie, sense amplifier 16A or sense amplifier 16B) should be accessed.

In the same manner as in the cache hit and no refresh mode, controller 60 activates signals CASIB or C to enable the desired set of set A or set B for the addressed cache line.
Drive one of A52B low (keep the others high).

Either a read or a write on the set to the desired cache line is accomplished in processing blocks 764a and 764b in the same manner as described above with respect to FIG. 7a.

As discussed above in connection with cache misses, controller 60 synchronously determines whether the refresh operation time is complete. Until the required cycle time has expired, controller 60 maintains signal RASB low (shown as decision block 768 for purposes of explanation) and sets and maintains flag bit R in storage 100. , and control operation returns to processing block 752 where the next cache address is received by controller 60, the Y address portion of that address is transferred onto the address bus, and whether this cache address match has occurred. It is compared against the stored cache tag to see if it is.

Once the required refresh cycle time has expired, the controller 60 signals this with three signals RASB, CASIB.
, CAS2B are all driven high. Each of the storage devices 100 resets the flag bit R to state "1" and enters the Cache Hi y } mode via connector A as described above with respect to FIG. 7a. In this way, subsequent cache misses cause the system to immediately enter cache miss mode without incurring the lockout required to complete the refresh operation.

In this way, the system of FIG.
The same storage devices 100 configured as described above with respect to the figures operate in such a way that they serve as both cache storage and also main storage. The n-way set association (in this example, n=2) provides cache capability for increased cache speed and improves overall system performance. An example to describe the operation of the system includes a cache hit mode, followed by write-back and set load operations in cache miss mode, followed by operation in cache hit and refresh mode. The flowcharts depicted in Figures 7a through 7C, as will be apparent from them, illustrate the operation of the system without regard to any particular order.

For further explanation, the specific order of operations will now be described with reference to FIG. FIG. 8 shows the memory device 11
The timing of the signal observed (or driven) by one of 00 is shown. The sequence in this example includes a read and write cycle in cache hit and no refresh mode, and also includes a cache miss writeback and set load, and one cycle in cache hit and refresh mode.

Upon entering the cache hit and no refresh mode, the address bus is routed to controller 6 as explained above.
A 0 indicates that a new Y address will be transferred onto this bus. In this mode, flag bit C is in state "1" and flag bit R is in state "0", as explained above. In this mode, as long as the cache hit continues, controller 60 controls signal RAS
Keep B high. The first cycle of FIG. 8 is a read operation into set B for the cache line, with signal CASIB being driven high and signal CA82B remaining low. In response to these signals, storage device 1
00 transfers the data state of the addressed storage cells to their output terminals Q with timing similar to that in accesses from conventional static column decoding storage devices. DRA with static column decryption access capabilities
An example of M is the TM84C1027D RAM manufactured and sold by Texas Instruments.
It is.

The second cycle shown in FIG. 8 is a one bit write operation into set A for the cache line addressed by the new Y address transferred on the address bus. In this cycle, the signals CASIB and W
RITEB is driven low, signal CA82B is driven high, and the data to be written to the addressed bit in set A for the addressed cache line (in this case data state "0") is From the central processing unit 50 to the storage device 10 via the multiplex converter 54
0 input terminal D (see FIG. 6). As explained above, the storage device 100 is configured according to a write-back scheme, so that data is not written into the array 10 of the storage device 100 by this operation, but only in the set for the cache line. written.

After the cache write operation shown in FIG. 8, a new Y address (indicated as address value Ymiss in FIG. Transferred to 100. However, in this order, the controller 6
0 has determined that the X address transferred to this controller by central processing unit 50 does not match the X address associated with cache line address value Y (i.e., the most significant 4 bits of the mass Y address portion). . As shown in FIG. 8, in the event of a cache miss, the signal RASB1CA
SIB and CAS2B are all driven high, causing storage device 100 to reset flag bit C to state "O".

For purposes of illustration, in this case the dirty bit flag DBIT in controller 60 has been set and written to the set for the cache line to be replaced, so its contents are Displays something different from what is stored in the location corresponding to. To achieve write-back operation, controller 60:
As shown in FIG. 8, first the X address associated with the set for the cache line to be replaced is transferred onto the address bus and signal RASB is driven active low. This allows storage device 100 to enter row address decoding and use the portion that follows the conventional multiple translation address DARM cycle. Controller 60 then:
The address value Y. indicated by the top four bits of the Y address. is transferred onto the address Inlgg bus to select the cache line to be replaced, which in this case is the same cache line that was addressed by central processing unit 50. Controller 60 also drives signal CASIB low and signal CA32B high to
Indicates that it is set A for the addressed cache line that is to be written to array 10 in the row selected by the address. In this example, set A is selected for replacement by controller 60 through detecting which of set A or set B for cache line mass at address value Y was recently accessed. As explained above, this scheme provides simple operations for writing back and updating the cache without requiring address translation to be performed. Signal WRITEB
is also driven to an active low state to enable write-back operation. What should be noted is that the memory device 1i11
Either output terminal Q or input terminal D of 00 is inactive, ie, the data output is in a high impedance state and the data input is a don't care.

Following a write-back cycle, storage device 100 enters an update mode in which the cache line associated with the address value Y driven by central processing unit 50 is loaded into the desired set.

Therefore, controller 60 causes multiplexer 52 to transfer the X address driven by central processing unit 50 (i.e., the "new" X address) onto the address bus and again drives signal RASB low. , so that conventional row address decoding and the row available portion of this cycle begins again. The controller 60 then sets the address value Y. of the Y address portion driven by the central processing unit 50.
is transferred onto the A11181 address bus, so that the cache line associated with the four most significant bits of the Y address portion is selected, the signal CASIB is driven low, and the signal CAS2B is
is driven high so that set A (i.e., main sense amplifier 1
6A) is loaded with new data. After the new data is loaded into set A for the addressed cache line, the desired read operation (in this case) is performed, with the associated address value Y. The bit of the cache line corresponding to the least significant bit of
will be forwarded to. In response to signal RASB being driven high at the end of this cycle, flag bit C of memory 1100 is set to state "1" to indicate that the operation is to be transitioned back into cache hit mode. .

In the sequence shown in FIG. 8, the next cycle is a conventional cache hit and no-refresh cycle, in which the new Y address is transferred onto the address bus and the desired bit is accessed (in this case, the address A read operation is performed on set }B for the cache line that has been read, producing a state "0" at output terminal Q). However, at this point in the sequence, controller 60 indicates that a refresh is required by driving signal RASB low and signals CASIB and CA82B both high. In response, the storage devices 100 each set their flag bit R to state "1", but cache operations continue as before (set A for the cache line, each corresponding to a new Y address). Continue the cache operation (as shown by the read operation above and the write operation on set B to the cache line), just keep signal RASB low until the refresh operation is complete. As explained above, the on-chip refresh address counter is used by the memory device 100, through the local sense amplifier 14, to energize one row of the memory array within the synchronous memory device. Signal RASB is driven high again and signals CASIB and CA8
In response to 2B also being driven high, storage device 1
00 each set their flag bit R to state "0" to exit cache hit and refresh mode and enter cache hit and no refresh mode.

Effects of the Invention The storage device 100 and the system of FIG. 6 constructed in accordance with the present invention have significant advantages in storage system performance and efficiency. Multi-set associative on-chip caches, along with array partitioning, provide improvements in cache hit speed and efficiency on write-back and update operations. Additionally, memory refresh can be performed in a manner that is substantially transparent to cache accesses, while maintaining both main memory and cache within chip boundaries.

It should also be noted that future system architectures will benefit from the memory organization described and advocated herein. In the future, the scale of integration will continue to increase, incorporating more functionality onto a single chip and including wafer scale integration.

An example of a future system is the P1958 system, which is described in Peterson et al., "Design Proposals for Future Single-Chip Computers," IEE Computer Technical Report, Volume C-29, No. 2 (IEEJ). Published, 198
February 0), pages 108-115 (PaHe
rson ej all. , ”DesignCon
Sideration for Single-Chi
p Computers of the Future
, IEEE Trans. ,on Compute
rs, VatC-2 9, Na2 (IEEE, F
eb, 1980) pp. 1 08-1
15. )It is described in. This example describes the incorporation of both dynamic and static storage as local storage for a one million transistor integrated circuit. The present invention
can be incorporated into such very large scale integrated circuits, including wafer integration, without the need to fabricate both dynamic and static storage cells on the same wafer. The use of multiple storage cells (eg, DRAM) provides storage performance advantages. Furthermore,
The system of FIG. 6 not only allows a single control block to perform both cache control and main memory control, thereby providing the benefit of improved performance;
It allows two functions to be efficiently integrated within a single chip or wafer integrated application. The present invention is further believed to be advantageous for application to multi-processor systems, particularly systems in which multiple processing devices are integrated on a wafer scale, as described above.

Additionally, it should be noted that the preferred embodiment of the present invention is described above in connection with a storage device configured as dynamic read/write RAM. Although it is believed that the advantages of the present invention are particularly advantageous for such storage devices, it is believed that the advantages of the present invention may also be provided for static read/write storage devices as well. Furthermore, in connection with the improved performance of storage devices and systems according to the invention obtained during read operations, it is noteworthy that the advantages of the invention also extend to read-only storage devices constructed according to the invention. (hereinafter referred to as ROM), especially, for example,
ROM stores program code for the data processing devices in the system and is also provided if the use of a program cache is desired.

Although the invention has been described herein in detail with reference to preferred embodiments thereof, this description is by way of example only;
It should not be construed in a limiting sense. Furthermore, many modifications in detail to embodiments of the invention, as well as additional embodiments of the invention, will be apparent and possible to those skilled in the art upon reference to this description. All such modifications and additional embodiments are considered to be within the spirit and true scope of the invention as claimed above.

Regarding the above description, the following sections are further disclosed.

(1) A type of memory device having a plurality of storage cells arranged in rows and columns, comprising: a row decoder for selecting the plurality of storage cells in the row in response to a row address signal; and a plurality of sense amplifiers. each of the plurality of sense amplifiers senses the data state of a storage cell selected by the row decoder; one latch in the first set of latches is associated with one of the plurality of sense amplifiers; one set, and each of the plurality of sense amplifiers has one sense amplifier in the first set.
one latch in the second set of latches, the second set being associated with one latch in the second set of latches, and one latch in the second set associated with one of the plurality of sense amplifiers; connecting each of the plurality of sense amplifiers to a latch associated with each amplifier in the first set in response to a signal, and each amplifier of the plurality of sense amplifiers in response to a second set selection signal; to a latch associated with each amplifier in said second set of latches; and in response to a row address signal, one latch in said first set or said second set for external access; a column decoder for selecting one latch in the memory.

(2) In the storage device according to item 1, the plurality of sense amplifiers include a first line and a second line of sense amplifiers, and each of the first line and the second line of the sense amplifier is connected to the plurality of sense amplifiers. associated with a first group and a second group of columns of storage cells of , and storage cells in both the first group and the second group of columns are selected by the row decoder; The storage device characterized by:

(3) In the storage device according to item 2, each of the first set and the second set of latches has a first line and a second line of the latches within the first set and the second set. the first line and the second line of the latch are associated with the first line and the second line of a sense amplifier, and the storage device further comprises: the column address signal and the first line the first line of a sense amplifier is connected to the first line of a latch in the first set in response to a set select signal; a connection device connecting the first line of a sense amplifier to the first line of the latches in the second set; and a connection device for connecting the first line of the sense amplifier to the first line of the latches in the second set; connecting the second line of a sense amplifier to the second line, and connecting the second line of the sense amplifier to the second line of the latch in the second set in response to the column address signal and the second set selection signal; The storage device comprising: a connection device for connecting a second line; and a connection device for connecting a second line.

(4) The memory device of claim 3, wherein each sense amplifier corresponds to a single row of the plurality of memory cells.

(5) In the storage device according to claim 4, a first value of the part of the column address signal corresponds to a column associated with the first line of the sense amplifier, and a second value of the part of the column address signal corresponds to a column associated with the first line of the sense amplifier. The memory device characterized in that the value corresponds to a column associated with the second line of a sense amplifier.

(6) In the storage device according to item 3, the connecting device connects the first line of a sense amplifier to the first set and the second set of latches, and the first set and the second set of latches. The storage device, wherein the connection device for connecting the second line of the sense amplifier to each of the connection devices includes a pass transistor.

(7) The memory device according to item 1, wherein the memory cell is a read/write memory cell.

(8) The memory device according to item 1, wherein the memory cell is a read-only memory cell.

(9) In the storage device according to item 1, the plurality of sense amplifiers include a first group and a second group of sense amplifiers, and the first group and the second group of sense amplifiers are the plurality of sense amplifiers. associated with first and second groups of rows of cells, and each column of said plurality of storage cells is associated with said first and second groups of rows of cells;
associated with one sense amplifier in a group and one sense amplifier in the second group.

(10) The storage device according to item 9, further comprising: the plurality of local data lines, each local data line of the plurality of local data lines being associated with one column of the plurality of storage cells; a connection device for connecting the first group of sense amplifiers to the plurality of local data lines in response to the row address signal selecting one row in the first group; and and a connecting device connecting the second group of sense amplifiers to the plurality of local data lines in response to the row address signal selecting a row.

(11) In the storage device according to item 10, each of the first group and the second group of sense amplifiers further includes a first line and a second line of sense amplifiers, and the first line of sense amplifiers and the second line are associated with the first group and the second group of the plurality of memory cells.

(12) In the storage device according to item 11, each of the first set and the second set of latches is connected to the first set of latches.
the first line and the second line of the latch within the set and the second set.
the first line and the second line of the latch are associated with the first line and the second line of a sense amplifier of the first group and the second group of sense amplifiers; and the storage device further comprises: assigning the local area associated with the first line of a column to the first line of a latch in the first set in response to the column address signal and the first set selection signal. a connection device for connecting a data line and for connecting the first line of a sense amplifier to the first line of a latch in the second set in response to the column address signal and the second set selection signal; connecting the local data line associated with the second line of a column to the second line of a latch in the first set in response to the column address signal and the first set select signal; a connection device for connecting the second line of a sense amplifier to the second line of a latch in the second set in response to a signal and the second set selection signal. The storage device.

(13) In the storage device according to item 12, the connection device that connects the first group of sense amplifiers connects the row address signal that selects one row in the first group to the first group of sense amplifiers. connecting the first line of the sense amplifier in the first group to a local data line associated with the first group in response to the column address signal selecting a line; In response to the row address signal selecting one row of the sense amplifiers and the column address signal selecting the second line of the sense amplifiers, the local data lines associated with the first group are connected to the local data lines of the sense amplifiers in the first group. connecting a second line; the connecting device connecting the second group of sense amplifiers;
local data lines associated with the second group in response to the row address signal selecting one row in the second group and the column address signal selecting the first line of the sense amplifier. connecting the first line of the sense amplifiers in a group and responsive to the row address signal selecting one row in the second group and the column address signal selecting the second line of sense amplifiers; and connecting the second line of a sense amplifier in the second group to a local data line associated with the second group.

(14) a data processing device that performs operations on data, the data processing device being operable to generate storage addresses on the data processing device and to receive data; and columns and rows. a first cache set and a second cache set corresponding to different rows and the same column of the main array; a storage device connected to an address bus and connected to the data processing device for storing the data in the storage device; and a storage device connected to the processing device for receiving storage addresses from the data processing device; and a storage controller connected to the address bus for transferring storage addresses, wherein the storage address transferred by the data processing device is transferred to the second cache set or the second cache set of the storage device. determining whether the storage address transferred by the data processing device corresponds to a location in the first cache set of the storage device, transferring the address to the address bus and forwarding a set selection signal to the storage device such that the storage device transfers data stored in the location of the first cache set corresponding to the transferred address to the data processing device; If the storage address transferred by the data processing device corresponds to a location in the second cache set of the storage device, transfer the address to the address bus and transmit a second set selection signal to the storage device. If the transfer by the data processing device results in the storage device transferring to the data processing device the data stored in the location of the second cache set corresponding to the transferred address. If the stored storage address does not correspond to data stored in the first cache set or the second cache set of the storage device, transfer the address to the address bus and send a control signal to the storage device. the storage controller operative to cause the storage device to transfer data stored in the array location corresponding to the storage address to the data processing device; data processing system.

(15) The system according to item 14, wherein the storage device is a read/write storage device, and the storage controller transfers a read/write signal corresponding to a desired operation to the storage device. Said system.

(16) In the system according to item 15, the storage device is a dynamic read/write storage device, and the storage controller further determines whether a refresh operation is necessary; transmitting a control signal to the storage device to perform refresh in response to the determination.

(17) In the system according to item 14, the first cache set and the second cache set are
each including a first cache line and a second cache line; and the portion of the address to be transferred by the data processing device is such that either the first cache line is to be selected or the second cache line is to be selected. The system described above is characterized in that it makes a judgment as to whether or not it should be done.

(l8) In the system according to item 17, the storage controller may store a storage address portion corresponding to a row stored in the first cache line of the first cache set, and a storage address portion corresponding to the row stored in the first cache line of the first cache set. a storage address portion corresponding to a row stored in a second cache line; and a storage address portion corresponding to a row stored in the first cache line of the second cache set;
a storage address portion corresponding to a row stored in the second cache line of the second cache set, and the storage address transferred by the data processing device is stored in the first cache set of the storage device. or determining whether the data corresponds to data stored in the second cache set by comparing the portion of the storage address that has been deleted and transferred with the storage address portion stored in the storage controller. The system characterized in that:

(+9) A storage device having binary set associative cache capability and a system using the storage device for both cache storage and main storage are disclosed.

The storage device can be sensed by a local sense amplifier in each group of columns, and the sensed contents in the local sense amplifier can be loaded into multiple (e.g., two) sets of main sense amplifiers. Certain results are stored in the set. 4. Delete main sense amplifier access by Y address. and the set of main sense amplifiers associated with the designated group selected by multiple clock signals (e.g., only one column address strobe signal associated with each set). Can be performed in column decoding mode. The multi-set associativity of the storage device provides improved performance. The closed system disclosed herein further includes a central processing unit and a controller, wherein the controller performs all of the functions of a cache comparator, dirty pit, and least recently used as a conventional cache controller. Not only do
It also performs storage control functions as a conventional dynamic constant access storage controller (refresh initiation, row and column multiple conversion, etc.). The system can therefore utilize the same storage device as main memory and cache memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram illustrating the association of a Kya Sosh memory device constructed in accordance with the present invention; FIG. 2 is a block-type electrical circuit diagram illustrating the operation of a single storage array of an embodiment of the present invention; 3 is a block diagram showing a schematic configuration arrangement of a storage device according to an embodiment of the present invention including a large number of storage arrays shown in FIG. 2, and FIG. 4 shows a local sense amplifier and main 5 is a schematic electrical circuit diagram of the connections between the sense amplifier and the memory device of FIG. 3; FIG. 6 is a configuration diagram of the address word for the memory device of FIG. 3; and FIG. 7a to 7c are flowcharts illustrating the operation of the storage system of FIG. 6; FIG. 8 is a block-type electrical circuit diagram of the storage system of FIG. 6; FIG. 9 is a timing diagram illustrating the operation of the storage system of FIG. 9, which corresponds to FIG. , a schematic type electrical circuit diagram corresponding to FIG. 4, but showing the connection between the local sense amplifier of FIG. 3 and the main sense amplifier, but for an alternative embodiment of the invention; [Symbol explanation 2: Storage array 4A, 4B: Register 4A ~ 48 4B ~ 4B3: Sub register 0
3' 0 60-63: Sub-array 10: Storage array 12: Row decoder 14: Local sense amplifier 15: Pass transistor 16. 16A, 16B + main sense amplifier 18A, 18B
:Pass transistor 20:Column decoder 21:Output enable circuit 22A. 22B: Bus transistor 24. 24,: Main data line 0 50: Central processing unit 52: Multiplex converter 54; Multiplex converter 60: Storage controller 100: Storage devices ARI to AR8 D=Data lines DA, DB: Data lines RLO to RLn: Line selection Signal SSA-SSB: Set selection signal output enable signal

Claims (1)

[Claims] (1) A type of memory device having a plurality of storage cells arranged in rows and columns, the device comprising: a row decoder for selecting a plurality of storage cells in a row in response to a row address signal; and a plurality of sense amplifiers. each of the plurality of sense amplifiers senses the data state of a storage cell selected by the row decoder; one latch in the first set of latches is associated with one of the plurality of sense amplifiers; one set, and each of the plurality of sense amplifiers has one sense amplifier in the first set.
one latch in the second set of latches, the second set being associated with one latch in the second set of latches, and one latch in the second set associated with one of the plurality of sense amplifiers; connecting each of the plurality of sense amplifiers to a latch associated with each amplifier in the first set in response to a signal, and each amplifier of the plurality of sense amplifiers in response to a second set selection signal; to a latch associated with each amplifier in said second set of latches; and in response to a row address signal, one latch in said first set or said second set for external access; a column decoder for selecting one latch in the memory.