JPH03201734A - Time slot replacing circuit - Google Patents

Abstract

PURPOSE:To reduce the circuit scale and power consumption by applying time division processing to plural low speed data so as to write or read the resulting data thereby using a couple of RAMs for the function of time slot replacement in a same string and string replacement of plural signal strings. CONSTITUTION:RAM 12, 13 are high speed random access memories having a storage capacity able to store information of one frame of a multiplexed signal, a one bit period of a low speed data signal is divided into n, t1-tn, and a time division data obtained by using an input selector 11 through the switching connection of n-channel signals CH1-CHn is tentatively stored. In this case, the sequence of the signals CH1-CHn corresponding to the times t1-tn is changed to realize time slot replacement (spatial switch) of the signal. On the other hand, an output address control circuit 16 accesses sequentially the RAN storing the time division data and outputs a signal subject to time compression to 1/n. Thus, a large storage capacity of the RAM is required but only a couple of the RAMs is enough, number of peripheral circuits is less and power consumption is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a time slot switching circuit, and more particularly, to a time slot switching circuit that converts a plurality of consecutive data signals into a high-speed time division multiplexed signal using a pair of random access memories (RAMs). On the other hand, the present invention relates to a multiprocessing type time slot switching circuit that converts a high-speed time division multiplexed signal into a plurality of continuous data signals.

[Conventional technology]

A conventional time slot switching circuit of this type has -pairs of RA
A speed conversion circuit writes data at low speed and reads it at high speed to convert continuous data signals into burst-like high speed signals, and conversely, a speed conversion circuit writes data at high speed and reads data at low speed to convert the signal into continuous data signals. The time slots are replaced by sequentially changing the address on the write side or the read side.

In the conventional time slot switching circuit for multiplexing, as shown in FIG.
The data is sequentially written into the RAM 2 or 3 for each frame by the input side address control circuit 4 which operates at the clock frequency of the low-speed data. Output side selector 5
In this case, the RAM on the opposite side from the input side selector 1 is connected to the high-speed side composite diagram GIO, and the written information is sent to the output side address control circuit 6 as a time-division multiplexed signal approximately 0 times that on the low-speed side. The signal is read out and transmitted at a clock frequency of approximately 1/n of one frame period. The address selector 7 is a selector that controls switching, writing, and reading of the RAMs 2 and 3. n-channel (CH
In order to perform multiplexing of I to CHn),
Conversion circuits 8-1-8-n are provided, and the control timing of each output side address control circuit 60 is set so that the output burst signals of each channel do not overlap, and then the synthesis circuit 9 synthesizes and performs time division multiplexing. I'm getting a signal.

The conventional time slot switching circuit for separation is
As shown in the figure, the time division multiplexed signal input from the high speed side is distributed by the distribution circuit 20 into n identical signals, which are each connected to conversion circuits 9-1 to 9-n in channel units. The distributed signal is alternately switched to the RAMs 22 and 23 at a frame cycle by the input side selector 25 controlled by the frame synchronization signal 102, and is sent to the RAM 22 and 23 by the input side address control circuit 26 which operates at the clock frequency of the high speed side data.
The writing tube is sequentially written to M22 or M23. Output side selector 21
connects the input side selector 25 and the RAMK low speed side data output end on the opposite side, and the information stored in the RAM is continuously read out by the output side address control circuit 24 at a clock frequency of about 1/n of the high speed side. Ru. address selector 2
7 is a selector that controls switching, writing, and reading of the RAMs 22 and 23;

[Problem to be solved by the invention]

The conventional time slot switching circuit described above has the drawback that the number of RAMs and their peripheral circuits used increases in proportion to the number of channels of the low-speed side data signal, and power consumption also increases.

An object of the present invention is to time-divisionally process and write or read a plurality of low-speed side data so that a pair of RAMs can perform the functions of column swapping of a plurality of signal columns and time slot swapping within the same column. It is an object of the present invention to provide a time slot switching circuit that eliminates the drawbacks of the conventional system.

[Means to solve the problem]

A time slot switching circuit according to a first aspect of the present invention includes an input control means for sequentially switching and connecting low-speed data signal strings of a plurality of channels to a pair of random access memories, and input control means for sequentially switching and connecting low-speed data signal strings of a plurality of channels to a pair of random access memories; storage control means for causing the random access to perform complementary operations such as writing and reading alternately and repeatedly at fixed time intervals, and time-sharing all the information written from the random access memory at fixed time intervals; and output control means for sequentially performing high-speed reading.

A time slot switching circuit according to a second aspect of the present invention includes an input control means for connecting a time division multiplexed signal including a plurality of channels to a pair of random access memories and sequentially connecting all information; and a pair of said random access memories. storage control means for performing complementary operation and storage by alternately repeating writing and reading at predetermined time intervals; and output control means for separating the time division multiplexed signal into low-speed data signal sequences of each of the channels. There is.

〔Example〕

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the first aspect of the present invention, showing a multiplexing circuit. This embodiment includes a pair of RAMs 12 and 13 with large storage capacity, an input selector 11 that connects n-channel low-speed data signals (CHI to CHn) to the RAMs 12 and 13, an input address control circuit 14, and an output selector 15. , output side address control circuit 1
6, an address selector 17. FIGS. 2(a) and 2(b) are time charts for explaining the operation of this embodiment. The RAMs 12 and 13 are high-speed random access memories with a storage capacity capable of storing information of one frame of the multiplexed signal, and as shown in FIG. -tn, and temporarily stores the time-division data obtained by switching and connecting n-channel signals (CHI to CHn) using the input side selector 11.Here, corresponding to each time of F+j2+...in signal (
By changing the order of CHI to CHn), signal time slot replacement (spatial switch) is realized.

On the other hand, the output side address control circuit 16 sequentially accesses the RAM in which the time-division data is stored, and performs control to output a signal time-compressed to 1/n.

Therefore, as shown in FIG. 2(b), the information of each channel consists of a burst signal, which is T1+T2. ... A time division multiplexed signal is obtained by sequentially arranging the signals within the time Tn.

Here, by controlling the output side address so as to change the time slots in units of 8 bits (1 byte) within each time period of Tl*Tte...Tn, the time slots in each channel can be changed (time switch ) is realized.

With the above configuration, a multi-processing type time slot switching circuit is realized, and although it requires a larger RAM storage capacity than the conventional circuit shown in FIG. Power is also reduced.

FIG. 3 is a block diagram of an embodiment of the second aspect of the present invention, showing a separation circuit. This embodiment includes a pair of RAMs 32 and 33 with a large storage capacity, an input side selector 35 that connects n-channel high-speed side data multiplexed signals to the RAMs 32 and 33, an input side address control circuit 36, an output side selector 31, and an output side It is configured to include an address control circuit 34 and an address selector 37. Figure 4 (ω and (
0 is a time chart for explaining the operation of this embodiment, and the figure (ω is the output side (t)) shows the input side. Third
As shown in the figure, RAMs 32 and 33 are multiplexed signals 1
High-speed RA with storage capacity that can store frame information
It is M. As shown in FIG. 4(b), the information of each channel is 'r1. The time-division multiplexed signal sequentially arranged for each time period T2, . . .
1 is sequentially written into the RAM at high speed. Here TI, T
0n...Tn p and 8 bits (
By controlling the input side address so as to change the time slots in units of 1 byte (1 byte), time slot replacement (time switch) within each channel is realized. on the other hand,
On the output side, the output side address control circuit 34 controls the fourth
As shown in the figure (-), the RAM is sequentially accessed and data is read out within one bit time of each channel.The output side address control circuit 34 latches the read data of each channel and 1-bit width data is reproduced. Here, the signal channels are swapped ( spatial switch) is realized.

In this embodiment as well, as in the embodiment of the first invention, the circuit scale and power consumption can be reduced compared to the conventional circuit.

〔Effect of the invention〕

As explained above, according to the present invention, circuit scale and power consumption can be reduced compared to conventional circuits.

[Brief explanation of drawings]

1 and 3 are block diagrams of embodiments of the present invention;
Figures (a) and (b) and Figures 4 (a) and (b) are time charts of embodiments of the present invention, and Figures 5 and 6 are block diagrams of conventional time slot switching circuits. 1.11, 25.35... Input side selector, 2
゜3.12, 13.22, 23.32.33...
・Random access memory (RAM), 4.14°26
．． 36...Input side address feed circuit, 5゜15
．． 21.31... Output side selector, 6, 16
゜726． 36...Output side address control circuit, 27 37...Address selector,...Composition circuit, 20...Distribution circuit.

Claims (2)

[Claims] (1) Input control means that sequentially switches and connects a plurality of channels of low-speed data signal strings to a pair of random access memories, and writes and reads all information of the low-speed data signal strings to and from the pair of random access memories at regular intervals. storage control means for causing memory to be operated alternately and repeatedly in a complementary manner, and output control means for sequentially and rapidly reading out all the information written from the random access memory at regular time intervals in a time-sharing manner. Time slot switching circuit. (2) input control means for sequentially connecting all information by connecting time division multiplexed signals including multiple channels to a pair of random access memories, and alternately writing and reading data to and from the pair of random access memories at regular intervals; A time slot switching circuit comprising: storage control means for repeatedly operating and storing data in a complementary manner; and output control means for separating the time-division multiplexed signal into low-speed data signal sequences of each channel.