JPH03196186A - Synchronizing signal inversion circuit - Google Patents

Abstract

PURPOSE:To eliminate a control terminal which instructs the signal polarity of a synchronizing signal from the outside and to automatically discriminate the signal polarity of the synchronizing signal by providing an EOR which inverts the synchronizing signal with the MSB of an up/down counter. CONSTITUTION:The circuit is equipped with the up/down counter 11 by which up-count and down/count are switched with the signal polarity of an inputted synchronizing signal. Furthermore, it is equipped with circuits 12-14 which control the Enable terminal of the up/down counter 11 with the overflow detection signal and the underflow detection signal of the up/down counter 11, and it inverts the synchronizing signal with the MSB output signal of the up/down counter 11 by using the EOR 16. In such a way, it is possible to eliminate the control terminal which instructs the signal polarity of the synchronizing signal from the outside, and to discriminate the signal polarity of the synchronizing signal in the inside.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a circuit for inverting the signal polarity of horizontal and vertical synchronizing signals in a controller (control circuit section) of a CRT and liquid crystal panel of a personal computer or the like.

2. Description of the Related Art In recent years, with the rapid spread of personal computers, the use of liquid crystal panels and the like in display devices has also increased.

Regardless of whether a CRT or a liquid crystal panel is used for the display, the control standards are two synchronization signals: a vertical synchronization signal (hereinafter abbreviated as VSYNC) and a horizontal synchronization signal (hereinafter abbreviated as H3YNC). .

These VSYNCs in normal television signals.

H8YNC is standardized as a negative logic signal, but depending on the model of a personal computer, these signals may be used as a positive logic signal. Therefore, in a circuit that controls a CRT or liquid crystal display, the signal polarity of these synchronizing signals must be inverted as necessary to match the synchronizing signal polarity specification of the control circuit, and subsequent digital processing must be performed.

A conventional synchronous signal inversion circuit will be explained below.

FIG. 3 is a circuit diagram of a conventional synchronous signal inversion circuit, with 23
is a vertical synchronization signal input terminal, 24 is a horizontal synchronization signal input terminal, 25 is a vertical synchronization signal polarity control terminal (CONTV),
26 is a horizontal synchronization signal polarity control terminal (CONTH), 2
1.22 is FOR (exclusive OR), 27 is a vertical synchronizing signal output terminal, and 28 is a horizontal synchronizing signal output terminal.

The operation of the synchronization signal inversion circuit configured as described above will be explained below.

The polarity control terminals C0NTH and C0NTV are set by an external microcomputer, etc., and the control circuit section does not discriminate the signal polarity of the input synchronization signal.
The logic of the synchronization signal was inverted as controlled by NTV and C0NTH. In other words, when the digital processing of the control circuit unit processes VSYNC as negative logic, when inputting positive logic VSYNC to the vertical synchronization signal input terminal from the outside, the vertical synchronization signal polarity control terminal (CON T V
) is set to H level to reduce the V used in the control circuit.
SYNC can be a negative logic.

By using this synchronization signal inversion circuit in the synchronization signal input circuit part of the control circuit section of a CRT or liquid crystal display, the synchronization signal inputted from the outside to the control circuit section can be input to the control circuit regardless of whether it is a negative logic or a positive logic. The same processing was achieved.

Similarly, logic setting for H8YNC is performed using C0NTH.

Problems to be Solved by the Invention However, in the above conventional configuration, the C0NT
It is necessary to input the polarity control signals of V and C0NTH,
Two terminals are required, and in order to control these terminals,
The problem was that the microcomputer had to take on that role.

The present invention solves the above-mentioned problems of the conventional technology.
It is an object of the present invention to provide a synchronization signal inversion circuit that can eliminate the polarity control terminal of a TV and C0NTH and automatically determine the signal polarity of a synchronization signal input from the outside in a control circuit section.

Means for Solving the Problems To achieve this object, the synchronous signal inversion circuit of the present invention includes an up-down counter, a counter control circuit controlled by an overflow/underflow detection circuit of the up-down counter, and an MSB of the up-down counter. It consists of a FOR that inverts the synchronization signal with the signal.

Effect: With this configuration, the signal polarity of the input synchronization signal can be automatically determined without using an external control signal.
The signal polarity can be inverted to a signal logic that matches the specifications of the control circuit section.

EXAMPLE An example of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of a synchronous signal inversion circuit in one embodiment of the present invention.

In Figure 1, 11 is an up-down counter 12
13 is an overflow detection circuit, 14 is an underflow detection circuit, 15 is a clock frequency dividing circuit, and 16 is an EOR.

17 is a synchronization signal input terminal, and 18 is a clock input terminal.

FIG. 2 shows a circuit diagram of the counter control circuit 12 in FIG. 1.

In FIG. 2, 121 is a synchronization signal input terminal, 122 is a latch clock input terminal, 123 is an overflow detection signal input terminal, 124 is an underflow detection signal input terminal, 125 is a counter control circuit output terminal, and 126 is an overflow detection signal input terminal.
is an inverter, 127 is a D flip-flop, 128,
130 is a NOR gate, and 129 is an AND gate.

The operation of the synchronizing signal inversion circuit of this embodiment configured as described above will be explained below.

In general, there is a difference of about 10 times between the L level period and the H level period of the synchronizing signal for both VSYNC and H8YNC.

For example, with a clock signal of a certain reference frequency, the L of the synchronization signal
Counting the widths of the level and H level, in the case of a negative logic synchronization signal with negative logic, if the L level section is 100 clocks wide, the H level section will be approximately 1000 clocks wide. Utilizing this property, the up/down counter is operated as an up counter during the L level section of the synchronizing signal, and as a down counter during the H level section. Then, in the case of a negative logic synchronization signal, since the H level is longer, the value of the up/down counter counts down toward O during the H level section of the synchronization signal. When the underflow detection circuit detects that the output of the up/down counter becomes 0, it sets the output of the underflow detection circuit to H level. That is, it is assumed that the underflow detection circuit is constituted by a large-power NOR gate that receives the output signal of the up-down counter.

The counter control circuit 12 in FIG. 1 can be realized by the circuit shown in FIG. As shown in FIG. 2, when the underflow detection signal 124 becomes H level during the H level period of the synchronization signal, the output 125 of the counter control circuit in FIG.
Next up/down counter 11 in Figure 1 is Disa.
ble, and the countdown stops. Therefore, the value of the up/down counter counts down during the H level period of the synchronization signal, and is held when it reaches 0.

Next, when the synchronization signal reaches the L level period, the up/down counter starts counting up. Here, the relationship between the bit length of the up-down counter and the count clock signal is determined in advance by the shorter pulse width of the synchronization signal (
If the count value is set to be less than (201)/2 (n is the bit length of the up/down counter) even if the count value is (201)/2 or less (n is the bit length of the up/down counter), the counter will be 0 during the L level interval. Since the count value does not exceed (2n-1)/2 even if the count is increased from
B remains at L level.

Even if we take the FOR of this MSB output signal and the synchronization signal,
Since the SB output signal is at L level, the synchronization signal is not inverted and is transmitted to the subsequent control circuit section as a negative logic signal.

Also, when the synchronization signal is positive logic, the H level pulse width is short and the L level pulse width is long, so the up/down counter counts up during the L level period and all bits of the counter become 1. Count up to. Here, it is assumed that the overflow detection circuit sets the output of the overflow detection circuit to L level when all the outputs of the up/down counters become 1. That is, it is assumed that the circuit is composed of a multi-input NAND circuit that receives the output signal of an up-down counter.

When the output of the overflow detection circuit 13 becomes L level, the input terminal 123 of the counter control circuit in FIG. 2 becomes L level, the output terminal 125 becomes L level, and the first
By setting the Enable terminal of the up counter 11 in the figure to L, counting up is stopped, and all outputs of the up/down counter are held at 1.

Next, when the synchronization signal becomes H level, the Enable terminal of the up/down counter becomes H level and starts counting down. However, since the relationship between the bit length and the clock signal is determined so that the count value during the H level period is less than (20-1)/2, the MSB of the up/down counter holds the H level and changes to the L level. It won't happen. Up-down counter MS
Since B is H, the synchronization signal is inverted by EOR, and the synchronization signal that was input at positive logic becomes negative logic and is transmitted to the subsequent control circuit section.

As described above, this embodiment includes an up-down counter that switches between up-counting and down-counting depending on the signal polarity of the input synchronization signal, and further connects the Enab Ie terminal of the up-down counter to the up-down counter's Enab Ie terminal. Equipped with a circuit that is controlled by an overflow detection signal and an underflow detection signal, and configured to invert the synchronization signal using EOR based on the MSB output of the up/down counter, it is possible to use a control terminal for externally instructing the signal polarity of the synchronization signal. The signal polarity of the synchronization signal can be determined internally.

Effects of the Invention The present invention controls an up-down counter that switches between up-counting and down-counting depending on the signal polarity of an input synchronization signal, and an enable terminal of the up-down counter by overflow detection and underflow detection of the up-down counter. By providing a circuit and an EOR that inverts the synchronization signal using the MSB of the amplifier down counter, it is possible to eliminate the control terminal that instructs the signal polarity of the synchronization signal from the outside. It is possible to realize an excellent synchronous signal inversion circuit that can reduce the burden on the microcomputer that controls the terminals.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a synchronous signal inversion circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram of an embodiment of the counter control circuit of FIG. 1, and FIG. 3 is a block diagram of a conventional synchronous signal polarity inversion circuit. It is a block diagram. 11...Up/down counter (n bits)
, 12... Counter control circuit, 13...
... Overflow detection circuit, 14 ... Underflow detection circuit, 15 ... Clock frequency division circuit, 16 ... EOR (exclusive OR), 17 ...
... Synchronous signal input terminal, 18 ... Clock input terminal, 19 ... Synchronous signal output terminal.

Claims (1)

[Claims] an up-down counter that performs up-counting or down-counting depending on the signal polarity of an input synchronization signal; an overflow detection circuit and an underflow detection circuit that detect overflow or underflow of the value of the up-down counter; and the overflow detection circuit. and a counter control circuit that controls the operation of the up-down counter based on the output of the underflow detection circuit, and an EOR (exclusive OR) that inverts the input synchronization signal using the MSB output signal of the up-down counter. A synchronous signal inversion circuit featuring: