JPH03192425A - Disk driving device - Google Patents

Abstract

PURPOSE:To suppress the influence of malfunction to a minimum and to improve the reliability of a disk driving device by synchronously operating plural microprocessors, executing the same program, collating results and suppressing write to a disk when the collated results are discordant. CONSTITUTION:Two microprocessors 23-1 and 23-2 are synchronously operated and execute the same program. At a data write cycle, a discordance detection circuit compares the data and the addresses respectively outputted from the two microprocessors 23-1 and 23-2 and generates a data write inhibiting signal 110 in the case of discordance. When the write inhibiting signal 110 is at a low level, a write inhibiting circuit 25 masks a write strobe signal and inhibits a data write operation at the relevant cycle. Thus, since the microprocessor is duplexed and the malfunction of the microprocessor is detected early, the influence of the malfunction can be suppressed to a minimum.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to increasing the reliability of disk drives such as magnetic disk drives and optical disk drives that incorporate a microprocessor.

[Conventional technology]

Conventionally, a disk drive device consists of a mechanism control section, a data writing circuit, and a data reading circuit, and has only the basic functions of rotating the disk, controlling the actuator to move the head, and reading and writing data. However, as the capacity of disks has increased and as a result of the pursuit of improved throughput and higher functionality, microprocessors have come to be built into disk drives in order to achieve these functions in a compact and low-cost manner. The configuration of a disk drive device incorporating a microprocessor is described, for example, in Nikkei Electronics, February 9, 1989 issue, pages 211 to 221.

Furthermore, a method for improving throughput by incorporating a write data buffer memory and a read data buffer memory in a disk drive device is described in the Journal of the Institute of Electronics and Communication Engineers, November 1984 issue, pages 1301 to 1308. Among these, the read data buffer memory is RP.
S (RotationalPos7'1tion
(Sensing) It prevents a drop in throughput due to mistakes and also has the characteristics of a cache memory.

FIG. 7 shows a block diagram of a conventional disk drive device.

In FIG. 7, l is a host controller, and the host computer may also serve as this function. The disk drive is connected to the control bus 101 by the interface circuit 2.
Connected to the upper controller 1 via the controller for seeking and data writing.

Receives and executes commands such as reading data.

Reference numeral 23 denotes a control microprocessor built into the disk drive, which interprets commands received via the interface circuit and controls various parts within the disk drive. Specifically, spindle motor control/drive circuit 1
5, the rotation of the disks 19 and 20 is controlled, and the actuator position is controlled based on the output of the servo data reading circuit 17. Further, a head switching circuit selects a head, controls a write data buffer memory and a read data buffer memory, and controls writing and reading of data to and from the disk.

[Problem to be solved by the invention]

An object of the present invention is to improve the reliability of a disk drive device incorporating a microprocessor. Therefore, we will discuss the issues with conventional disk drives from the perspective of reliability.

In a disk drive that does not have a built-in microprocessor and has only basic functions, seek operation errors can be detected by checking the ID of the read data, and data errors can be detected within the disk drive or by the upper host. It can be detected and corrected by the controller. Therefore, there is a very small possibility that erroneous data due to a malfunction of the disk drive device will be used as is by the host computer.

However, in a disk drive device that includes a built-in microprocessor, write data buffer memory, and read data buffer memory, the reliability of the microprocessor is extremely important in maintaining the reliability of the disk drive device. For example, in FIG.
However, the command from the upper controller 1 was misinterpreted,
Executing a read command as a write command will destroy the data stored on the disk. Also, write data buffer memory 3. The read data buffer memory 4 is also controlled by the microprocessor 23. The microprocessor 23 has a control table and controls the buffer memory.
If there is an error in reading or writing data to the control table at this time, there is a high possibility that the wrong data will be sent to the higher-level controller or written to the disk, and these malfunctions will be detected by higher-level devices such as the higher-level controller. This can be difficult.

As mentioned above, in order to achieve high reliability in disk drives, it is desirable to eliminate malfunctions of the built-in microprocessor, but in addition to the possibility of failure, there is a reduction in margin due to deterioration. Malfunctions can occur accidentally due to noise on the power supply, noise on signal lines, or even alpha radiation, and it is impossible to eliminate malfunctions in microprocessors. Therefore, it is important to detect microprocessor malfunctions early and reliably and to minimize the effects of malfunctions in order to achieve high reliability of disk drive devices, and this is also the purpose of the present invention.

[Means to solve the problem]

In order to achieve the object explained above, in the present invention, (D) a plurality of microprocessors are operated synchronously,
The same program is executed and the results are compared, and if the comparison results do not match, writing of the results to the control system is prohibited, writing to the disk is also inhibited, and a means of notifying the upper controller is provided (for example, interrupt means). Or as status information (6).

■ A means is provided for three or more microprocessors to operate synchronously and execute the same program to determine the result by majority vote, and if the result cannot be determined by majority vote, writing of the result is prohibited and writing to the disk is inhibited. A means for notifying the upper controller is provided.

■ Even if the outcome can be determined by majority vote,
If all the results do not match, a means is provided for identifying a microprocessor that outputs a result different from the result determined by majority logic and notifying the upper controller;
Furthermore, a memory for storing the identification results and a means for reading the memory from the host controller are provided.

(2) A diagnostic mode is provided in the disk drive device, and in the diagnostic mode, the output values from each microprocessor are intentionally made different, thereby making it possible to diagnose the tif[4dJf$f, discrepancy detection function, or majority circuit.

[Effect]

Since it is extremely rare for two microprocessors to malfunction at the same time and output the same data as a result of malfunction, it is possible to detect almost all malfunctions, and if the results do not match, prohibit writing of the results. Since writing to the disk is inhibited, the effects of microprocessor malfunction can be minimized.

Furthermore, by multiplexing three or more microprocessors,
Even if one of the microprocessors malfunctions, it is possible to continue operating as a disk drive by determining the output by majority vote. In addition, the host controller reads out the identification results stored in memory and uses statistical methods to detect malfunctioning microprocessors, as well as microprocessors that frequently malfunction. , between the outputs of multiple microprocessors contained in a disk drive.

Since it is possible to intentionally cause a mismatch, it is possible to diagnose the mismatch detection circuit, the majority decision circuit, and the processing function associated with mismatch detection.

〔Example〕

A first embodiment of the present invention will be described using FIGS. 1 to 6.

In FIG. 1, reference numeral 1 denotes a host controller for controlling a disk drive device, and a host computer may also have this function. Reference numeral 2 denotes an interface circuit on the disk drive side, which receives commands from the higher-level controller 1 via the control bus 101, and also exchanges data and status with the higher-level controller 1. 19
．． 20 is a disk on which information is recorded, 16 is a spindle motor for rotating the disk, IS is a control/drive circuit for the spindle motor, 11.13 is a magnetic head for writing and reading data, 14 is a servo A magnetic head for reading control data, 9 an actuator drive motor for driving the actuator on which the magnetic heads 11, 13 and 14 are mounted, 8 an actuator motor control/drive circuit, and 7 a head selector for switching. A head switching circuit, 5 a data write circuit consisting of a modulation circuit, a write amplifier, etc., 6 a data read circuit consisting of a read amplifier, a pulsing circuit, a demodulation circuit, etc., 3 a write data buffer memory for temporarily storing write data. , 4 is a read data buffer memory for temporarily storing read data, 23-1
．． 23-2 is a control microprocessor that operates synchronously, 21 is a tarlock generator that generates a clock to be supplied to the microprocessor, and 22 is for establishing and maintaining synchronization between the two microprocessors 23-1 and 23-2. 24 is a synchronous control circuit for microprocessors 23-1 and 2
This is a mismatch detection circuit that compares the data output from the two microprocessors and the address in the data write cycle 3-2, and generates a mismatch flag and a data write inhibit signal if they do not match.

In FIG. 1, microprocessor 23-1゜23-
2 receives commands from the host controller 1 via the control bus 101 and the interface circuit 2, interprets the received commands, and sends them to the spindle motor control/drive circuit 15.゛Actuator motor control/drive circuit 8, head switching circuit 7゛Write data buffer memory 3
．． Commands are executed while controlling necessary parts such as the read data buffer memory 4.

Here, the two microprocessors 23-1 and 23-2 operate synchronously at the bus cycle, that is, machine cycle level, and execute the same program. Synchronous control circuit 2
Reference numeral 2 denotes a circuit for establishing synchronization when the two microprocessors start operating and maintaining synchronization thereafter, and its output 105 is commonly input to the two microprocessors.

FIG. 2 shows the circuit configuration of the synchronous control circuit 22. In FIG. 2, 30 is a reset control circuit that controls the timing of the reset signal supplied to the microprocessor, 31 is a latch circuit that latches interrupts input to the microprocessor, and 32 is a latch circuit that latches data read by the microprocessor. FIG. 3 is a timing chart for explaining the operation of the circuit shown in FIG. 2. A microprocessor normally starts operating when a reset signal input to the microprocessor is released. At this time, if the reset signal 105-2 is released with sufficient centamp time and hold time with respect to the clock 105-1 commonly supplied to the two microprocessors, the two microprocessors will operate at the same timing. Since the operation starts, synchronization at the start of operation is established. The reset control circuit 30 receives a clock 104 generated by the clock generator 21, a reset signal 103-1 whose timing relationship with the clock 104 is not guaranteed, and a clock 105-1 which is commonly supplied to the two microprocessors. A reset signal 105-2 having a sufficient set-up time and hold time for the reset signal 105-1 is output.

Next, factors that break down established synchronization include interrupts that are input asynchronously to the clock supplied to the microprocessor, and setup time for the microprocessor's read strobe.

There is read data for which the hold time is insufficient.

If two microprocessors accept interrupts in different machine cycles, synchronization will be lost, so each interrupt must be input to the microprocessor with sufficient setup time and hold time relative to the clock 105-1. The latch circuit 31 latches interrupts whose timing relationship is not guaranteed with respect to the clock at the timing of the clock 105-1, and secures sufficient setup time and hold time with respect to the clock 105-1 so that the microprocessor 23-1.23 -2. Additionally, if the read data set-up and hold times are not sufficient for the microprocessor's read strobe, two microprocessors may read different data in the same read bus cycle, causing synchronization to break down. . Such a thing can occur, for example, in a flag sensing operation. The latch circuit 32 once latches such data at the leading edge of the read strobe 222, and stores it as read data 105-5 and 105-6 for which sufficient setup time has been secured for the read strobe 222.
microprocessors 23-1 and 23-2.

As described above, the synchronization control circuit 22 can establish and maintain synchronization between the two microprocessors 23-1 and 23-2.

Next, the operations of the mismatch detection circuit 24 and the write inhibit circuit 25 in FIG. 1 will be explained using FIGS. 4 and 5.

In FIG. 4, 40 is a comparator that compares the data and address of the output bus 108 of the microprocessor 23-1 and the data and address of the output bus 109 of the microprocessor 23-2, and if they match, sets the output 110 to high level. The circuit 41 is an AN for masking the write strobe signal 251 and inhibiting data write operation in the cycle when the write inhibit signal 110 is at a low level, that is, when the data or addresses output by two microprocessors are different. D gate 45 forms a self-hold circuit with an OR gate 43, a flip-flop for storing the occurrence of a mismatch and outputting a mismatch occurrence flag 111, 44 a write strobe 244 from the microprocessor 23-1 and the microprocessor 23
-2 and the write strobe 245 and supplies it to the flip-flop 4S as a clock 246.

Note that the flip-flop 45 is cleared to zero by the clear signal 247 in the initial state. The circuit described above operates as shown in the timing chart shown in FIG. In other words, when a mismatch occurs in data or address in a write bus cycle, the output 110 of the comparator becomes low level, the write strobe is masked and data write operation in that cycle is prohibited, and the flip-flop is activated at the timing of the trailing edge of the write strobe. 45 is set to 1 and the mismatch occurrence flag 111
becomes 1.

The write inhibit circuit shown in FIG. 4 described above is effective if the write data set-up time is sufficiently guaranteed for the leading edge of the write strobe, but it is effective for the trailing edge of the write strobe. Unable to mask light strobe.

In such a case, the write strobe can be masked by the circuit shown in FIG. The operation of the circuit shown in FIG. 12 will be explained below using the timing chart shown in FIG. 13. In FIG. 12, 80 is a latch, which launches the address and write data of the microprocessor bus using the write strobe 251. 81 is a delay circuit, 8
2 is an inverter, and a write strobe 252 is used to write the write data 254 latched from the write strobe 251 to the latch 80 by the AND gate 41.
Create. At this time, the width of the write strobe 252 is determined by the delay time in the delay circuit 81. Also, AND gate 4
1 has a function of masking the write strobe by the mismatch signal 255 latched in the launch 80. According to the circuit shown in FIG. 12, since the write 1 data is once latched and then written, the set-up time and hold time of the write 1 data are guaranteed for a microprocessor with respect to the trailing edge of the write strobe. You can mask the light strobe without any problem.

Next, with reference to FIG. 6, the operation of the disk drive device shown in FIG. 1, including its relationship with a host controller, will be explained. First, the upper controller sets a command to the disk drive and starts it.

When the disk drive is activated, the microprocessor interprets the received commands, controls each part, and executes the commands. During this process, if a mismatch occurs between the data or addresses output by the two microprocessors, the operation of the disk drive is frozen, as explained above, and the host controller is notified as an interrupt caused by the mismatch. If it is possible, the upper controller performs recovery processing, sets a 1-write command, and starts the disk drive. If the retry is not possible, necessary processing such as initialization of the disk drive device is performed, and if the number of retries exceeds the allowable number of times, the disk drive device is regarded as having failed and measures such as disconnection are taken.

As described above, as a first embodiment of the present invention, in a disk drive device incorporating a microprocessor, the microprocessor is duplicated, a malfunction of the microprocessor is detected early and reliably, and the influence of the malfunction is minimized. This article has described a disk drive device that achieves high reliability through this.

However, although reliability is greatly improved in the first embodiment,
If the microprocessor malfunctions, it freezes the operation of the disk drive and leaves the processing to a higher-level controller, which has a large impact on the system and may make recovery processing difficult. Therefore, in order to solve these problems, a second embodiment in which the microprocessors are triplexed will be described below.

FIG. 8, FIG. 9, and FIG. 10 are diagrams explaining a second embodiment of the present invention. FIG. 8 is a diagram showing the configuration of a disk drive device according to a second embodiment of the present invention, FIG. 9 is a diagram showing an example of the configuration of the majority circuit in FIG. 8, and FIG. 10 is a diagram showing the control signals in FIG. 9. FIG. 3 is a diagram showing the input/output relationship of the generating circuit. In FIG. 8, 23-1, 23-2, 23-3 are microprocessors that operate synchronously, 26 is a write cycle of the microprocessors, and data output from each microprocessor is compared with an address. The write data and address are determined by majority vote. If it cannot be decided by majority vote, an error flag and data write prohibition signal are generated. If it can be determined by majority vote but not everything matches, the data and address selected by majority vote are 27 is an error logging memory that stores the identification results output from the majority circuit 26 and can read the contents from the host controller. . The operation of the disk drive device of the second embodiment is basically the same as that of the first embodiment, but since the microprocessors are triplexed, even if one microprocessor malfunctions, the disk drive The drive can continue to operate and is frozen only when two or more microprocessors malfunction. Next, the circuit configuration and operation of the majority circuit 26, which is characteristic of the second embodiment, will be explained.

In FIG. 9, 40-1 is the microprocessor 23-
Comparator 4o-2 compares the data and address of output bus 108-1 of microprocessor 23-2 with the data and address of output bus 108-2 of microprocessor 23-2, and if they match, sets output 261 to high level. A comparator 40-3 compares the output of the microprocessor 23-1 and the output of the microprocessor 23-3;
A comparator 62 that compares the outputs of the three comparators 261, 262 and 263 inputs the output bus selection signal 269 of the selector 61 according to the table shown in FIG. 121. Identification code of the malfunctioning microprocessor when one unit malfunctions 122.
A control signal generation circuit 61 generates a signal 270 indicating that one unit has malfunctioned, according to the output bus selection signal 269,
a selector 63 that selects the output bus 108-2 of the microprocessor 23-2 when only the microprocessor 23-1 malfunctions, and selects the output bus 108-1 of the microprocessor 23-1 for output in other cases; is O
The R gate 66 forms a self-hold circuit, and the flip-flop 64 stores malfunctions of two or more units and outputs an error flag 123. The OR gate 64 forms a self-hold circuit, and one malfunction occurs. A flip-flop 65 stores and outputs a flag 124 indicating that one unit malfunctions, and a timing 268 is set to two flip-flops 63 and 64 by ANDing data strobes from three microprocessors. This is a NAND gate to give .

Next, the operation of the majority circuit 26 will be explained in relation to the operation of the disk drive device. If the outputs of the three microprocessors that operate synchronously all match, the outputs 261, 262, and 263 of the three comparators will all be 1, so the outputs 269, 12 of the control signal generation circuit 62
1, 122, and 270 are all O, and the disk drive operates normally. If only one microprocessor malfunctions, the outputs of two comparators to which the outputs of the malfunctioning microprocessor are inputted among the outputs of the three comparators become 0. The relationship between the malfunction status of the microprocessor and the output of the comparator is as shown in the table in FIG. Outputs the processor identification code. Since 270 becomes 1, the flip-flop 64 is set to 1,
The flag 124 notifies the - controller 1 as a status signal that there is a malfunction in one unit. Further, the selector 61 selects the output of a normal microprocessor. At this time, is the identification code of the malfunctioning microprocessor stored in the error logging memory 27? 77 Be M. On the other hand, the signal 121 indicating the malfunction of the second metal fitting 1- is O
Therefore, the operation of the disk drive continues.

Furthermore, if two or more microprocessors malfunction, the outputs of all three comparators will become O, so the signal 121 indicating malfunction of two or more microprocessors will become 1, and the write inhibit circuit 25 will block the data in that cycle. Writing is prohibited. Furthermore, since the flip-flop 63 is set to 1, the write operation to the disk is inhibited.
The upper controller is notified by an interrupt, and the three microprocessors are also stopped by the interrupt. These operations when two or more microprocessors malfunction are as follows:
The operation is the same as in the first embodiment when a mismatch occurs between the outputs of the two microprocessors.

The disk drive devices according to the first embodiment and the second embodiment each have a function for diagnosing a discrepancy detection circuit and a majority decision circuit. FIG. 11 is a diagram showing the diagnostic procedure from the upper controller. To make a diagnosis, first -
Set a diagnostic command from the upper controller and start the disk drive. When a plurality of microprocessors in a disk drive receive a diagnostic command, each microprocessor executes a different diagnostic program. The diagnostic program is configured so that only the output data or addresses do not match without breaking the synchronization of the plurality of microprocessors, and generates a desired mismatch pattern. As a result, a data or address mismatch occurs, so the upper controller receives an interrupt from the disk [J] device,
Alternatively, it is sufficient to wait for the status and check whether a predetermined response or processing has been performed.

[Effects of the Invention] As explained in 1- below, according to the present invention, almost all malfunctions of the microprocessor can be detected in a disk drive device incorporating a microprocessor.
The reliability of disk drives is greatly improved.

Further, by providing a majority circuit, high reliability can be achieved and the availability rate can be increased at the same time.

Furthermore, maintainability is improved by storing the identification code of the malfunctioning microprocessor in the error logging memory.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a disk drive device according to the first embodiment of the present invention, FIG. 2 is a diagram showing the circuit configuration of the synchronous control circuit in FIG. 1, and FIG. 3 is the circuit shown in FIG. 2. 4 is a diagram showing the circuit configuration of the mismatch detection circuit 24 and write inhibit circuit 25 in FIG. 1, and FIG. 5 is a diagram showing the operation of the circuit shown in FIG. 4. A diagram showing a timing chart for explanation,
61★1 is a diagram showing a flowchart for explaining the operation of the disk drive device shown in FIG. 1, FIG. 7 is a diagram showing the configuration of a conventional disk drive device, and FIG. FIG. 9 is a diagram showing the circuit configuration of the majority circuit in FIG. 8,
10 and 11 are flowcharts for explaining the diagnostic procedure of the disk drive device according to the present invention, FIG. 12 is a diagram showing one circuit configuration in which the write-only protection circuit 2 is disabled, and FIG. FIG. 3 is a diagram showing a timing chart for explaining the operation of the circuit shown in the figure. DESCRIPTION OF SYMBOLS 1... Upper controller 2... Interface circuit, 3... Write data buffer memory, 4... Read data buffer memory, 5... Data write circuit, 6... Data read circuit, 7 . . . Head switching circuit, 8 . . . Actuator motor control/drive circuit, 21 . . . Clock generation circuit, 22 . ...Write-protected circuit, 26...
- Majority circuit, 40... Comparator, 61... Selector, 62 - Control signal generation circuit, 80... Latch, 8
1...Delay circuit.

Claims (1)

[Claims] 1. In a disk drive device incorporating a microprocessor, a plurality of microprocessors that operate synchronously at the bus cycle level and execute the same program, and synchronization between the plurality of microprocessors is established and maintained. and in a data write cycle of the plurality of microprocessors,
A means for comparing and detecting the write data output from the plurality of microprocessors and a means for comparing and detecting the write destination address, and if there is a mismatch between the comparison results, prohibiting writing of the write data to the disk drive device. and means for notifying a host controller that there is a discrepancy in the comparison results. 2. A disk drive device characterized in that a majority logic means is added to the plurality of microprocessors. 3. The disk drive device according to claim 2, further comprising means for detecting a mismatch state when there is no matching data or address. 4. The disk drive device according to claim 2, further comprising means for identifying a processor corresponding to mismatched data, memory means for storing the identification result, and means for transferring the information in the memory to the outside. Drive device. 5. A method for diagnosing a disk drive device according to claim 1, which comprises diagnosing the functions of the disk drive device according to claim 1 by causing the plurality of microprocessors to execute different diagnostic programs.