JPH03191518A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent a high melting point metal buried in a contact hole from being released to fall off by a method wherein the high melting point metal layer is buried in the contact hole on whose sidewall a conductor film or a semiconductor film is formed. CONSTITUTION:An interlayer insulating film 3 is formed on a semiconductor substrate 1 and then a contact hole 4 is made in the interlayer insulating film 3. A conductor film or a semiconductor film covering the sidewall of the contact hole 4 is formed and then a tungsten layer 7 as a high melting point metal to be an electrode is selectively deposited by chemical vapor deposition process in the contact hole 4 so as to be buried therein. At this time, since the contact hole 4 is exposed to the single crystal silicon of the polysilicon film 5 and the silicon substrate 1, the tungsten layer 7 is entirely in contact with the silicon in the contact hole 4 so that the bonding strength may be increased while lowering the resistance in comparison with the contact with the interlayer insulating film 3. Through these procedures, a high melting point metal buried in the contact hole 4 as a connecting electrode can be prevented from being released to fall off.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly relates to an electrode in a contact hole for connecting a conductor layer such as a wiring with low resistance, and a method for forming the same. .

[Conventional technology]

Integrated circuits formed on semiconductor substrates, especially silicon substrates, are becoming increasingly dense and highly integrated, and in particular, the density of MO9 type vertical memory devices is about to advance from 1Mbit to 4Mbit! /Xru. In order to increase the integration of such devices, from the viewpoint of cost and yield of chi-yl,
- The most effective method is to reduce the area occupied by each element.

1M Bi・7) RA in MO3 type static memory
In M, the occupied area per cell was 40 to 50 μm2, whereas in 4M and RAM, it was 15 to 25 μm.
m2 is required.

With the reduction in the area occupied by each cell, it is necessary to reduce the area occupied by the contact hole that electrically connects the wiring layers, and as the contact hole becomes smaller, the contact resistance increases. It becomes a problem. That is, in integrated circuit devices such as memory devices, high integration and high speed are required, and the increase in wiring and contact resistance as well as various capacitance components have a large negative effect on the operating speed.

Therefore, even if the contact hole becomes fine, it is required that the contact resistance be low.

While high speed is required, low power consumption is also required, so CMO8 is becoming more and more popular in semiconductor integrated circuits. Therefore, there is a need for a connection method between conductor layers that requires fewer steps and is compatible with CMO3.

As a method for connecting conductor layers that satisfies these three requirements at the same time, a technique is being considered in which a refractory metal is selectively buried as a connection electrode in a contact hole, as shown in FIG.

That is, an interlayer insulating film 3 is used to connect the N-type diffusion layer 2 formed on the silicon substrate 1 and the upper aluminum wiring 8.
A contact hole 4 is opened in the contact hole 4, and a metal such as tungsten 7 is selectively buried only in the contact hole 4 using a chemical vapor deposition technique that selectively grows only on the silicon substrate or wiring layer. be.

This method not only connects conductor layers with low resistance, but also flattens the layers at the same time, making it extremely effective as a connection technology between conductor layers in integrated circuits that are becoming smaller, more dense, and more highly integrated. .

In addition, in CMO3 type O3 circuits, it is also possible to connect N-type and P-type impurity diffusion layers in the same process, which reduces the number of processes and is extremely effective in reducing costs and improving yield. It is a method.

[Problem to be solved by the invention]

However, in the conventional connection method between conductor layers in which a high-melting point metal is buried, the adhesion between the insulating film on the side wall of the contact hole and the high-melting point metal is poor, and the high-melting point metal buried as a connection electrode in the contact hole peels off. There was a problem in that the conductor layer could be easily connected to the other conductor layers and the conductor layer could be easily connected to the conductor layer.

The main reason for this seems to be that no compound is formed between the silicon dioxide on the inner wall of the contact hole and the buried metal. For example, the coefficient of thermal expansion of tungsten and silicon dioxide is 4,5 x 10-
6T-1, whereas silicon dioxide has 0,4
Since it is X 10-6T-1, there is also a problem that these substances, which have weak chemical bonds, become more likely to separate when a thermal process is applied.

An object of the present invention is to provide a method of manufacturing a semiconductor device with high reliability and yield, which prevents the high melting point metal buried in such a contact hole from peeling off or falling off.

[Means to solve the problem]

A semiconductor device of the present invention includes an interlayer insulating film provided on a semiconductor substrate, a contact hole provided in the interlayer insulating film, a conductor film or a semiconductor film provided on a side wall surface of the contact hole, and a conductor film provided on a side wall surface of the contact hole. Alternatively, the contact hole may include a high melting point metal layer buried in the contact hole provided with a semiconductor film.

Further, the method for manufacturing a semiconductor device of the present invention includes a step of forming an interlayer insulating film on a semiconductor substrate, a step of forming a contact hole in the interlayer insulating film, and a conductive film or a semiconductor film covering the side wall surface of the contact hole. and a step of embedding a high melting point metal layer in the contact hole in which a conductive film or a semiconductor film is formed on the sidewall surface.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(e) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a first embodiment of the present invention.

First, as shown in FIG. 1(a), N
After forming the type diffusion layer 2, an interlayer insulating film 3 made of SiO is formed on the entire surface. Next, a contact hole 4 is formed in the interlayer insulating film 3 on the N-type diffusion layer 2 by a well-known lithography process and a reactive ion etching method.

Next, as shown in FIG. 1(b), a polysilicon film 5 is formed to cover the side wall surface of the contact hole 4.

The material to be formed may be any material as long as it has good adhesion to the interlayer insulating film, and tungsten silicide may be used.

The polysilicon M5 may be formed by sputtering, chemical vapor deposition, or the like. The film thickness is approximately 100 to 2000 without burying the contact hole 4. This polysilicon film 5 may be doped with impurities by a method such as ion implantation or diffusion. next,
The polysilicon film 5 is etched back to remove the polysilicon film 5 on the interlayer insulating film 3, leaving the polysilicon film 5 only on the side wall surface of the contact hole 4.

Next, as shown in FIG. 1(c), a high concentration impurity is introduced into the bottom of the contact hole 4 by ion implantation or diffusion to form an N+ type scattering layer 6. The concentration of impurities is 1020 ~
Approximately 8 x 1.021011-3 is desirable. This is because the higher the impurity concentration, the lower the resistance due to the Schottky barrier between the refractory metal formed in the contact hole and the N'' type diffusion layer 6 formed on the silicon substrate.

If the N+ type scattering layer concentration is 1021 cm4 or more, the contact resistance can be made 10-7Ω·cT112 or less. At this time, it is desirable that the polysilicon film 5 formed on the side wall surface of the contact hole 4 is also doped with impurities.

Next, as shown in FIG. 1(d), a tungsten layer 7, which is a high melting point metal, is selectively grown as an electrode in the contact hole 4 by chemical vapor deposition to fill the contact hole 4. Since the polysilicon film 5 and the single crystal silicon of the silicon substrate 1 are exposed inside the contact hole 4, the tungsten layer 7 is entirely in contact with the silicon inside the contact hole 4, and is bonded rather than being in contact with the interlayer insulating film 3. Strength is increased and resistance is reduced.

Next, as shown in FIG. 1(e), an aluminum wiring 8 is formed as an upper wiring.

As described above, according to the first embodiment, since the electrode made of tungsten layer 7 is well bonded to interlayer insulating film 3 via polysilicon film 5, it will not come off or come off.

FIGS. 2(a) to 2(e) are cross-sectional views of a semiconductor chip for explaining a second embodiment of the present invention.

First, as shown in FIG. 2(a), an N-type diffusion layer 2 is formed on a semiconductor substrate 1, and then a metal such as PT or 1゛i is formed, and then heat treatment is applied to form an N-type diffusion layer in a self-aligned manner. A metal silicide layer 9 is formed on the diffusion layer 2.

The N-type diffusion layer 2 is formed by introducing impurities into the metal silicide layer 9 by a method such as ion implantation after forming the metal silicide layer 9, and then heat-treating the metal silicide layer 9, which has a high impurity concentration, to introduce the impurity into the silicon substrate 1. The N-type diffusion layer 2 may be formed by diffusing .

Next, as shown in FIG. 2(b), a polysilicon film 5 is formed on the side wall surface of the contact hole 4 in the same manner as in the first embodiment.

When a gas such as CF4 is used for reactive ion etching of a polysilicon film, the etching speed is 3 to 10 times that of metal silicide. , since the metal silicide layer 9 at the bottom of the contact hole 4 can be left, the metal silicide layer 9 and the high melting point metal come into contact inside the contact, and the resistance is further reduced to 1/2 compared to the first embodiment.
There is also the advantage that the resistance value is reduced to about 0 to 115.

Next, as shown in FIG. 2(c), N-type impurities are doped into the metal silicide layer 9 by ion implantation or the like. The concentration is l Q 20 ~ I Q 22 co! -3 is sufficient. Then, heat treatment is performed to diffuse impurities from the metal silicide layer 9 into the silicon substrate to form an N+ type scattering layer 6. This step is carried out during the etching back of the polysilicon film 5.
If the metal silicide layer 9 remains, it may be omitted.

Next, as shown in FIG. 2(d), a high melting point metal as an electrode is selectively grown in the contact hole 4. Tungsten layer 7 is used as the high melting point metal.

Next, as shown in FIG. 2(e), an aluminum wiring 8 is formed as an upper wiring.

In the above embodiment, the case where the diffusion layer and the wiring layer are connected using an electrode made of a tungsten layer has been described, but the invention is not limited to this, and even if the connection is between diffusion layers or wiring layers. good. Further, although tungsten is used as the high melting point metal, other metals such as molybdenum may be used.

〔Effect of the invention〕

As explained above, the present invention has the effect that a semiconductor device with high reliability and high yield can be obtained by forming a conductive film or a semiconductor film with strong adhesive strength to the buried high melting point metal on the side wall surface of a contact hole. There is.

[Brief explanation of drawings]

1 and 2 are cross-sectional views of a semiconductor chip for explaining first and second embodiments of the present invention, and FIG. 3 is a cross-sectional view of a semiconductor chip for explaining a conventional example. l...Silicon substrate, 2...N-type diffusion layer, 3...
Interlayer insulating film, 4... Contact hole, 5... Polysilicon film, 6... N-type scattering layer 7... Tungsten layer, 8... Aluminum wiring, 9... Metal silicide layer.

Claims (1)

[Claims] 1. An interlayer insulating film provided on a semiconductor substrate, a contact hole provided in the interlayer insulating film, a conductor film or a semiconductor film provided on the side wall surface of the contact hole, and a conductor. and a high melting point metal layer buried in the contact hole provided with a film or a semiconductor film. 2. A step of forming an interlayer insulating film on a semiconductor substrate, a step of forming a contact hole in the interlayer insulating film, a step of forming a conductive film or a semiconductor film covering the side wall surface of the contact hole, and a step of forming a conductive film or a semiconductor film on the side wall surface. A method for manufacturing a semiconductor device, comprising the step of embedding a high melting point metal layer in the contact hole in which a conductive film or a semiconductor film is formed.