JPH03185545A - I/o control adaptor - Google Patents

Abstract

PURPOSE:To improve the efficiency of data transfer by switching whether data are to be transferred at a high speed or a low speed corresponding to devices connected to I/O devices based upon each device address. CONSTITUTION:The I/O control adaptor is provided with a control means 35 for switching rapid transfer and slow transfer in accordance with the address of each device at the time of switching rapid transfer or slow transfer to each device while allocating an address to each device in the case of data transfer to respective devices connected to the I/O devices and a buffer control means 33 for controlling the storage state of a buffer for temporarily storing transfer data. Rapid transfer is applied to a disk device connected to the I/O device and slow transfer is applied to devices other than the disk device. Thus, the rapid transfer of data or its slow transfer corresponding to each device connected to the I/O device is switched based upon the device address. Thus, the efficiency of data transfer for DMA transfer can be improved.

Description

[Detailed Description of the Invention] [Summary] A common bus that connects the central processing unit and system memory, and an input/output device (Ilo) that connects multiple I/O
I/O that controls the transfer of the corresponding I/O via the port
Regarding control adapters, the purpose is to improve data transfer efficiency between the common bus and I/O, and it is placed between the common bus that connects the central processing unit and system memory, and the I/O, and supports multiple l/○ ports. An I/O control adapter that controls the transfer of the corresponding I/O through the I/O, and in data transfer to each device under the I/O,
comprising a control means for assigning an address to each device and switching between high-speed transfer and low-speed transfer to each device according to the address of each device; and a buffer management means for managing the storage state of a buffer for temporarily storing transfer data; High-speed transfer is performed for the disk device under I/O,
Devices other than the disk device are configured to perform low-speed transfer.

[Industrial application field]

The present invention is an I/O control system that is placed between a common bus connecting a central processing unit and system memory and an input/output device (Ilo), and that controls the transfer of corresponding I/Os via multiple I/O ports. Regarding the adapter.

In recent years, the performance of information processing devices has improved significantly, and along with this, data transfer speeds have also become faster. Furthermore, the I/O bus has also been standardized, making it possible to connect different types of Ilo to the same I/O bus.

[Conventional technology]

A magnetic disk device, a magnetic tape (MT) device, a printer device, an optical disk device, etc. are connected to Ilo. Some of these devices require high-speed transfer and others require low-speed transfer. For example, a disk device requires high-speed transfer, and an MT device requires low-speed transfer.

Generally, an I/O control adapter is placed between the common bus and these devices via Ilo. The I/O control adapter is provided with an I/O port corresponding to each of the plurality of I/Os.

In such a configuration, control procedures during data reading and data writing are as follows.

When reading data for high-speed transfer ■ When the I/O control unit 31a is ready to read data, the buffer management unit 3 starts using the 4-word buffer 32.
Request 3.

(2) The buffer management unit 33 allows the use of the 4-word buffer if the 4-word buffer is empty and usable.

(2) The I/O control unit 31a stores data in a 4-word buffer.

(2) When the 4-word buffer is filled with data, the buffer management unit 33 requests the common bus management unit 11 to use the common bus through the common bus control unit in order to transfer the data to the common bus 5.

■When the common bus 5 becomes in use, the common path management unit 33 responds with permission to use the common bus.

■The common bus control unit 34 uses the common bus to
Four words are transferred in the MA cycle and the data is written to the system memory 2.

■Common bus H1 [111t4 Opens the word buffer and responds to requests from other I/O ports.

When writing data for high-speed transfer (2) When the I/O control unit 31a is ready to send (write) data to Ilo, it requests the buffer management unit 33 to use a 4-word buffer.

(2) When the 4-word buffer becomes usable, the buffer management section 33 requests the common bus management section 11 to use the common bus through the common bus control section.

■When the common bus becomes usable, the common bus management unit 11 responds with permission to use the common bus.

(2) The common bus control unit 34 controls the common bus to read data from the system memory 2 and store the data in a 4-word buffer. Incidentally, as in the case of reading, four words are fetched in one DMA cycle.

■When the buffer management unit 33 finishes storing data, the buffer management unit 33
/O Allows the control unit 31a to use the 4-word buffer.

(2) The I/O control unit 31a reads data from the 4-word buffer and transfers it to the I/O.

(2) The buffer management unit 33 releases the 4-word buffer and responds to requests from other I/O ports.

Note that during low-speed transfer, one word is transferred in one DMA cycle. Further, the 4-word buffer is operated when it is determined to be full when l words are included.

[Problem to be solved by the invention]

Usually, high-speed transfer refers to nibble transfer, and in this transfer, once the right to use the common bus is acquired, four words are transferred in one normal cycle. When attempting to transfer 4 words, it is necessary to have a data buffer for 4 words (the 4 word buffer described above), but this 4 word buffer is shared by multiple I/O ports.
In the case of low-speed transfer where the transfer speed of /O is slow, the acquisition time (occupation time) of the 4-word buffer becomes long. If this state continues, other I/O boats will become unusable, resulting in a decrease in transfer efficiency.

An object of the present invention is to improve data transfer efficiency by switching each device under I/O to perform high-speed transfer or low-speed transfer, and to perform this switching using a device address.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle configuration of the present invention. The present invention is arranged between a common bus (5) connecting a central processing unit (1) and a system memory (2) and an input/output device (Ilo),
An I/O control adapter that controls the transfer of corresponding I/O via multiple I/O boats, and when transferring data to each device under the I/O, assigns an address to each device and control means (35) for switching between high-speed and low-speed transfer according to the address of each device;
and buffer management means (33) for managing the storage state of a buffer that temporarily stores transfer data, performs high-speed transfer to the disk device under the I/O, and transfers data to other devices other than the disk device. It is characterized by low-speed transfer.

[Effect]

In the present invention, data transfer efficiency in DMA transfer is improved by switching between high-speed and low-speed data transfer for each device under I/O and performing this switching based on the device address. It is something.

〔Example〕

FIG. 2 is a configuration diagram of an embodiment of the present invention. The I/O control adapter 3 includes a plurality of I/O control units 313 to 31n that perform input/output control of each device under the connected I/O, a 4-word buffer 32, and input/output management and storage for the 4-word buffer 32. A buffer management section 33 that manages the state, a common bus control section 34, a DMA control section 35 that performs DMA control of the 4-word buffer 32, each I/O control section 31a to 31n, and a microprocessor (MPU) 36. has. In addition, l/O-#0. l/O1t1. -1/O-#
n, etc. are disk devices, MT devices, etc. under I/O.

The transfer mode of each 1/O is assigned by an address given to each device, and when configuring the system, an address determined according to the transfer speed of the connected I/O is assigned. For example, Ilo #7 to #3 → high-speed transfer I/O #2 to #0 → low-speed transfer Therefore, for example, when connecting a disk device, addresses #7 to #3 for high-speed transfer are allocated.

FIG. 3 is an explanatory diagram of the signal system in FIG. 2. The functions of each part will be explained in detail below.

The I/O control unit 31a controls the I/O control unit 31a when the DMA start
When a data transfer request is generated from lo, it sends a BFREQ 1 signal requesting buffer use to the buffer management unit 33, and further sends a DREQ 1 signal requesting DMA control to the DMA control unit 31a.

When the DMA control unit 31a receives the DREQ signal, the DMA control unit 31a outputs a BFA indicating permission to use the buffer from the buffer management unit 33.
Confirm that the CK signal and data transfer amount (L[EN) are not "O", and when the 4-word buffer is empty (EMP) when reading, and when the 4-word buffer is full (FULL) when writing. , are ANDed with the above-mentioned confirmations and output the DACK signal to the I/O control unit 31.
Send DMA transfer to a.

Therefore, when reading, data is written to the 4-word buffer, and when writing, data is written to the I/O control unit 31a.

The DMA control unit 35 controls transfer between all I/Os and the 4-word buffer, and determines the I/O control unit to which data should be transferred based on the BFACK signal.

The buffer management unit 33 manages the use of the 4-word buffer and its storage status (full/empty), and controls the I/O
Based on the BFREQ signal generated from the control section, a buffer use conflict is determined and permission to use the 4-word buffer is allocated. In addition, buffer full/empty management is
During high-speed transfer, it becomes full when 4 words are input,
During low-speed transfer, it becomes full when one word is input.

When the 4-word buffer is used by any I/O control unit, the common bus control unit 34 issues a request to use the common bus of the common bus management 8Bll when the 4-word buffer is full when reading, and when the 4-word buffer is empty when writing. DM with system memory
Perform A transfer.

Referring to FIG. 3, the procedure for reading data in high-speed transfer according to the present invention will be explained in more detail.

■When I/O control becomes necessary, the CPU
A read command is issued to the O control adapter 3, for example, a read command for Ilo #7 of the I/O control unit 31a.

(2) The MPU 36 in the I/O control adapter 3 analyzes this read command and determines that read processing using high-speed transfer is requested based on the device address.

(2) The MPU controls the I/O control unit 31a to enable data transfer.

(2) When Ilo becomes ready for data transfer, the MPU activates the I/O control unit to DMA. Furthermore, the control register 37 contains the transfer amount (IP:N) and transfer mode (MOD).
E), direction (DIR), etc. In addition, multiple I
Since the /O control units operate simultaneously, the control register 37 sets the transfer amount, transfer mode, direction, etc. for each I/O control unit to select one.

■When the I/O starts data transfer, the I/O control unit 31
a requests the buffer management unit to use a 4-word buffer (BFREQ 1).

■When the 4-word buffer becomes empty, the buffer management unit 33 judges the buffer use request signal BPRBQ sent from the I/O control unit 31a, and gives the I/O control unit 31a the right to use the 4-word buffer (BFAC
K1).

■When the I/O control unit 31a acquires the right to use the 4-word buffer, the DMA control unit performs a DMA operation between the I/O control unit and the 4-word buffer, and stores data until it is full. . At this time, the buffer management section monitors the state of writing to the 4-word buffer, and when 4 words of data are written, the buffer becomes full.

■When the 4-word buffer is full, the common bus control unit 34 requests the common bus management gll to use the common bus, and when the common bus receives a use permission signal (C-Bus-ACK), the common bus Performs DMA transfer. Note that at this time, if the high-speed transfer mode is selected, nibble transfer is performed.

(2) After ensuring that the data has been sent from the 4-word buffer, the buffer management section 33 makes the 4-word buffer empty and cancels the I/O control section 31a's right to use the buffer.

〔Effect of the invention〕

As explained above, according to the present invention, by switching between high-speed data transfer and low-speed data transfer depending on the device under I/O, and performing this switching based on the device address, data transfer is possible. Efficiency can be improved.

[Brief explanation of drawings]

FIG. 1 is a basic configuration diagram of the present invention, FIG. 2 is a configuration diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of the signal system in FIG. 2. (Explanation of symbols) 1...CPU. 2...I/O control adapter, 3... System memory, 4...I/O device, 5...Common bus, 31a to 31n-1/O control unit, 32...4 word battle, 33...Buffer management section, 34... common bus control section, 35...DMA control unit, 36...MPU. 37...Control register.

Claims (1)

[Claims] 1. A common bus (5) that connects the central processing unit (1) and system memory (2), and a common bus (5) that is arranged between the I/O and the corresponding I/O ports It is an I/O control adapter that controls /O transfer, and when transferring data to each device under the I/O port, assigns an address to each device and switches between high-speed and low-speed transfer to each device. A control means (35) that switches according to the address of each device, and a buffer management means (33) that manages the storage state of a buffer that temporarily stores transferred data.
), the I/O control is characterized in that high-speed transfer is performed to a disk device under the I/O port, and low-speed transfer is performed to other devices other than the disk device. adapter.