JPH03183211A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To reduce a switching noise like ground bounce by providing capacities between the sources and the drains of a pull-up transistor(TR) and o pull-down TR so os to moderate the steep change of a current in a circuit. CONSTITUTION:In the case the logical level of a data input terminal 4 is 'L', the pull-up TR 1a is turned ON. Therefore, the logical level of an output terminal 5 becomes 'H', and charges a load capacity 8. On the contrary, in the case the logical level of the data input terminal 4 is 'H', the pull-down TR 1b is turned ON. Therefore, the logical level of the output terminal 5 becomes 'L', and discharges the load capacity 8. Here, in the case the logical level of output varies, current change is caused, and the switching noise is likely to be caused, but a first capacity 11a and a second capacity 11b moderate this current change, and suppress the switching noise.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output buffer circuit, and more particularly to an output buffer circuit used in an MO8 integrated circuit.

[Conventional technology]

FIG. 3 is a circuit diagram showing a conventional output buffer circuit.

In the figure, la is a pull-up transistor, 1b is a pull-down transistor, 2 is a power supply terminal, 3 is a ground terminal, 4 is a data input terminal, 5 is an output terminal, and 6 is an output buffer circuit. Further, 7 indicates an externally connected load circuit, which is composed of a load capacitor 8 and a load resistor 9.

Data input terminal 4 is connected to the gates of pull-up transistor 1a and pull-down transistor lb, and output terminal 5 is connected to the drains of pull-up transistor la and pull-down transistor lb. The source of the pull-up transistor 1a is connected to the power supply terminal 2, and the source of the pull-down transistor 1b is connected to the ground terminal 3.

The output buffer circuit 6 and the load circuit 7 are connected via the output terminal 5, and the output buffer circuit 6 drives the load circuit 7 according to the logic level of the data input terminal 4. That is, when the logic level of the data input terminal 4 is rLJ, the pull-up transistor 1a is turned on, so that the logic level of the output terminal 5 becomes rHJ, charging the load capacitor t8.

Conversely, when the logic level of the data input terminal 4 is rHJ, the pull-down transistor 1b is turned on, so that the logic level of the output terminal 5 becomes rLJ, and the load capacitor 8 is discharged.

[Problem to be solved by the invention]

Since the output buffer circuit used in the conventional MO3 integrated circuit was configured as described above, there was a problem in that switching noise was generated every time the logic level of the output changed due to the parasitic inductance.

FIG. 4 is an equivalent circuit diagram clearly showing the parasitic inductance of the output buffer circuit shown in FIG. 3.

In the figure, 10a is a parasitic inductance between the pull-up transistor la and the power supply terminal 2, and t
ab is a parasitic inductance between the pull-down transistor 1b and the ground terminal 3;

In addition, 10c is the output terminal 5 from the drain terminal of the pull-up transistor la and the pull-down transistor 1b.
The sum of the parasitic inductance up to and the parasitic inductance existing in the wiring from the output terminal 5 to the load circuit 7 is shown.

Whenever the output logic level changes, a current change occurs. This current change induces a voltage in the parasitic inductance. The magnitude of this induced voltage is proportional to the rate of change of current. The operating speed of integrated circuits is increasing year by year, and the rate of change in current during switching is also increasing, so if no measures are taken, the voltage induced in this parasitic inductance will also increase.

This induced voltage has various effects on the operation of the integrated circuit as "switching noise". In particular, a phenomenon called "ground bounce" in which the ground potential within the integrated circuit changes from the potential of the ground terminal 3 due to this electromotive force has a negative impact on circuit operation, deteriorating circuit performance and sometimes causing malfunction. be. For example, when an output buffer switches, the output of another output buffer may exceed the threshold of the external element it is driving (even though it should not be exceeded) due to ground bounce.
It also changes the threshold of the input buffer in the integrated circuit, such that when negative ground bounce occurs, the threshold of the human cover sofa is lower than that of the low level signal. occurs.

As described above, in the conventional output buffer circuit, switching noise caused by sudden current changes during switching has an adverse effect on the circuit operation, and in the worst case, there is a risk that the circuit may malfunction.

The present invention has been made in view of these points, and its purpose is to provide an output buffer circuit that can alleviate sudden current changes and reduce switching noise.

[Means to solve the problem]

In order to achieve such an object, the present invention provides source and
A capacitor is provided between the drains.

[Effect]

In the output buffer circuit according to the present invention, sudden current changes are alleviated and switching noise such as ground bounce is reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of an output buffer circuit according to the present invention. In the figure, 1a is a pull-up transistor, lb is a pull-down transistor, 2 is a power supply terminal, 3 is a ground terminal, 4 is a data input terminal, 5 is an output terminal, and 6 is an output buffer circuit. Further, numeral 7 indicates an externally connected load circuit, which is composed of a load capacitor 8 and a load resistor 9. lla and Ilb are the first and second capacitances.

Data input terminal 4 is connected to the gates of pull-up transistor 1a and pull-down transistor lb, and output terminal 5 is connected to the drains of pull-up transistor 1a and pull-down transistor 1b. The source of the pull-up transistor la is connected to the power supply terminal 2, and the source of the pull-down transistor 1b is connected to the ground terminal 3.The operation thereof will be described below.

The output buffer circuit 6 and the load circuit 7 are connected via the output terminal 5, and the output buffer circuit 6 drives the load circuit 7 according to the logic level of the data input terminal 4. That is, when the logic level of the data input terminal 4 is rLJ, the pull-up transistor 1a is turned on, so that the logic level of the output terminal 5 becomes rHJ, and the load capacitor 8 is charged.

Conversely, when the logic level of the data input terminal 4 is rHJ, the pull-down transistor 1b is turned on, so that the logic level of the output terminal 5 becomes rLJ, and the load capacitor 8 is discharged. The above operation is similar to that of the conventional output buffer circuit shown in FIG.

Now consider the case where the output logic level fluctuates. In this case, as mentioned above regarding the operational problems of the conventional output buffer circuit, current changes occur and tend to generate switching noise, but the first capacitor 11a and the second
The capacitor 11b has the function of alleviating this current change and suppressing switching noise. For example, consider a case where the output logic level changes from rLJ to rHJ. In this case, a current change occurs because the pull-down transistor ib is cut off, but this change is alleviated by the charging current flowing through the second capacitor 11b. Furthermore, when the logic level of the output changes from rHJ to rLJ, the current change that occurs because the pull-up transistor 1a is cut off is alleviated by the charging current flowing through the first capacitor 11a.

FIG. 2 is a schematic cross-sectional view showing the structure of a capacitor used in this embodiment. 12a and 12b are first and second electrodes,
Reference numeral 13 indicates a dielectric material. It is desirable that the first and second electrodes 12a and 12b be constructed using a wiring layer within a semiconductor. The reason for this is that by using a wiring layer for the electrode, latch-up is less likely to occur compared to other configurations, such as a case where a diffusion layer is used for the electrode.

〔Effect of the invention〕

As explained above, by providing a capacitance between the source and drain of the pull-up transistor and pull-down transistor, the present invention can alleviate sudden current changes in the circuit and reduce switching noise such as ground bounce. This makes it possible to avoid circuit malfunction or performance deterioration caused by switching noise. Furthermore, if the plurality of electrodes constituting the capacitance used in the output huffing circuit according to the present invention are constructed using a wiring layer within a semiconductor, it is possible to suppress the occurrence of latch-up due to addition of capacitance.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an output buffer circuit according to the present invention, FIG. 2 is a schematic cross-sectional view showing the structure of a capacitor used in the circuit of FIG. 1, and FIG. 3 is a conventional output buffer circuit. The circuit diagram, FIG. 4, is an equivalent circuit diagram clearly showing the parasitic inductance in the conventional output vanofer circuit of FIG. la... Pull-up transistor, b... Pull-down transistor, 2... Power supply terminal, 3... Ground terminal, 4... Data input terminal, 5... Output terminal, 6...
...Output buffer circuit, 7...Load circuit, 8...Load capacitance, 9...Load resistance, lla, llb...Capacitance.

Claims (1)

[Claims] A pull-up transistor for pulling up the output terminal, a pull-down transistor for pulling down the output terminal, a capacitor provided between the source and drain of the pull-up transistor, and a capacitor provided between the source and drain of the pull-down transistor. An output buffer circuit comprising: