JPH03183051A - Sound recording circuit - Google Patents

Abstract

PURPOSE:To record a start identification (ID) signal prior to a recording object signal by detecting the level change point of the recording object signal, generating the start ID signal and recording it together with a delayed recording object signal in a digital audio tape recorder (DAT). CONSTITUTION:When a level detection circuit 4 detects the level change point in which the level of the recording object digital signal from an A/D conversion circuit 3 is more than a threshold value, a microcomputer 11 generates the start ID signal. The recording object digital signal passing through this circuit 4 is supplied to a code applying circuit 5 and the circuit 5 writes these data into a memory 6 of 1M bits, reads out the data, applies an interleave code or an error correction code to a PCM signal and outputs the required delayed recording object signal. This delayed signal and the start ID signal are recorded to a magnetic tape T and the start ID signal is recorded prior to the recording object signal.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a recording circuit in a DAT or the like.

[Prior Art] In a recording/reproducing apparatus such as a DAT, a start ID signal is recorded together with a signal to be recorded in order to ensure the beginning of a song.

Conventionally, there has been an attempt to automatically record this start ID signal to prevent forgetting to record it and to improve the convenience of the user. This type of device is, for example,
It is disclosed in Japanese Patent No.-56551.

As shown in FIG. 4(A), this device first compares the recording target signal with a specified value and detects the point at which the level of the recording target signal exceeds a threshold value. Then, in response to the detection of the level change point, the start I is started as shown in FIG.
A D signal is generated, and this start ID signal is recorded together with the recording target signal.

This is very convenient because the start ID signal is automatically recorded without the user having to worry about recording it.

However, such a start ID automatic recording technique still has the problem that the start ID signal is recorded after the recording target signal actually rises.

In order to overcome such problems, conventional methods have been considered such as playing back from a position slightly earlier than the start ID or configuring the start ID itself to be moved slightly earlier by post-recording.

[Problem to be solved by the invention]

However, in the former case, a problem arises because the start ID has a redundant interval from the rising point of the recording target signal depending on how the recording target signal rises.

In other words, the more rapidly the rising edge of the recording target signal, the closer the start ID and the rising point of the recording target signal will be.
By moving the playback start point before the start ID, there is a high possibility that playback will start from the part after the signal recorded before that point.

Furthermore, in the latter case, even if the start ID is automatically recorded, it is meaningless, and the end result is the same as manual recording.

When a CD player is the source, some devices are configured to send a start ID signal to the DAT 0.5 seconds to 1 second before the start of the song.

However, in air checks such as FM broadcasting, it is impossible to know the beginning of a song in advance, and this measure is hardly sufficient.

The present invention was made in view of these problems, and
The purpose is to provide a recording circuit that can record a start ID before a signal to be recorded.

[Means to solve the problem]

The recording circuit of the present invention comprises a level detecting means for detecting a level change point where the level of a signal to be recorded exceeds a threshold value, an ID signal generating means for generating a start ID signal in response to the level change point detection signal, and the above-mentioned. The apparatus includes a delay means for delaying a signal to be recorded, and a recording means for recording a start signal from the ID signal generation means and a start ID signal from the delay means on a recording medium.

[For production]

According to the present invention, by adjusting the delay time of the recording target time in the delay means, the start ID signal can be recorded before the recording target signal.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a DAT recording circuit according to a first embodiment of the present invention.

In this figure, 1 is an amplifier and 2 is a low-pass filter (
Hereinafter, it will be abbreviated as LPF. ), 3 is an A/D conversion circuit. The analog audio signal is amplified by amplifier 1, aliasing is cut by LPF 2, and sent to A/D.
The signal is input to the conversion circuit 3. This A/D conversion circuit 3 samples the analog audio signal at a predetermined frequency and digitizes it.

4 is a level detection circuit. This level detection circuit 4 is
The level of the digital audio signal from the /D conversion circuit 3 is compared with a specified value (for example, full scale -50 dB), the point at which this digital audio signal exceeds the specified value is detected as a level change point, and the level is determined. Outputs a change point detection signal.

11 is a microcomputer, and this microcomputer 11 generates a start ID signal (start flag) in response to a level change point detection signal from the level detection circuit 4.

5 is a code addition circuit, and 6 is a memory. Sign addition circuit 5
receives the digital audio signal via the level detection circuit 4, sequentially writes it into the memory 6, and adds codes such as interleave codes and error correction codes to the PCM audio signal read from the memory 6 and outputs it. It is something.

The memory 6 consists of a 1M bit memory and has a 4-bit address input terminal.

The sign addition circuit 5 includes a signal processing IC 7 and a 2-bit counter 8.
and Exclusive OR Gate (hereinafter referred to as EX OR Gate) 9.10.

The signal processing IC 7 controls reading by interleaving the data written in the memory 6.
This control is performed by controlling the lower two bits of the address.

The counter 8 counts the frame signals from the signal processing IC 7 and supplies the lower bits of the 2-bit output to the EX-OR gate 9 and the upper bits to the EX-OR gate 10, respectively.

EX or gates 9 and 10 also have leads/
A read/write control signal from the write control section is input manually, the output of the EX OR gate 9 is input to 23B at the address input terminal of the memory 6, and the output of the EX OR gate 10 is input to the MSB at the address input terminal of the memory 6. The upper two bits are used to switch the memory 6 into four banks, and control is performed so that the bank memory immediately after reading is used when writing data.

12 is an 8-10 irregular circuit. The data from the code addition circuit 5 is supplied to the 8-10 modulation circuit 12, and the 8-1
The 8-bit data is converted into 10-bit data by the 0 modulation circuit 12 and supplied to the recording head 13 via the recording amplifier section.

Here, the data transmission speed in DAT is 48 (kHz) in standard mode (48kHz stereo).
X 16 (b!t)X 2 (C!()-1,536
It is X10B (bit/5ee).

The processing required to interleave the DAT and add error correction codes takes the time equivalent to two rotations of the drum (66,6
7m5ec), the memory is 1.5
36X (66,67/1000)xlO-102,4
All that is required is xlO3 (bit), but in the case of this example, since 1M memory is used, (
1xlO6) / (1,536x106)4 = Burning 0.6
5 (see), and the data is delayed by about 0.65 seconds.

As a result, the microcomputer 1 is required to generate the start ID signal.
It takes several tens of m5ec to extract the booter from the level detection circuit 4 every 10 + ascc, but the positional relationship between the recording target signal and the start ID signal is as shown in Figure 3. It will be after.

According to this embodiment, the conventional small-capacity memory for the memory 6 is replaced with a large-capacity memory, and the signal processing IC is used as is.
In addition, 2-bit counter 8 and EX or game) 9, 10
The present invention can be realized by simply changing the circuit by adding . Incidentally, in recent years, the capacity of memory has been increasing, and the small capacity memory used in the past is actually more difficult to handle.

Therefore, this embodiment is in line with technological trends.

FIG. 2 is a block diagram of a recording circuit according to a second embodiment of the present invention.

In this figure, the signal to be recorded is delayed by a FIFO memory.

14 is the FIFO memory, 15 is its control circuit, 16 is a code addition circuit, and 17 is a memory.

Here, since the audio signal is delayed in the FIFO memory 14 as described above, the memory 16
And the memory 17 can be the same as the conventional one.

In the case of this embodiment, the capacity of the FIFO memory 14 is as follows:
In the above standard mode, 768 kbit when delaying 0.5 seconds.

1536 kbit for 1 second delay.

only needed.

Furthermore, when using a commercially available Sony CXK1206M, this memory is 960 (C) X360 (R) X4 (bit
) DRAM, 960X306X4/ (1,536X106)-0,
765 (see), and a delay of about 0.7 seconds or more is possible.

This embodiment also provides the same effects as the first embodiment.

〔Effect of the invention〕

As explained above, according to the present invention, by adjusting the delay time of the recording target time in the delay means, the start ID signal can always be recorded before the recording target signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a recording circuit according to a first embodiment of the present invention, FIG. 2 is a block diagram of a recording circuit according to a second embodiment of the present invention, and FIG. 3 is a block diagram of a recording circuit according to a second embodiment of the present invention. FIG. 4 is a time chart for explaining the operation of the recording circuit shown in FIG. 4, and FIG. 4 is a time chart for explaining the operation of the conventional recording circuit. 4... Level detection circuit, 5.16... Code addition circuit, 6... Memory for code addition memory, 7... Signal processing IC, 8... 2-bit counter, 9.10...・Exclusive or gate, 11... Start ID generation microcomputer, 14... FIFO memory for delay, 17.
...Memory for adding code.

Claims (1)

[Scope of Claims] Level detection means for detecting a level change point in a recording target signal whose level exceeds a threshold; ID signal generation means for generating a start ID signal in response to the level change point detection signal; A recording circuit comprising: delay means for delaying a signal to be recorded; and recording means for recording a start ID signal from the ID signal generation means and a signal to be recorded from the delay means on a recording medium.