JPH03181195A - Manufacture of wiring substrate - Google Patents

Abstract

PURPOSE:To connect upper and lower conductors securely and to enable high density wiring by forming a via hole by dry-etching in an interlaminar insulating layer and by forming a via inside the via by electrical plating. CONSTITUTION:An intermediate insulating layer 12 is formed on a substrate 11 which is provided with a lower conductor 10. Then, a via hole 14 is formed by reactive etching using a resist 13 as a mask; the hole 14 is etched to form a vertical wall. Then, the resist 13 is removed and an Ni film 15 is attached all over by electroless plating. After patterning is carried out with a resist 16 to cover all over excepting the hole 14, Cu electrolytic plating is carried out using the film 15 as an electrode to form a via 17. Then, the resist 16 is removed. When the Cu-plated via 17 projects from a surface of the layer 12, the projecting part is removed by etching, etc., for flattening. Thereby, it is possible to connect upper and lower conductors securely even with a via of a small diameter and to enable high density wiring since an upper part of the via is also flattened.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a method for manufacturing a wiring board on which an IC used for computers, etc. is mounted, and aims to enable high density interlayer connections and flattening of through holes. a step of forming an interlayer insulating layer using an insulating paint, a step of forming a hole for a via in the interlayer insulating layer by dry etching, a step of forming a metal coating on the interlayer insulating layer by electroless plating, A process of masking parts of the metal film other than the holes for vias with a resist, electroplating using the metal film as an electrode, and depositing plating metal in the holes for vias to fill chain holes. If there is a part of the deposited metal that protrudes from the hole, the protruding part is removed by wet etching and is flattened to match the surface of the interlayer insulating layer to form a via, and an upper conductor is formed by connecting to the via. The configuration includes at least the following steps.

[Industrial application field]

The present invention relates to a method of manufacturing a wiring board used in devices such as computers that require high-density packaging of ICs.

[Conventional technology]

In recent years, computers have become faster and faster, and as a result, wiring boards are required to have shorter wiring lengths. Therefore, in a multilayer wiring board, it is necessary to perform high-density interlayer connections.

As shown in FIG. 2, a conventional multilayer wiring board has a lower conductor 2, an interlayer insulating layer 3, and an upper conductor 4 provided on the board (2), and the lower conductor 2 and upper conductor 4 are provided on the interlayer insulating layer 3. hole(
It has a configuration in which it is electrically connected via a through hole.

The multilayer wiring board is created by using photosensitive polyimide for the interlayer insulating layer 3, opening through holes for interlayer connections, forming a thin film using spack and buttering, or electroplating as necessary. This forms the upper conductor 4.

[Problem to be solved by the invention]

In the above-mentioned conventional method for manufacturing a multilayer wiring board, when holes are formed using photosensitive polyimide, they become conical with an open top.
Since a hole with a diameter twice the required contact area with the lower conductor is formed on the surface of the interlayer insulating layer 3, the contact area between the lower conductor 2 and the upper conductor 4 must be reduced in order to perform high-density wiring. However, electrical resistance increases and reliability decreases. For this reason, it is necessary to keep the contact area at the bottom of the through hole the same and reduce the area at the top of the interlayer insulating layer (in other words, make the hole vertical without tapering). A problem arises in that the metal thin film does not adhere to the wall surface of the through-hole portion, making it impossible to connect the upper and lower conductor layers via the interlayer insulating layer.

Further, in the conventional method, a step corresponding to the thickness of the interlayer insulating layer is generated in the through-hole portion, but there is also a problem that it is difficult to fill in the step when multilayering.

SUMMARY OF THE INVENTION In view of the above-mentioned conventional problems, it is an object of the present invention to provide a method of manufacturing a wiring board that enables high density interlayer connections and flattening of through-hole portions.

[Means to solve the problem]

In order to achieve the above object, the method for manufacturing a wiring board of the present invention includes a step of forming an interlayer insulating layer 12 using an organic insulating paint, and forming holes 14 for vias in the interlayer insulating layer 12 by dry etching. Process and the above interlayer insulating layer 1
a step of forming a metal film 15 on the metal film 15 by electroless plating, a step of masking a portion of the metal film 15 other than the via hole 14 with a resist 16, and a step of masking a portion of the metal film 15 other than the via hole 14;
Electroplating is performed using the electrode as an electrode, and plating metal is deposited in the via hole 14 to fill the via hole 14. If there is a part where the deposited metal protrudes from the via hole 14, wet etching is performed. The method includes at least the steps of removing the protrusion and planarizing it to match the surface of the interlayer insulating layer 12 to form a via 17, and connecting to the via 17 to form an upper conductor 18. Features.

[For production]

In the method of the present invention, holes 14 for vias are formed in the interlayer insulating layer 12 by dry etching, so the walls of the holes are vertical and the upper part of the holes does not widen, making it possible to form vias in a high density arrangement. can.

Also, a via 1 is formed in the via hole 14 by electroplating.
7, the upper part can be flattened, and the intermediate insulating layer 1
2 can be prevented from occurring.

〔Example〕

FIG. 1 is a diagram for explaining the present invention in detail, (a
) to (e) are diagrams showing the steps.

In this embodiment, first, as shown in FIG. 1(a), a lower conductor 10 is
A polyimide resin is applied onto the substrate 11 on which the polyimide resin is formed, and is baked and hardened to form the intermediate insulating layer 12.

Next, as shown in FIG. 2B, a via hole 14 is formed by reactive etching using an Af metal or resist 13 having a hole for forming a via hole as a mask. In this case, the holes 14 are etched so that their walls are vertical. Next, Ni 15 is deposited on the entire surface by electroless plating, except for the resist 13, as shown in FIG. 3(C).

Next, as shown in FIG. 4(d), patterning is performed so as to cover areas other than the via hole 14 with a resist 16, and then the N1
Electrolytic plating of Cu is performed using the film 15 as an electrode to form via 1.
7 is formed and the resist 16 is removed. In this case, if the Cu-plated via 17 protrudes from the surface of the interlayer insulating layer 12, the protruding portion is removed by etching or the like and planarized. Finally, the upper conductor 18 is formed as shown in FIG. 3(e). Multilayering is achieved by repeating the steps (a) to (e) above. Note that a step of removing organic matter and roughening the surface to some extent using 02 plasma may be added before the electroless plating in step (C).

According to the above embodiment, the lower conductor 1 is connected to the via 17.
0 and the upper conductor 18 can be electrically connected.

Furthermore, in this embodiment, the holes 14 for vias are formed in the interlayer insulating layer 12 by dry etching, so the walls of the holes are vertical and the upper part of the holes does not widen, so the vias are arranged and formed at high density. be able to. Furthermore, since the via 17 is formed in the via hole 14 by electroplating, the upper part of the via 17 can be flattened, and the generation of a step between the via hole 14 and the intermediate insulating layer 2 can be prevented.

〔Effect of the invention〕

As explained above, according to the present invention, the upper and lower conductors are reliably connected even when using small diameter vias, and the upper part of the via is also flattened, making it possible to perform high-density wiring and also facilitate multilayering. becomes.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining the present invention in detail, and FIG. 2 is a diagram showing a conventional multilayer wiring board. In the figure, 10 is a lower conductor, 11 is a substrate, 12 is an interlayer insulating layer, 13, 16 is a resist, 14 is a via hole, 15 is a Ni film, 17 is a via, and 18 is an upper conductor.

Claims (1)

[Claims] 1. a step of forming an interlayer insulating layer (12) using an organic insulating paint; a step of forming a via hole (14) in the interlayer insulating layer (12) by dry etching; and a step of forming a via hole (14) in the interlayer insulating layer (12) by dry etching.
12) forming a metal film (15) on the metal film (15) by electroless plating; masking a portion of the metal film (15) other than the via hole (14) with a resist (16); Electroplating is performed using the coating (15) as an electrode to deposit plating metal into the via hole (14).
14), and if there is a part where the deposited metal protrudes from the hole (14) for the via, the protruding part is removed by wet etching, and the via (14) is flattened to match the surface of the interlayer insulating layer (12). 17); and forming an upper conductor (18) connected to the via (17).