JPH0316064A - Signal processor for digital signal - Google Patents

Abstract

PURPOSE:To easily mix and separate an audio signal and a video signal by converting a time base of a digital video signal to a time base based on a signal format of a DAT. CONSTITUTION:An audio signal is subjected to A/D conversion by a sampling clock based on a signal format of a digital audio tape recorder DAT, and a video signal is subjected to A/D conversion by a sampling clock of a frequency of an integer multiple of a subcarrier. Subsequently, in a state that this video signal subjected to A/D conversion is synchronized with the sampling clock of the audio signal, its time base is converted, and it is added to the audio signal in its state. In such a way, the video signal based on the signal format of the DAT can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to a digital decoding signal processing device suitable for use as an adapter for a digital audio tape recorder, and in particular for inserting a video signal into an audio signal. Regarding the time axis conversion process.

[Conventional Technology] Three types of digital audio tape recorders (hereinafter referred to as DATs) are capable of recording and reproducing only audio signals.

However, it would be very convenient if not only audio signals but also other signals, such as video signals for still images, could be recorded and played back simultaneously.

Here, in order to record and reproduce video signals, it is conceivable to record each signal one channel at a time, such as recording audio signals on odd-numbered tracks and recording video signals on even-numbered tracks.

Alternatively, it may be possible to record in a format other than the current audio format.

[Problem to be Solved by the Invention 1] However, if an audio signal is recorded on one channel and a video signal is recorded on the other channel in the DAT audio format, unless a playback device that can also play back the video signal is used. , the video signal will also be played back at the same time.

A DAT having only an audio signal reproducing device cannot be used because when a video signal is reproduced, this becomes excessive noise and is not reproduced.

If a video signal is recorded in a format other than the current audio format, it will not be compatible with the current DAT, and therefore the normal DAT will not be able to reproduce even the audio signal.

In order to solve these problems, it is necessary to record and reproduce video signals without adversely affecting audio signals while maintaining compatibility with current models. Also, in that case, considering recording and playback with DAT,
The video signal is DA. The format must comply with the T signal format.

However, as is well known, the DAT sampling clock fs is 48kHz. 44.1 kHz. It is 32kHz. On the other hand, since the sampling clock of the video signal is usually an integral multiple of the subcarrier, the time axes of the audio signal and the video signal are different. Therefore, the video signal cannot be added to the audio signal as is.

Therefore, the present invention takes these points into consideration and proposes a signal processing device that can form a video signal compliant with the DAT signal format.

[Means for Solving the Problem] In order to solve the above-mentioned problem, in this invention, the upper N bits (N t...t integer) are used as an audio signal, and the lower M bits (M is an integer) are used as a video signal. , in a signal processing device for a digital signal which processes the video signal by adding or separating it to the audio signal, the audio signal is processed by A at a sampling clock fs conforming to the signal format of a digital audio tape recorder. /D conversion, and the video signal is converted to A with a sampling clock having a frequency that is an integral multiple of the subcarrier.
This video signal, which has been subjected to A/D conversion and A/D conversion, has its time axis converted in synchronization with the sampling clock fs, and is added to the audio signal in this state. {It is a song.

[Operation The co-audio signal Sa is supplied to the A/D converter 18,
A/D with sampling clock (audio sampling clock) fs compliant with DAT signal format
It is converted and supplied to the mixing and separating means 86.

The video signal Sv is supplied to the A/D converter 54, and a clock (video sampling clock) 3fsc (or 4f
sc) is A/D converted.

Digital video signal DSV is supplied to memory means 60 and written into memory 62 or 64 with write clock WCK synchronized with video sampling clock 3fsc.

Then, the digital video signal DSv is read out using 2'fs synchronized with the audio sampling clock fs as the readout clock RCK.

The read digital video signal DSV is mixed with the digital audio signal DSa by a confusion separating means 86. The mixed digital signal DS is recorded by the DAT, reproduced again, and separated into an audio signal Sa and a video signal SV by signal processing opposite to that described above.

If the time axis of the digital video signal DSv is converted to the time axis compliant with the DAT signal format in this way,
Audio signal Sa and video signal Sv can be easily mixed and separated.

[Embodiment] Next, an example of a signal processing device for digital signals according to the present invention will be described in detail with reference to FIG. 1 and subsequent figures.

Figure 2 shows the format (bit configuration) of the digital signal DS, which is a mixture of the audio signal Sa and the video signal Sv.
An example is shown below.

In this invention, in consideration of both compatibility with conventional models and the playback quality of audio signals, the D
Although the number of bits of the AT original digital signal DS is used, this is the same as A. It is divided into two as shown in B, and the digital audio signal DSa is on the upper bit side.
A digital video signal DSv is applied to each of the lower bits.

According to the audio format, the total number of bits is T (T is an integer), and T=16 is selected, and the number of bits of the digital audio signal DSa is N (N is an integer), and the remaining number of bits is When M (=TN) is the digital video signal DSv, better results can be obtained by selecting N as N≧1/2T. Among these, a practical value is about N=8 to 10 (Fig. 2A). As a result, the digital video signal DSV has a 6- to 8-bit configuration (FIG. 2B). In this example, N=10. M=6.

Then, if the digital audio signal DSa and the digital video signal DSv are mixed so that the digital audio signal DSa is on the upper bit side, the upper 10 bits become the area of the digital audio signal DSa,
The lower 6 bits are the area of the digital video signal DSv (FIG. 2C).

When mixing the audio signal Sa with the video signal SV after applying noise countermeasures such as noise reduction, the relationship between the audio signal Sa and the video signal Sv is not limited to the above-mentioned relational expression, and the audio signal The number of bits of Sa can also be further reduced.

A digital signal DS having such a bit configuration is supplied to a rotating magnetic head (not shown) provided on the DAT, is recorded thereon, and is reproduced from the rotating magnetic head (not shown).

48k as audio sampling clock fs
When using Hz, on the other hand, when the video sampling clock is 3fsc (fsc is 3.58MHz), there is a frequency difference of about 112 times between the two, so one field of video signal takes about 2 seconds. recorded. Furthermore, since the audio signal (narration or BGM) corresponding to the image content of the video signal is usually longer than 2 seconds, the audio signal for one image is usually recorded for 2 seconds or longer. As a result, if the audio signal is used as a reference, a plurality of images can be inserted before the audio signal ends.

Considering the later search processing and the like, it is preferable to add some kind of identification code to the video signal (image data) and then add the video signal to the audio number 8. Signal formats have been constructed from this perspective.

FIG. 3 shows an example.

An identification code ID is added before and after the video signal (image data) inserted into the audio signal (sound data). As shown in the figure, the identification code ID includes a start code section S-ID that is added immediately before the video signal, and a stop code section E-ID that is added immediately after the video signal.
An example is shown in which the ID is configured with the ID.

Examples of how the start code section S/ID can be used include (1) the identification code of the video signal data, that is, the image data itself, (2) the format of the video signal, that is, whether it is a composite video, or Y Signal and C signal video or R. Examples include identification code for G or B component video, (3) quantization bit number of image data, and (4) cue code (LS/ID) for image data. However, this is just one example.

To realize such a usage example, start code part S
- It is possible to configure the ID as follows.

Figure 4 is an example. First, as shown in the figure, a 6-bit code in which only the least significant bit is "1" is used as a start code. Similarly, a code with all "0"s is used as a stop code.

Treating 6 bits as 1 block B, (4 8
A start code section S-ID is constructed using 0 0 + 1 ) blocks (approximately E50 msec), of which 600 blocks are made into main blocks, and the same code data is inserted into each main block. This means that no matter where the start code section is played from, the start code section S.
This is to enable the ID to be searched.

The main block is divided into 20 sub-blocks of 30 blocks, of which the first half 1 and 2 sub-blocks FO to Fil are used as framing codes.

Then, when the codes of the blocks that construct each sub-block are all start codes, "O
”, all sub-blocks FO~Fil
When is "○", this is determined as a framing code.

Furthermore, the remaining eight subblocks DO to D7 are used as mode codes.

An example of the mode code is shown in FIG. The content of the mode code is an example.

As shown in FIG. 4, the stop code section E-ID is composed of 8 blocks (approximately 93 μsec) in this example.

Then, a certain blank period is placed in the latter half of this stop code section E-ID, and this start code section S-ID is set as a blank period.
From the beginning of the ID to the end of the blank period (approximately 2
seconds) is taken as a unit area of one image data. The time of this unit area also corresponds to 120 times the vertical period.

Since the phase of subcarrier fsc goes around in four fields, if the unit area is set to approximately 20 times the subcarrier fsc, the phase of the still image video signal SV recorded before and after will always be in the ○ phase. , subcarrier f
sc discontinuity can be avoided.

Now, Fig. 1 shows how the digital signal DS is processed so as to adopt such a signal form, and then the digital signal DS recorded on the DAT and reproduced from the DAT is separated into the original audio signal Sa and video signal Sv. An example of a main part of a signal processing device for processing is shown.

The 4= processing system of the audio signal Sa will be explained first.

The audio signal Sa supplied to the audio in terminal 12 is supplied to the low-pass filter 16 via the amplifier 14 to be band-limited, and then supplied to the A/D converter 18 and converted into a 10-bit digital audio signal DSa. be done. The audio sampling clock used at this time is fs (48kHz).

The digital audio signal DSa is supplied to a mixing means (adder) 20 constituting the mixing/separating means 86 and mixed with a digital video signal DSv, which will be described later. The mixed digital signal DS (FIG. 2C) is supplied to the digital out processing circuit 22 and converted into a digital signal conforming to the audio format.

As is well known, the digital out processing circuit '#122 is provided with clock generation means for generating pit clock BCK.

The formatted digital signal DS is finally supplied to the rotating magnetic head via the terminal 24 and is recorded.

The digital signal DS reproduced by the rotating magnetic head is supplied to a digital-in processing circuit 34 via a reproduction terminal 32 and subjected to digital-in processing.

For example, a PLL circuit (not shown) is driven to generate a master clock synchronized with the reproduced pit clock BCK.

A separation signal for separating the digital audio signal DSa and the digital video signal DSv is generated based on this master clock, and the digital audio signal DSa and the digital video signal DSv are separated from the separating means 36 at the next stage. (A and B in Fig. 2).

Separated 10-bit digital audio signal DS
a is converted into an analog signal by a D/A converter 38, limited to a predetermined band by a low-pass filter 40, and then outputted to an audio out terminal 44 via an amplifier 42.

The signal processing system for the video signal Sv has the following configuration.

The still image video signal Sv supplied to the video in terminal 50 is supplied to the A/D converter 54 via the amplifier 52, and in this example, it is converted into a 6-bit digital video signal DSv.
is converted to The sampling clock used at that time has a frequency that is an integral multiple of the subcarrier fsc, and is 3fSC in this example.

The digital video signal DSv is supplied to the memory means 60 via a changeover switch 56 for switching between an input signal and a reproduction signal and a changeover switch S8 for after-recording.

The memory means 60 functions as a time axis conversion means for the digital video signal DSV.

In other words, in order to combine the digital video signal DSv with the digital audio signal DSa, the digital video signal DSV is read out in synchronization with the pit clock BCK, and the time axis of the reproduced digital video signal DSv is expanded. Used for axial compression.

The memory means 60 has a pair of memories 62, 64, and a memory control circuit 70, 64 provided in association therewith.
72, the data is controlled to be stored one field (or one frame) at a time in the corresponding memories 62 and 64.

When only one image is inserted one-shot, only one field of video signal is stored in one of the memories. If the same screen is to be inserted continuously, the stored video signal may be repeatedly read out. When inserting different screens successively, video signals are captured at predetermined time intervals and are stored alternately in memory. memory 62
．． Since it takes about 2 seconds to read data from 64, the predetermined time is any time longer than 2 seconds.

Here, writing to the memories 62 and 64 is performed using a 3fSC clock. The reading is performed using a 2fs clock.

This is to synchronize the time axis of the digital video signal DSv with the time axis of the digital audio signal DSa while maintaining synchronization. As shown in FIG. 6, since the digital audio signal DSa is designed to record both L and R channels sequentially, at the time of reading,
Instead of fS, a 2fs clock is used.

Reference numeral 100 denotes a control means for a memory, etc., to which the subcarrier fsc extracted by the subcarrier extraction circuit 110 is first supplied. The control means 100 supplies control signals to the respective memory control circuits 70 and 72 based on this subcarrier fsc.

Reference numeral 124 denotes a changeover switch that is controlled in relation to the recording mode and playback mode in the signal processing device 10, and the mode is determined based on the switching state.

The control means 100 is further supplied with a pit clock BCK from the digital out processing circuit 22 and the digital in processing circuit 34. Therefore, the read clock RCK (=2f
s) is generated, the memory control circuit 70
．． 72 is supplied with a predetermined control Ill signal.

As a result, the digital audio signal DSa and the digital video signal DSv are input to the mixing means 20 in complete synchronization with the pit clock BCK.

In addition, in the digital out processing circuit 22, the detailed explanation is omitted, but based on the pit clock BCK, the
A bit switching signal BS of 0 bit and 6 bit is created,
This bit switching No. 48 BS is supplied to the mixing means 20, and the 10-bit digital audio signal DSa and the 6-bit digital video signal DSv are mixed as shown in FIG. 2C.

Reference numeral 112 denotes a vertical synchronization signal separation circuit, and a vertical synchronization signal extracted and separated from the digital video signal DSv is supplied to the control circuit 100. This allows the memory 62
．． The digital video signal DSv for one field is always stored in the memory 64 based on the vertical period.

A pair of output selector switches 66, 88 that are switched in conjunction with each other are provided downstream of the memories 62, 64. The output selector switch 68 is used during No. 8 recording, and the other output selector switch 66 is used during signal reproduction.

The digital video signals DSv alternately read out from the memories 62 and 64 by the output changeover switch 68 are supplied to the sync bit shift encoder 76, where the sync bits are shifted.

Originally, a video signal is A/D* converted into 6 bits, so its sync bits are all "O" digital data. However, the above-mentioned identification code ID
Considering this, as shown in FIG. 7, since the identification code ID is assigned to the bit that does not affect the image, processing is performed to shift only the sync bit, and the identification code ID is assigned to the bit that does not affect the image. and the sync bit can be distinguished from each other.

Therefore, during recording, the sync bit is shifted by one bit, and then the adder 78 adds the identification code ID. 80 is this identification code ID
It is a generator of

Digital video signal DS with identification code IO added
Parallel/serial conversion processing is performed on v in the processing circuit 82, and bit inversion processing is also performed on an arbitrary bit of the digital video signal DSV, in this example, the most significant bit MSB. This process will be described later.

Digital video signal ゜DS that has undergone predetermined signal processing
v is converted by the format conversion circuit 84 into a format compliant with the DAT signal format, and then
As shown in Figure C, it is mixed with the digital audio signal DSa and sent to the DAT side.

When the digital signal DS is reproduced, the separating means 36 separates it into a digital audio signal DSa and a digital video signal DSv. The separated digital video signal DSv is converted to the original format by a format inverse conversion circuit 88, which is subjected to serial/parallel conversion processing by a No. 8 processing circuit 90, and the topmost pit of the digital video signal DSv is Re-inversion processing is performed.

Thereafter, in the sync bit shift decoder 92, only the sync bits are shifted in the opposite direction to that during recording, and returned to the original sync bits (see FIG. 7).

After that, the memory 6 is transferred via the changeover switch 56+58.
2.64 and reproduced digital video signal DSv
By clock W synchronized with bit clock BCK
Written by CK (=2fs), subcarrier f
Read clock RCK associated with sc (-3fsc)
is read based on.

The digital video signal DSV outputted from the output changeover switch 66 passes through the input/output monitor changeover switch 102, is converted into an analog signal by the D/A converter 104, and is outputted as video out to the output terminal 108 via the amplifier 106. . There is a monitor means (not shown) on the video out side.

An identification code ID detection means 94 is provided on the output stage side of the signal processing circuit '#i90, and the detected identification code ID is supplied to the control circuit 100. The memory control circuits 70 and 72 are controlled by this identification code ID, and signal processing is changed based on mode information.

Now, when the digital video signal DSv to which the identification code ID is added is reproduced and stored in the memory means 60, only image data is stored. At this time, the final image data is obtained when a predetermined period of time has elapsed from the first data of the image data, but in order to detect this final image data more accurately, in addition to time management, the stop code E-10 is detected. , it is preferable to judge it as the final image data when both of them match. Then, when the storage of this final image data is completed, writing to the memory 62, 64,
When the read mode is reversed, the output selector switch 6
6.68 also switches.

On the other hand, when the playback mode of the DAT is stopped during playback of the digital video signal DSv, the playback output data input to the terminal 32 is all "O" as shown in FIG.
”. Since time management (count-up processing) for image data is performed on the signal processing device 10 side, D
Even if the AT enters the stop mode, the count-up process will not be stopped.

Therefore, since the memory means 60 is still in the write mode, all "O" data is stored in the corresponding memory, for example 64, as original image data.

Then, when a predetermined period of time has elapsed from the stop mode, the playback time for the final image data has arrived, and since the playback data at that time is always all "O", this may be mistakenly judged as a stop code. Put it away. In that case,
The signal processing device 10 considers that the final image data has arrived, seals it in the memory means 60, and instructs the writing and reading modes and switching of the changeover switches 66 and 68, so the memory 64 is controlled to read mode. be done.

Then, after DAT goes into stop mode, memory 6
Since the data "O" written in 4 is read out and monitored as an image, the data "O" portion appears black, resulting in a very unsightly image being monitored.

In order to avoid this, if the most significant bit of the image data is recorded inverted and then re-inverted during playback, as shown in Figure 8, even if the playback output when stopped midway is all "0",
After re-inversion processing, the most significant bit becomes "1".

As a result, on the signal processing device 10 side, (1) there is no misjudgment that the final image data has arrived;

(2) Therefore, the memory means 60 is not controlled to switch.

Therefore, according to (2), the previous screen is always monitored in this case, and the above-mentioned drawback is eliminated.

The operation of dubbing will be explained next.

Before that, this signal processing device 10 includes at least two function switches 120. as shown in FIG.
122 is provided. One is a mode switch and the other is a shirt switch.

The mode switch 120 is for selecting whether the screen to be inserted is single or continuous, and the shutter switch 122 is for selecting the screen to be inserted when the screen to be inserted is a single shot. .

When dubbing an audio signal, the insertion screen remains as it is, so put the DAT in a playback state, monitor the screen, and switch to dubbing mode when the desired screen for dubbing appears.

The ittt reading and writing of the memories 62 and 64 are repeated alternately, but when performing the post-recording of Audio No. 13, the switching state is fixed.

For example, if the dubbing mode is selected while image data in the memory 62 is being monitored, the image data in the memory 62 is always monitored, whereas the image data in the memory 64 is
It is in a state where it can be recorded on AT.

The image data in memories 62 and 64 do not match in most cases. On the other hand, since the operator performs dubbing operations while looking at the monitor screen, the monitor screen during dubbing and the screen actually recorded by dubbing end up being different.

To eliminate this problem, it is sufficient to match the image being monitored with the image to be recorded when in the post-recording mode.

Therefore, in terms of hardware, the changeover switch S8 for dubbing
is provided.

The dubbing mode will be explained with reference to FIG.

It is assumed that the changeover switches 66, 88 are switched to the state shown in FIG. 1 (FIG. 9F).

The write enable signal W is used so that the identification code ID added to the digital video signal DSV is not stored in memory.
T is output (A and C in the same figure).

When the cue code LS/ID is detected from the identification code ED, an address clear signal is output (B in the same figure).
. When the shutter switch 122 is pressed while the memory 64 is in the writing state (D in the same figure), the #a circuit 100 determines that it is the post-recording mode, and fixes the operation mode of the memory means 60 to the previous operation mode.

Then, the dubbing switch 58 is switched to the terminal C side in FIG. At the same time, the frequency of the write clock RCK for the memory 64 is changed from 2fs to 3fsc (
Same figure E>. Then, the image data in the memory 62 is supplied to the memory 64 via the dubbing switch 58, and is rewritten at high speed.

Now, the image data in the memories 62 and 64 match, and the monitor screen and the image data to be recorded match.

When writing is completed, the write enable signal W''''ff for the memory 64 is inverted, and image data cannot be written thereafter. The dubbing switch 58 also automatically returns to its original state and switches to the terminal d side (G in the same figure). To cancel dubbing mode, press the shutter switch 1 again during playback.
22 or switch the mode switch 120 to the continuous side.

With the above configuration, it is possible to mix the audio signal Sa and the video signal Sv in accordance with the current audio format. In this case, the number of quantizations of the audio signal Sa decreases from the current 16-bit configuration to 10-bit configuration, but the deterioration in sound quality caused by this decrease in the number of quantizations is small. Furthermore, since the video is a still image, 6-pit quantization is sufficient.

When the digital signal DS, which is a mixture of the audio signal Sa and the video signal Sv, is to be played back using the current DAT, that is, as shown in FIG. No. 8 DSv
When reproduced as a digital audio signal DSa, there is almost no effect on the audio signal Sa.

In that case, for the audio signal Sa, the video signal Sv
is nothing but a noise component. However, as is clear from the second mC, since the digital video signal DSV is inserted into the lower bit side of the digital audio signal DSa, the audio signal Sa can have a dynamic range of about 6NdB.

Therefore, as mentioned above, if the quantization number N is selected to be about 10 pits, a compact power set, Dolby B (
Quotient 4! A) The dynamic range is comparable to recording and playback. For this reason, even if the video signal Sv is played back at the same time, there is almost no effect on the audio signal Sa, and there is little deterioration in sound quality.

If the bit combination positions are reversed so that the least significant bit data ■0 of the digital video signal DSv becomes the least significant bit data AO{II of the digital audio signal DSa as shown in FIG. The effect is practically negligible.

As for the post-recording process, although audio I No. 8 is used as an example of post-recording, it is also possible to perform post-recording on a video signal, or to select one of them.

In the above, T=16. Although the explanation has been made assuming that N=10 and M=6, the values of N and M are not limited to these as described above.

[Effects of the Invention] As explained above, according to the present invention, when recording and reproducing video signals such as still images in addition to audio signals at the same time, the two are mixed in accordance with the DAT audio format. It is something.

Further, in this case, since the time axis of the video signal is converted and mixed with the audio signal, compatibility with the current 1TE 4L 1 type (DAT) can be achieved.

Of course, efforts have been made to minimize deterioration in the sound quality of the reproduced audio signal.

Therefore, it becomes possible to record and play back both current models and dedicated models that incorporate this signal processing device, and the effect on audio signals can be practically ignored, so attached equipment such as DAT for events can be used. It is extremely suitable for use as a

[Brief explanation of drawings]

FIG. 1 is a system diagram showing an example of the digital signal No. 48 processing device according to the present invention, FIG. 2 is a configuration diagram showing an example of the audio format of digital signal No. 8, and FIGS. 3 to 7 are identification codes, respectively. FIG. 8 is an explanatory diagram of bit inversion processing of a digital video signal, FIG. 9 is a waveform diagram of post-recording processing, and FIG. 10 is a system diagram showing an example of a current DAT. 1 0 ・ 20 ・ 36 ・ 58 ・ 60 ・ 76 ・ 80 ・ 82. 90 ・ 92 ・ ・Signal processing device・D combination means・Separation means・Dub record switch◆Video signal memory means・Sync pit shift encoder・Identification code generator・Signal processing circuit◆Sync bit shift decoder 94・Sa・DSa・Sv・DSV ・・Identification code detection circuit・Audio signal・Digital audio signal・Video signal・Digital video signal

Claims (1)

[Claims] (1) A digital device in which the upper N bits (N is an integer) are used as an audio signal, the lower M bits (M is an integer) are used as a video signal, and this video signal is added to the audio signal or separated from the audio signal for signal processing. In the signal processing device, the audio signal is A/D converted using a sampling clock fs that conforms to the signal format of a digital audio tape recorder, and the video signal is A/D converted using a sampling clock fs having a frequency that is an integral multiple of the subcarrier.
This A/D converted video signal is synchronized with the sampling clock fs and its time axis is converted to have the same time axis, and then added to the audio signal. A signal processing device for digital signals, characterized in that: