JPH03150933A - Data transmission system - Google Patents

Abstract

PURPOSE:To reduce number of pins of a connector interconnecting equipments by superimposing a modulation signal onto a power line driving circuit components in the equipment so as to send a data between the equipments. CONSTITUTION:When a data signal is sent from an equipment to other equipment, e.g. from a storage device 1 to a terminal equipment 30, a modulation demodulation circuit 4a superimposes a modulation signal of a sent data signal onto a power line 16a. The modulation signal on the power line 16a is inputted to a modulation demodulation circuit 4b via a power line 16b and demodulated to be a demodulation signal representing a sent data. Thus, it is not required to provide exclusive signals pins for data transmission and reception to the connector interconnecting equipments and number of pins of the connector is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transmission method for transmitting data between, for example, a terminal and a portable semiconductor storage device.

[Conventional technology]

FIG. 3 is a block diagram showing the configuration of a portable semiconductor memory device for explaining a conventional data transmission system. In the figure, 11 is a static RAM capable of data writing/reading by transferring data with a terminal (not shown) via an address bus 26, a data bus 27, and a control bus 28, and 3 is a static RAM whose voltage on a power line 16a is higher than a specified value. This is a power supply control circuit that establishes conduction between the power supply line 16a and the internal power supply line 19 when the internal power supply line 19 is reached. Further, the power supply control circuit 3 sends a high level signal to the reset signal line 25.

! 4 is a power supply limiting resistor 1 when there is no voltage on the power line 16a.
3 and an internal battery that supplies voltage to the internal power supply line 19 via the reverse charge prevention diode 12. 15 is a capacitor for removing noise on the internal power supply line 19; 17a;
is the ground wire of the power supply.

The ground wire 17a is at a reference level, which is normally O■.

Next, the operation will be explained.

Now, when a voltage higher than a specified value is supplied from the terminal to the power line 16a, the power supply control circuit 3 makes the power line 16a and the internal power line 19 conductive. Therefore, a high level signal is sent to the reset signal line 25 at the same time that the internal power line 19 is supplied with the voltage of the power line 16a. Statec R
When a high level signal is applied to the AMII signal line 25, the AMII enters an enabled state (operable state). At this time, the terminal is connected to the address bus 26. Via the data bus 27 and control bus 28, the static RAM 1l can be accessed (data written/continued). This operation is a well-known technique and will therefore be omitted. Further, since the potential of the internal power supply line 19 is higher than the potential of the internal battery 14, the internal battery 14 does not consume current due to the action of the diode I2.

- Power line 16a, internal power line 19 and internal battery 1 for boat fishing
The potentials of 4 are 5V, 4.5V, and 3■, respectively. Next, when there is no voltage on the power supply line 16a, the power supply control circuit 3 cuts off the connection between the power supply line 16a and the internal power supply line 19. At the same time, a low level signal is sent to the reset signal line 25. Therefore, the static RAM II is disabled (
(operation prohibited). At this time, the voltage of the internal battery 14 is supplied to the internal power supply line 19 via the resistor 13 and the diode 12. Therefore, the data stored in the static RAM 11 can be retained. The resistor 13 connects the internal battery 14 from the internal power supply line I9 when the diode 12 breaks down.
limit the current flowing into the Capacitor 15 removes noise superimposed on internal power supply line 19.

[Problem to be solved by the invention]

As explained above, the conventional data transmission method uses an address bus 26. Signal lines such as a data bus 27 and a control bus 28 are required. For example, Statec R
If the memory capacity of AMII is 1M bits, the address bus 26 requires address lines A0 to A16, resulting in 17 signal lines, and the data bus 27 requires data lines D.
Since 0 to D7 are required, the number of signal lines becomes eight. Further, the control bus 28 requires at least three lines: a chip enable signal line, a write enable signal line, and an output enable signal line. Therefore, in order to connect a portable semiconductor memory device to a terminal, the power supply line 16a and the ground line are required! ? Including A, 30 bin connectors are required.

As described above, according to conventional data transmission methods, the number of connector pins increases as memory capacity increases, memory types change, data bus length increases, additional functions change and improve, etc. This causes problems such as an extremely large force for inserting and removing the connector, a decrease in contact reliability, and an increase in cost. Also, as the number of connected connectors increases, the influence of external noise increases (
Therefore, a problem arises in that the reliability of data processing decreases.

This invention was made to solve the above-mentioned problems, and it is possible to dramatically reduce the number of pins of connectors that connect devices, as well as increase memory capacity, change memory types, and data bus length. There is no need to increase the number of connector pins even if the connector is expanded, or additional functions are changed or improved. This improves the reliability of connector contact, reduces the influence of external noise, and increases the reliability of data processing. The purpose is to provide a data transmission method that can improve performance.

[Means to solve the problem]

The data transmission system according to the present invention includes modulation/demodulation circuits 4a and 4b that modulate a data signal to be transmitted to create a modulated signal and demodulate a received modulated signal to create a demodulated signal.
A device that transfers data (portable semiconductor storage device 1,
The modulated signal is superimposed on power supply lines 16a and 16b provided in each terminal device 30) for driving circuit elements within the device, thereby transmitting data between the devices.

[Effect]

For example, when transmitting a data signal from a device (storage device 1) to a device (terminal device 30), the modulation/demodulation circuit 4a superimposes a modulated signal of the data signal to be transmitted onto the power supply line 16a. The modulated signal on the power source cotton 16a is input to the modulation/demodulation circuit 4b via the power source line 16b, and becomes a demodulated signal representing the demodulated and sent data.

〔Example〕

FIG. 1 is a block diagram showing the configuration of a data processing device using a data transmission method according to an embodiment of the present invention. In FIG. 6, a portable semiconductor memory device 1 includes a filter 2a, a filter 2a,
Power supply control circuit 3, modulation/demodulation circuit 4a, CPU (central processing unit) 9, oscillation circuit 10, static RAM II, coupling capacitor 12a, reverse charging prevention diode 12, current limiting resistor 13, internal battery 14, capacitor 15, power supply line 16a, power supply grounding line 17a, first internal power supply line 18
, a second internal power supply line 19, and the like.

The filter 2 a removes the modulated wave superimposed on the power supply line 16 a (more specifically, superimposed on the power supply voltage) and sends the power supply voltage to the first internal power supply line 18 . When the voltage reaches a specified value or more, conduction is established between the first internal power supply line 18 and the second internal power supply line 19, and
For example, a high level signal is sent to the reset signal line 25. The modulation/demodulation circuit 4a includes a switching circuit 5 that switches between the reception modulation signal line 20 and the transmission modulation signal line 22 (switching the movable contact C to contact A or contact A), an amplifier circuit 6 that amplifies the reception modulation signal, and It includes a demodulation circuit 7 that demodulates the modulated signal amplified by the circuit 6, and a modulation circuit 8 that modulates the data signal to be transmitted. CPU9 is an oscillation circuit lO
The static RAMI performs calculations and controls according to the clock signal output from the
Write/read data to/from I. Static RAM II address bus 26, data bus 27
The control bus 28 is not directly connected to the terminal as in the conventional case, but is connected to the input/output terminal of the CPU 9. The internal battery 14 is used as a static RAM when the storage device 1 is carried.
Back up the data stored in II.

Capacitor 15 removes noise on internal power supply line 19.

The terminal device 30 includes a filter 2b that removes the modulated wave superimposed on the power line 16b and prevents it from being applied to the power line 32, and a filter 2b that modulates the data signal to be transmitted to create a modulated signal and modulates the received modulated wave. It includes a modulation/demodulation circuit 4b that demodulates a signal to create a demodulated signal, a coupling capacitor 12b that passes the modulated signal, and a control section 31 that performs various controls for transmitting and receiving data to and from the storage device 1. The power line 16b and ground line 17b of the terminal 30 are connected to the power line 16a of the storage device 1.
and the ground wire 17a, respectively.

In this embodiment, a connection between a portable semiconductor memory device 1 and a terminal 30 is shown. Data transmission between the storage device l and the terminal device 30 is performed by serial transmission, and the data signal is modulated and sent to the power supply line 16.
This is done by superimposing it on a and 16b. Since data is transmitted using a power line, there is only one transmission line (more specifically, two lines, a power line and a ground line), so signals cannot be transmitted in both directions at the same time.

Therefore, from the terminal 30 to the storage device 1, the storage device 1
It is necessary to alternately transmit data from the terminal 30 to the terminal 30. - There is a half-duplex transmission method as this type of data transmission method for boat fishing. Furthermore, as a method of synchronization, start-stop synchronization is often used. Since these transmission procedures are well-known techniques, their explanation will be omitted here. As described above, in this invention, data is transmitted and received using the half-duplex, start-stop cycle method. Furthermore, in order to superimpose data on the power supply line, which is a feature of the present invention, it is necessary to modulate and superimpose data, since it is impossible to use a 5V binary signal for boat fishing. Modulation methods include amplitude modulation, frequency modulation, phase modulation, etc., and here, a method using amplitude modulation is adopted. Second
The figure shows the modulation and demodulation signals.

Next, the operation of this embodiment will be explained. The terminal device 30 and the storage device l are connected, and the power line 32 is connected to the power line 16a.
When a voltage is supplied from the first internal power supply line 16b through the power supply line 16b, the power supply control circuit 3 switches between the first internal power supply line 18 and the second internal power supply line 19 when the voltage of the first internal power supply '4fA18 reaches a predetermined voltage value or higher. conduction. As a result, the power supply voltage is supplied to the second internal power supply line 19, and at the same time, a high level signal is sent to the reset signal line 25. At this time, C.P.
U9 is released from reset and becomes operational. On the other hand, the static RAM II also becomes operational, and data signals can be sent and received at any time. Here, the filter 2a removes high frequency components of the modulated signal, and the first internal power supply line 18 is supplied with a power supply voltage from which the high frequency components have been removed. The CPU 9 uses the switching circuit 5 as an operation for canceling the reset.
is controlled by the signal on the transmission/reception switching signal line 24, and the movable contact G is set to the contact a side to enter the receiving state.

Now, consider the case where a data signal is written from the terminal device 30 to the CPU of the storage device 1. The control unit 31 of the terminal 30 modulates the write data signal with the modulation/demodulation circuit 4b, and superimposes the modulation signal of the data signal from the capacitor 12b onto the power supply line 16b.

At this time, the switching circuit 5 of the storage device 1 is in a receiving state, and the movable contact C is connected to the contact a. Therefore, the modulation signal is transmitted through the power line 16b, the power line 16a, and the capacitor 12.
a, switching circuit 5, reception conversion 1! The signal is transmitted in the order of the signal line 20. The waveform of the signal on the reception modulation signal line 20 at this time is as shown in FIG. It is demodulated by the circuit 7 and becomes a demodulated signal.This demodulated signal is transmitted through the demodulated signal line 21a, and as shown in FIG. ) is an asynchronous signal with the same waveform.

The CPU 9 processes this start-stop synchronization signal and writes a data signal to a predetermined static RAM II. data bus 27
Since they are connected by a control bus 28 and a control bus 28, writing can be performed using a well-known technique.

Next, when the terminal device 30 reads a data signal from the static RAM II of the storage device 1, it sends out a predetermined command code to put the control section 31 into a receiving state. CP of storage device 1
U9 is the movable contact G of the switching circuit 5 according to the above instruction code.
After connecting to the contact side, data signals are sequentially read from the corresponding area of the static RAM II, and data signals are sequentially sent to the modulation circuit 8 via the transmission signal line 23a. Modulation circuit 8 amplitude modulates the data signal. This modulation signal is transmitted to the capacitor 12a, the power supply line 16a, the power supply &
b, and is input to the modulation/demodulation circuit 4b via the capacitor 12b, where it is demodulated. This demodulated signal is input to the control section 31 via the demodulated signal line 21b. Therefore, the control section 31
will process the read data signal from the static RAM II. Information can be exchanged between the storage device 1 and the terminal device 30 by alternately performing the write/read operations as described above between the storage device 1 and the terminal device 30.

Next, when there is no voltage on the power supply line 16a, the voltage on the second internal power supply line 19 becomes low level due to the action of the power supply control circuit 3, and the static RAM II becomes disabled.
A voltage is supplied to the second internal power supply line 19 from the internal battery 14 via a resistor 13 and a diode 12 . Therefore, the data stored in the static RAM II is retained.

As described above, in the above embodiment, data is transmitted and received between the terminal device and the portable semiconductor memory device via the power supply line, so that only two connector pins are required for connection with the terminal device. Furthermore, increasing memory capacity, changing the type of memory, and changing or improving additional functions can all be addressed by changing the content of communication data, so the number of pins on the connector, which is the means of connection with the terminal, can be addressed. You can leave it at two.

Note that although static RAM II is used in the above embodiment, it may be replaced with other semiconductor memory. in this case,
Internal battery 14, resistor 13, and diode I2 may also be omitted. Furthermore, the portable semiconductor memory device 1 is a CP
Since U9 is built-in, security functions can be easily provided. Further, although the amplitude modulation method is employed in the above embodiment, other modulation methods may be employed. Further, in the above embodiment, the power supply voltage is set to 5.5 cm, but the power supply voltage is not limited to this, and it is sufficient to supply a power supply voltage corresponding to the operating voltage of the circuit element.

〔Effect of the invention〕

As described above, according to the present invention, a modulation/demodulation circuit that modulates a data signal to be transmitted to create a modulated signal and demodulates a received modulated signal to create a demodulated signal is installed in each device that is the target of data transmission. The above modulation signal is superimposed on the power supply line for driving the circuit elements in the device, and data is transmitted between the devices. Therefore, a signal pin dedicated to sending and receiving data is connected to the connector that connects the devices. (This allows the number of pins on the connector to be dramatically reduced to, for example, two, as well as increasing memory capacity, changing the type of memory, extending the data bus length, and changing or improving additional functions.) etc., it is no longer necessary to increase the number of connector pins, and security functions can be added easily.Therefore, the reliability of connector contact is improved, and the influence of external noise is reduced (and data processing is This has the effect of improving reliability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a data processing device using a data transmission system according to an embodiment of the present invention, FIG. 2 is a signal waveform diagram for explaining modulation/demodulation operations in this embodiment, and FIG. Figure 3 shows a portable semiconductor device for explaining a conventional data transmission method...modulation/demodulation circuit, 16a,
16b...Power line, 30...Terminal (
Device).

Claims (1)

[Claims] Each device that is the target of data transmission is equipped with a modulation/demodulation circuit that modulates the data signal to be transmitted to create a modulated signal and demodulates the received modulated signal to create a demodulated signal, and drives the circuit elements in the device. A data transmission method characterized in that the modulated signal is superimposed on a power supply line for transmitting data between devices.