JPH03148994A - High definition television signal transmission device - Google Patents

Abstract

PURPOSE:To transmit a video signal by the payload of STM-4 advised by CCITT and in addition, synchronizing it with a network side clock by reducing information quantity by removing the horizontal blanking signal of every video component signal, and simultaneously, providing a buffer memory. CONSTITUTION:After the video signals Y,PR,PB are band-limited into 20, 7, 7 MHz respectively by low pass filters LPF 111 to 113, they are converted into the parallel signals of 8-bits by A/D converters A/D 114 to 11b by sampling frequencies 44, 55, 14.85, 14.85 MHZ, and after the horizontal blanking signals are removed by removing parts HBR 117 to 119, they are divided into four parts, and are synchronized respectively with the network side clock through the buffer memories, and generate the video frames of variable length frames together with video headers and stuffing signals by the frequency of a horizontal synchronizing signal. Further, after the frames of STM-1 are generated by adding the signals called section-over signals, they are multiplexed by a byte multiplexing part 131 by a byte unit, and the frame of STM-4 of transmission rate 622.08 Mb/s is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a device for transmitting a high-definition television video signal.

BACKGROUND ART FIG. 5 shows the configuration of a conventional device for transmitting video signals of high-definition television.

The video signals are component signals Y, PR, and PO defined by the BTA studio standard. The bandwidth is 30 MHz each.

In Fig. 5, 501, 502, and 503 are low-pass filters LPF, each with a cutoff frequency of 20
．． 7. Limit the band of the video signal at 5 MHz. 5
04.505.506 is an analog/digital converter A/D, which converts a band-limited video signal into an 8-bit parallel digital signal. The sampling frequency is 44.55 (1320fH) and 14, respectively.
．． 85 (440fI(), 14.85 (440fs
) MHz. Note that fI (is the horizontal synchronization frequency (33
, 75KHz). 507.508.509.51
0.511.512 is parallel/serial converter P/S
and P/S 507 has an 8-bit Y signal and 1
A total of 9 bits of the bit frame pattern synchronization signal F are converted into serial data. P/S508 and 509 are
The 8-bit Y signal and 1-bit dummy signal are converted into serial data. The P/S 510 serially converts the 8-bit PR signal and the 1-bit dummy signal.

The P/3511 converts an 8-bit PR signal and a 1-bit dummy signal into serial data. P15512 is
Converts the output signal from P/S 507.508.509.510.511 to serial. 513 is a scrambler SCR, which performs an exclusive OR of the output of the P/S 512 and the PN sequence signal.

Next, the operation of the above conventional example will be explained. The video signals are band-limited by LPFs 501 to 503, respectively, and then analog-to-digital converted by A/Ds 504 to 506 to be converted into 8-bit parallel signals. The Y signal is branched into three, each with tLP/S 507 to 509.
is input. At this time, the frame synchronization signal F is input in parallel to one of the P/S 507 to 509, and the other P/S
Dummy signals are input in parallel to 1550B and 509. The PR and PI signals are similarly input to the P/S 510 and 511 together with a dummy signal.

The output signal of each P/S 507 to 511 is output from another P/S.
/S 512 and is converted into a serial signal to form a video frame.

In FIG. 6, each P/S 507 to 512 in FIG.
The output of 514.515.516.517.518.51
Nine frame patterns are shown. That is, each P
Outputs 514 to 518 of /S 507 to 511 are 9-bit frames with 1-bit F and D signals added to 8-bit Y signal, PR signal, and P8 signal, respectively, and output 519 of P/S 512 is , these are serially added to form a 45-bit frame. And the overall transmission speed is (44,55+14-85+14°85)
X9=668.25 Mb/s.

In this way, even with the above-mentioned conventional transmission device, the bands of high-definition television signals, that is, Y and PISps signals are 2017 MHz and 4 MHz, respectively, and the sampling frequency is 4 MHz.
1 55.14.85.14.85 MHz video signals can be transmitted.

Problems to be Solved by the Invention However, since the transmission speed of the above-mentioned conventional high-definition television signal transmission device is 668.25 Mb/s, the broadband ISDN currently recommended by CCITT is
NN I (Network Node I
Transmission speed at 622.08Mb/s
STM-4 (CCITT G707.708.70
There was a problem in that it could not be applied to the frame format (see 9). Furthermore, conventional devices have a problem in that they cannot transmit video signals in synchronization with the network clock.

The present invention solves these conventional problems, and allows video signals to be transmitted using the STM-4 payload recommended by CCITT, and can be transmitted in synchronization with the network clock. The purpose is to provide an excellent high-definition television signal transmission device.

Means for Solving the Problems In order to achieve the above object, the present invention reduces the amount of information to be transmitted by removing the horizontal blanking signal of each video component signal, and by providing a puff 7 memory. , and can be transmitted in synchronization with the network side lock.

Therefore, according to the present invention, by removing the horizontal blanking signal, the information amount of only the video signal can be reduced from 2200 (1320+440+440) samples to 1920 (1152+384+384) samples per horizontal period. That is, 594Mb/
s (2200X33.75KHzx8bit) to 5
18-4Mb/s (1920X33.75KHz
H4 (139 bits) in STM-4 in NNI of Broad ISDN.
, 264 Mb/s)x4 information transmission rate 557.056
It has the effect that it can be kept within Mb/s. Further, by providing the puffer memory, an effect is obtained in that an asynchronous video signal can be transmitted in synchronization with the network clock.

Embodiment FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 1, 111, 112, and 113 are low-pass filters LPF, each having a cutoff frequency of 20.7.7 MHz as in the conventional example, and high-definition video signals Y,
Bandwidth limitation for PR and PB is performed. 114.115.116
is an analog/digital converter A/D, which converts band-limited Y1PR and PB signals into 8-bit parallel digital signals. The sampling frequencies are 44.55 (1320 fH) and 14.85 (
440ftl), 14. 85 (440fH) M
It is H2. Note that fH is the horizontal synchronization frequency (33°75
KHz). Reference numerals 117, 118, and 119 are horizontal blanking signal removal units HBR, which perform sampling of the YlPR and Pa signals at 1320f11.440fH, respectively.
1152fH, 384fH from 440fll, respectively.
Reduce to 384fH. #1, #2, #3, #4 are H8
This is a channel for branching the 8-bit parallel signal from R117, 118, and 119 into four parts and transmitting two bits each. 120, 121, 122 are each channel #1
It is a serial/parallel converter (hereinafter abbreviated as S/P) provided for each #4 to #4, and each 2-bit YlP
Convert the R, pH signal into an 8-bit parallel signal. 1
A buffer memory 23 synchronizes each video signal with the network clock. 124 and 125 are counters and phase comparators for performing this network synchronization. 126 is a multiplexer for adding a video header to the frame. 127 is a buffer memory for speed conversion. 128 is a scrambler for keeping the mark rate of highly correlated video signals close to constant.

129 is the SOH whose speed has been converted by the puffer memory 130
(Section overhead, CCITTG707, G7
08, G709)) is a multiplexer that multiplexes byte. 131 is 4 S from channels #1 to #4
This is a byte multiplexing unit that multiplexes TM-1 format signals by byte. 132 is a scrambler that scrambles the output signal from the byte multiplexer 131 to bring the mark rate of the signal on the transmission path closer to 1/2. 13
3 is a parallel/serial converter P/S for converting a parallel signal into a serial signal. 134 is a timing clock generating section that generates timing pulses for each section.

Next, the operation of the above embodiment will be explained. Video signals with a bandwidth of 30 MHz specified by BTA's studio standards are processed by low-pass filters LPF111 to 113.
After being band limited to 0.7 MHz, the sampling frequency is set to 44.55 (1320 fll), 14
．． 85 (440fH), 14-85 (440fo
) MHz and is converted into an 8-bit parallel signal. Next, horizontal blanking signal removal units HBR117 to HBR119 each output 1320f■
, 44oro, and 44oro are reduced to 1152fH, 384fH, and 384fH, respectively. As a result, (1320fo+440fu+440
fu) x 3 bits = 594 Mb/s information amount (1152fII + 384fI++384fII
) x 8 bits = 518-4 Mb/s. Next, horizontal blanking removal parts HBR117 to 119
The 8-bit parallel output signal from
Each bit is divided into four channels #1 to #4. The 2-bit Y, PR, and PI signals of channel #1 are as follows:
The signals are input to serial/parallel converters S/P 120 to 122, and are converted into 8-bit parallel signals, respectively. The parallel signals output from the serial/parallel converters S/P 120 to 122 are synchronized with the network clock in the buffer memory 123.

Next, this network synchronization will be explained with reference to FIG.

In FIG. 2, writing of each video signal into the buffer memory 123 is performed using a Y signal sampling clock 44-5.
The reading is done using a clock that is 5MHz divided by 4.
Clock synchronized to the network, here 65.088MHz
The clock frequency is 16°2 MHz, which is obtained by dividing (9X (226X4)X8KHz) by 4. The phase comparator 125 identifies the edge of the horizontal synchronizing signal pulse at the network side clock frequency of 16.272 MHz. Next, the counter 124 that counts the 16.272 MHz clock is reset using the output pulse at the time of identification. The readable time of the buffer memory 123 is set at the cycle of resetting the counter 124.

As a result, the video frame has a frame length of 482.133 bytes (16,272 MHz) as shown in Figure 3.
/33.75kHz) variable length frame. 482
．． 133...2 bytes are the video header, 288 (=1152/4) bytes are the Y signal, 96
(=384/4) pi) X2 is PR%pa signal, 0-
133... bytes are stuff signals. A video header is added at multiplexer 126. In this way, since a video frame is configured with the period of the horizontal synchronization signal and stuff ink is performed at the end of the frame, the influence of stuff jitter on image quality can be reduced in appearance.

Furthermore, since the frame is configured as a variable length frame, the influence of stuff jitter can be reduced compared to a fixed length frame.

Returning to FIG. 1, the video signal synchronized with the network side clock in this way is stored in the buffer memory 127 at 1-272 bits.
The speed is converted from Mb/s to 19.44 Mb/s. FIG. 4 shows the SOH (section overhead) speed converted to 19.44 Mb/s from the pub buffer memory 130 by the multiplexer 129 after the mark rate of the strongly correlated video signal is brought close to a constant value by the scrambler 128. Byte multiplexing into a frame format such as The signal speed is 19.44Mb/sx8 (Larel (155,
52Mb/s serial) and STM in Broad ISDN NNI recommended by CCITT.
-1 (see CITT G707.708.709) format. Note that the hatched portion in FIG. 4 is the area in which the video signal of the video frame shown in FIG. 3 is used. In addition, in Fig. 4, the video signal area and SO
Items other than H are surplus. Then, the byte multiplexing section 131 byte multiplexes the four STM-1 format signals of channels #1 to #4, and the output signal is sent to the scrambler 13.
2, and the mark rate of the signal on the transmission path approaches 1/2. At this time, scrambler 13
2, the first row of the SOH signal is not scrambled. Then, 77.76Mb/s (19,44Mb
/sx4), 8-bit parallel input signal to 622.0
Converts to 8 Mb/s serial signal and outputs signal in STM-4 frame format.

As described above, according to the above embodiment, since the horizontal blanking signal of the video signal is removed and transmitted, the transmission speed can be reduced, and the high-definition video signal can be transmitted using STM-4 recommended by CCI TT. This has the advantage that it can be transmitted in a frame format of Further, according to the above embodiment, since the Puffer memory is used, it has the effect that signals can be transmitted in synchronization with the network clock.

Effects of the Invention As is clear from the above examples, the present invention has the following advantages: 20.7,
High-definition video signals Y, P band-limited to MHz
By removing the horizontal blanking signal, it is possible to transmit R, PB at a lower transmission rate than the conventional transmission rate of 668.25 Mb/s.
Transmission speed recommended by ITT: 622, 08M
The present invention has the advantage that it is possible to transmit data in the STM-4 frame format of b/s, and to realize a transmission device that complies with the CCITT recommendations. Furthermore, since the video signal can be synchronized with the network using the Babufa memory, it has the effect that the signal can be transmitted in synchronization with the network clock. Furthermore, since the video frame is constructed with the period of the horizontal synchronization signal and stuff ink is performed at the end of the frame, there is an effect that the influence of stuff jitter on image quality can be reduced in appearance. Furthermore, since it has a variable length frame structure, it has the effect of being able to reduce the influence of stuff jitter compared to fixed length frames.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a high-definition television signal transmission device according to an embodiment of the present invention, FIG. 2 is a block diagram of main parts of the device, and FIG. 3 is a frame configuration diagram of a video signal in the device. FIG. 4 is a diagram showing the transmission frame configuration of channel #1 in the same device, FIG. 5 is a schematic block diagram of a conventional high-definition television signal transmission device, and FIG. 6 is a frame diagram of the video signal in the same device. . 111.112.113...Low pass filter, 11
4.115.116...Analog/digital converter, 117.118,119-...Horizontal blanking signal removal section, 120.121,122...Serial/parallel converter, 123.127.130... Buff 1 memo, 124
...Counter, 125...Phase comparator, 126.129...Multiplexer, 128.132
... Scrambler, 131... Byte multiplex unit, 133... Parallel/serial converter, 134...
Each part timing block generation part. Name of agent: Patent attorney Shigetaka Awano
2 Fig.lηri〉Tabi 1 124 1 Previous Pass Ore Example l L-Ichiryo 11-11''V ``-- Fig. 3 S-・Itto y Fubatato Fig. 4 2% 35 C Beg A :l-To arbor-1/F/Matori Figure 6

Claims (1)

[Claims] 2 high-definition video signals Y, P_R, and P_B signals each
A low-pass filter for band-limiting to 0, 7, and 7 MHz, and an analog/digital filter for converting the band-limited video signal into 8-bit parallel digital signals at sampling frequencies of 44.55, 14.85, and 14.85 MHz, respectively. a converter, a horizontal blanking removal means for removing a horizontal blanking signal from each of the digitally converted signals, and outputs from the horizontal blanking removal means are divided into four branches and sent to the network side via buffer memories respectively. means for synchronizing with a clock and generating a video frame of a variable length frame at a horizontal synchronization signal period together with a video header and a stuff ink signal; and means for generating an STM-1 frame by adding a section overhead signal; 4 processed by means
The branched signals are multiplexed in byte units to achieve a transmission rate of 622
．． 1. A high-definition television signal transmission apparatus comprising means for generating STM-4 frames at 0.08 Mb/s.