JPH03148697A - Computer having self-building video circuit - Google Patents

Abstract

PURPOSE: To use various monitors by providing a programmable video circuit for transferring video data from a RAM to the monitor so as to supply video timing signals to the monitor and displaying the video data on the monitor. CONSTITUTION: Under the control of a CPU 13, a memory decoding unit MDU 12 receives video request signals from an RBV 14 and sends RAM control signals to the RAM 11. The RAM 11 sends the stored video data to the RBV 14. The RBV 14 receives frequencies A-C from the frequency sources 18-20 of the three different frequencies A-C and sends timing signals to the montior 27. Also, the RBV 14 supplies the video data through a bus 29 to a video A/D converter(VADC) 26. The VDAC 26 receives dot clock signals, composite blanking period signals and composite video synchronizing signals through signal lines 30, 31 and 33 and sends the color signals of RGB to the monitor 27. The monitor 27 displays images and sends monitor identification signals to the RBV 14.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to the field of digital computer displays and associated video circuits, and more particularly to microprocessor-based computer systems that generate video signals to be displayed on CRT monitors. I'm interested.

[Problems to be solved by conventional technology and invention]

Today, microprocessor-based personal computers (PCs) are widely used in education, science, business, and the home. As the range of uses for personal computers continues to expand, so too does the demand for faster, more flexible video capabilities. Therefore, computer manufacturers are actively seeking ways to improve the performance and adaptability of video display systems while reducing costs to customers.

-ff K The internal architecture of the personal combination unit is organized such that the same printed circuit board that contains the system memory and support logic also houses the central processing unit (CPU). This circuit board is generally called a "motherboard." Traditionally, if you want a video graphic display function, you are forced to purchase a separate video card, which is configured to be plugged into a slot that connects to the motherboard via a connecting bus interface. This card includes a 2-vote video random access memory (VRAM) that is used next to store video display data that is later output to the display device (i.e. monitor).The video timing circuit of the video card is Hibiki's configuration is tailored to one type of monitor, meaning the card can only be used with that type of monitor and not with another monitor. It was commonly used in machines such as the Macintosh series of computers, and is still widely used today.

However, there are some serious drawbacks to using a separate video card. Perhaps - a fundamental limitation in quantity is the display device connected to the computer, i.e. the type of monitor and the need for different video cards, or in some way when changing monitors (e.g. different This would mean that the system would have to be reconfigured by operating the selector switch. For example, if the computer used to generate graphics on a 15-inch portrait monitor requires an LLI-type video card,
Those coupled to a 9-inch black and white screen require a separate video card.

Therefore, changing monitors requires matching video cards, which ultimately reduces the flexibility afforded to the kneezer.

As you can see from the following explanation, this invention company, Computer Ki
This eliminates the need to use separate video cards or other forms of different video circuitry for different monitor types. That is, a wide variety of monitor types can be used without reconfiguring the computer's internal video circuitry.

The present invention utilizes a self-configuring video circuit that first identifies the type of monitor used and then selects one of a plurality of parameter sets corresponding to the type of monitor used. , achieve this. Those parameters are then provided to other parts of the display circuit. Therefore, the present invention allows connection to a wide variety of monitors without the need to replace the video circuit. As a result, for Nieser, the end result is no need to change cards, operate selector switches, or reconfigure the computer system when changing monitors.
This is far more convenient than before.

[Means for solving problems]

A computer is described that has a self-configuring video circuit that allows connection to a wide variety of monitors. The computer automatically senses the type of monitor to which it is coupled and then configures its internal circuitry to provide a compatible video signal to the monitor.

In one embodiment, a computer of the present invention includes a central processing unit (CPU) that executes a program to provide video data to be displayed on a monitor. Data Corporation, Random Access Memory (RAM) in Computers
K is remembered. The monitor supplies a separate signal to the video circuit Kll, where the video circuit supplies the monitor with both video timing signals and video data suitable for display on the monitor. The identification signal is used to configure the video circuit according to the monitor's requirements.

〔Example〕

A computer is described that has self-configuring video circuitry for connection to a wide variety of video display monitors. In the following explanation, in order to fully understand the present invention in KN,
Although many specific details are given, such as clock frequencies, register sizes, bit designations, etc., it will be obvious to those skilled in the art that the invention may be practiced without such specific details. Dew. In other instances, well-known circuits are shown in block diagram form in order to avoid obscuring the present invention unnecessarily.

Below, Maein manufactured by Apple Computer
Although the invention will be described in terms of a preferred embodiment based on a tosh l ci computer, it will be understood that the invention may be practiced on other computers and that numerous modifications may be made without departing from the spirit of the invention. You should understand.

Explanation will be made regarding FIG. A generally preferred generalized block diagram of the present invention is shown in FIG. Computer system 10 includes a RAM-based video device (R) that provides video display signals to a wide variety of display monitors.
BV) 14.

The RBV 14 has two basic parts: a video part that provides synchronization signals and data for a variety of different monitors (in the preferred embodiment, the RBV circuit supports four types of monitors), and a universal interface adapter (
The VIA section includes a plurality of 8-bit registers used for various input and output controls, video control, RBV chip test modes, and interrupt handling. CPU 13 communicates with these registers via an 8-bit bidirectional data bus that is separate from the 32-bit RAM data bus used by the video portion. This allows access to the Lujistor independent of video portion activity on a separate RAM data bus. In general, V of RBV
Parts of the IA are not material to an understanding of the invention. Therefore, VI
Part A will be explained only in terms of the strings that will be helpful in understanding the invention.

RBV device 14 is preferably fabricated as an integrated circuit (IC) using a metal oxide semiconductor (MO''S) process, 41 using complementary metal oxide semiconductor (CMOS) technology.

The RBV 14 operates in conjunction with a mail decoding unit (MDU) 12 and a random access memory (RAM) 11. Functions as MDU12ti memory control device, RB
The priority order of access to RAM11 by VI4 is determined. MDU12 has CPU13 and RAM11
The ROM 47 is designed to form a compatible interface between the ROM 47 and the input/output device 45 (see FIG. 2). In a generally preferred embodiment, the CPU
13 is Motorala CorporationOfl
It is a manufactured MC68030-f microprocessor.

RAM11 contains at least one dynamic memory (
DRAM) puncture is connected to RBVI4 via L, 32 pitnos (S line 21.RAM 11 companies, M
Preferably, there are two separate RAM punctures driven directly by DU12.

MDU12 is connected to RAMIIK via control line S2, and RBVI4 and MDU12 are connected to signal lines 22 to 25.
communicate with each other via. As will be described later, initial access to video data stored in RAM 11 requires five CPU clocks, followed by a two-clock burst access. Internally, MDU 12 includes a state machine and address multiplexer associated with the control of Punk A of RAM 11 in relation to the video request signal provided by RBVI 4.

Frequency timing for dot clock generation is obtained from three separate frequency sources 18-20.

Each of these frequency sources is a crystal oscillator circuit operating at one physical frequency. Frequency sources 18-20 are coupled to RAM-based video device 14 via signal lines 31-39, respectively. Using multiple frequency reference inputs is one way to adapt the computer of the present invention to different types of monitors. Although three frequency sources are shown, more than four may be used without departing from the spirit of the invention. Alternatively, a separate frequency source 18
~200 Alternatively, a single programmable or adjustable locking source may be used.

RBVI4 supplies video data to a video digital to analog converter (VDAC) 211 via bus 2g. VDAC21i has a color lookup table (CL
UT) and, in the preferred embodiment, Bro・ktree C
DAC, which is a Bt 478 device manufactured by Orporationll. VDAC 2B further receives a dot clock signal, a composite blanking (CRY, ANK) signal, and a composite video synchronization (CSYNC) signal from RBVI 4 via signals [30, 31, and 33, respectively. These signals vary depending on the type of monitor used and are used to organize the video timing of data on the monitor screen. VDAC 26 supplies red, green, and back (RGB) color analog video signals to monitor 27 via signal line 36 . monitor 2
7 is RBVI4, video timing horizontal synchronization (HSYNC) signal and vertical synchronization (VSYNC) signal,
Alternatively, a composite synchronization (CSYNC) signal may also be received. The monitor 21 sends a monitor identification (ID) signal via the signal line 35. Supply RBV14K.

As previously discussed, the generally preferred embodiment supports four types of display monitors. One of those monitors is directly driven by RBVI4, and the remaining three are driven by VDAC2.
Driven through B. Each type of monitor is identified by grounding certain bins at RBV. This automatically sets appropriate pixel clock and synchronization timing parameters. Generally, the four types of monitors supported by the preferred embodiment of the present invention are the 9-inch Macintosh 8E (Mac
8E), a modified apple 11-a5 monitor, and a Macintosh 1112 inch white/
They are a black and 13-inch color monitor, and a 15-inch portrait monitor (white/Kuromatasha color).

1E t ftj:, it-jH13sノ3 hif)
An overview of the monitors selected by the monitor jf-ID bin is shown. For driving the built-in 9-inch SE monitor, a separate bin is provided on the RBV chip (not shown in FIG. 1).

Table 1 1 MaciGNDI Ol 1 1 0 15JI
#Applell-G8 Monitor 1 Next, FIG. 2 will be explained. FIG. 2 shows a detailed block diagram of the RBV chip 14 along with its connections to the computer terminal 40. As shown in the figure, the CPU 13 connects various devices such as a ROM 47, an input/output device 45, a NUBUS 4B, and a VDAC 26 to a CPU data bus 50 and a CPU address bus 6.
It is connected via 5. Two banks of system memory auAM, namely Banhum (43) and Bank B
(42). Bank B RAM (4
2) is directly connected to the CPU data bus SOK, whereas the bus buffer 44tJ: The CPU data bus 50 can be separated from the Banhum RAM data bus 21. The generally preferred embodiment is a 74F245 Passbuffer available from Passbuffer 44.

Functionally, RBVI4 operates like a separate video card, even though it is integrated into the motherboard as an integrated circuit. To provide this functionality, the bus buffer 44 transfers the system RAM from CP to CP.
It may be selectively cut off from the U data bus 50. This makes it possible for 9.RBVI4 to independently access buffer A via RAM bus 21 of bank A.

The RBV uses data stored in banks 43 of system RAM to send a continuous stream of video data to display monitor 21 during the live video portion of each horizontal scan line. RBVI 4 #i asks the MDU 12 for the necessary data when needed. Therefore,
The MDU 12 connects the data bus 21 to the CPU data bus 5◎
Bank Af) RAM43 to RBVI4
8 long word page mode burst read to PIFO 54 located internally. Banks 43 and 42 are controlled by MDU 12 via RAM control path S2.

If a video burst is in progress, CPU access to the pantum 43 is delayed, effectively slowing down the CPU 13. This effect varies depending on the size of the monitor and the number of bits per pixel. Note that only access to the ROM pankum is performed (by video). Since the RAM bank B ij is directly connected to the CPU data bus 50, the CPU 13 always has full access to this bank, and the same is true for the iROM 47 and input/output device 45. It will be clear that the present invention may be practiced without bank B 42, or may be practiced with additional BAM banks on either side of bus buffer 44. Although the present invention would operate correctly without bank B42, adding bank B42 increases the efficiency and performance of the overall computer system by dedicating a portion of the memory to CPU 13.

The video portion of the RBVI4 has 16 to 32 bit first-in-first-out (FIFO) memory devices 54.

The memory device further includes logic for keeping the FIFOtRAM filled with data and logic for arranging and shifting out that data. RBV
14d, further includes a latch 53 used to strobe the video data appearing on the data bus H to the FIFOS 4 via the load pointer @SS. Video data is unloaded from FIFOS 4 via signal line 56 which couples to bit ordering device 57. Array device 5T is coupled to shift register 59 via signal line 58. The shift register 59 is a bit ordering device 5.
7)), the arranged video data is transferred to the video data bar λ.
Shift out to 2B. The tap selector 60 that connects the shift register 59 to the data bus 2sK will be described below.

Video PIFO 54 is divided into two halves each containing eight 32-bit long words. One FIFO
Once the last data of a half has been used (i.e. 1
For a 3-inch monitor, 8 bits per pixel, 1
In the case of a 5-inch monitor, if three long words have been previously used with four bits per pixel (1), RBV 14 lowers its data request output line 24 (VID, REQ). This video request line instructs the MDU 12 to operate the bus buffer 44 and disconnect the RAM data bus 21 of bank A from the CPU data bus 50. Also, as soon as possible, the data bus 21
Start page mode burst read of RAM data to. The MDU 12 then uses the RBV video data load input line 2s (VID, LD) to load valid RAM data to the RBV 14. Video data load input line 23 controls latch 53.

Each falling edge of the VID, LD pulse latches one 32-bit long word of RAM data into latch 53, stores the latched data in FIFO 4K, and then advances the input pointer to the next position in the FIFO. let Data is,
It is input to the video PIF 054 via the signal aSS coming out of the control latch 53. After the falling edge of the sixth VID, LD pulse, the RBV raises its video data request line (VID-REQ) 24. 7th VID,
If KVID, REQ#E/I occurs before the falling edge of the LD pulse, MDU 12 reads another long word (eighth long word) and ends the burst after RBV K strobes it. let Now the previously empty FIFO
half is filled.

While doing so, the other half of the FIFO transfers the eight data length words (the data loaded into the register from the previous burst read) via bus 58 to shift register 59.
It is also possible to load 16 bits at a time. After the 8 long words are unloaded from the second half of FIFO 4 (i.e. the second half is empty), the next 8 long words from the first half of FIFO In the first half, video data (which has been previously loaded) is loaded into the shift register 59. During this time, the second half-off of FIFOS4 (which was on !2 during the most recent load sequence) will cause the RA
Receive updated video data from M Banhum. 1
The half of a2 is filled into the passage 9 described earlier, and the entire pro-7 is repeated again. That is, FIFOS4
The two half-time periods alternately receive data from the KRAM bank A43 and load the data into the shift register S9.

Shift register 59 has eight output taps coupled to tap selector 60. Data is advanced through shift register 511 one bit at a time by a dot clock signal appearing on signal line 30. Eight output taps are located along the shift register to correspond to every other bit (ie, one for every two bits). One, two, four of those taps
By using one or all eight, the video data output bus can be loaded one bit at a time (one bit video).
or 2 bits at a time (2-bit video), or 4 bits at a time (4-bit video), or 8 bits at a time.
Data can appear bit by bit (8-bit video).

Needless to say, in order for the data to appear in the correct order on the output tap, the 16 bits must be loaded into the shift register 51B in the correct vhj order, depending on the number of bits per selected pixel. . This is the role of the bit order arrangement device 5T. This equipment company PIFO
54 along signal line 58 as well as the number of bits per pixel information appearing on signal aSS. For 1 bit/pixel video, only the last output tap is used, all 16 bits of the shift register are
Sixteen consecutive dots appear on his tap.

In contrast, in the case of 8-bit video, all 8 tags are used, and 16 bits are already sent out to the 2908 output lines of the video data bus after two dot clocks. There is. In any case, when all 16 bits have been sent out onto the video data bus, the primary 16 bits are loaded from the FIFO 54 into the shift register 58 and the FIFO output pointer is advanced. As a result of this, finally, that half-day of FIFo will be 1 in the sky. The firefly is empty & the FIFO 54 is half off, and the RAM data is another 8
(long word parsing) as described above.

Next, referring to FIGS. 5a to 5d, the arrangement of bits inside the shift register 59 for each case of 1 bit/pixel, 2 bits/pixel, 4 bits/pixel, and 8 bits/pixel The order is shown.

As is clear from the figure, in the case of %1 bit/pixel video, the arrangement of bits starts from 0, p) 151, which is located at tap 0, and continues sequentially. in this way,
1-bit video, data is output data path 29-8
When sequentially loaded or advanced on one of the book's output lines, it becomes . The remaining seven output lines of bus 29 are in a high state.

In case of 2-bit video, odd numbered bits are located in the left half of the shift register ending with tap l (i.e. odd bits from 1 to 15) and even numbered bits (i.e. even bits from θ to 14). is loaded into the right half of the shift register ending at tap O. Also in this case,
Output data bus lines connected to unused taps are in a high state.

In the case of 4-bit video, the bit arrangement is further input]
It is assembled. As shown, the bits are 12.8.4 and 00 bits shifted in that order starting from tap 0 and 1
The 4, 10.6 and 20 bits are shifted in that order from tap 2, the 13°9.5 and l bits are shifted in that order from tap 1, and the 15, 11, 7 and 3 bits are shifted in that order from tap 1.
The bits are arranged to be shifted in that order starting from tap 3.

For 8-bit video, Ka, use all eight taps as follows. That is, tap 0 shifts bit 8 and bit 0 in that order, tap l shifts bit 9 and bit l in that order, tap 2 shifts bit 10 and bit 2 in that order, and tap 3 shifts bit 10 and bit 2 in that order. Shift bit 11 and bit 3 in that order, tap 4 shift bit 12 and bit 4 in that order, tap 5 shifts bit 13
and bit 5 in that order, tap 6 is bit 1
4 and bit 6 are shifted in that order, and tap 7 shifts bit 15 and bit 6 in that order. For 8-bit video, all 116 bits have been shifted out after two dot clock periods.

In the taps shown in FIGS. 1 to 15 d, the most significant bits correspond to VID and OUTT K, and the least significant bits correspond to VI
D, 1 tap selector 60 to correspond to OUT OK
via the video data output bus 29 (e.g. VID
, OUT), respectively. To give one example:
For 8-bit video, each long word has 30 hits
, OUT6 K appears, Biy ) 251! VID,OU
T5, 28 hits VID.

OUT4, human 27 is VID, OUT3, human 26
uVID, OUT2, human 25 is VID, OUT1
゜And bit 24iJ: 1 at the same time as each appears in VID-OUTO, bit 31 is VID, OUT7
It is shifted so that it appears in . 1-bit video appears in the output bin VID, OUT OK, VID, O
UT 1 to VID, OUT 7 are held high (appears as l). Each long word from RAM starts at bit 31 as the monitor beam progresses from left to right, VID, VID, and bits Off without interruption.
Shifted out to OUT O.

As shown in FIG. 2, tap selector 60 is coupled to signal line 8sK to receive per-pixel bit number information to be output to video data bus 211. Once per video frame - once at the end of the vertical sync pulse - R
BV14a lowers its video reset (VID, RE8) output line 25 to reset the MDU's video address counter.

Then, just before the first scan line of live video, %8BY executes two 8 long word requests so that the video PIFO 54 starts completely full.

The K process then proceeds as previously described, with a new hiteodata word being shifted in at the same time as a word is shifted out.

When the RBV 14 is ready to accept input data consisting of eight long words from the RAM 43,
Lower the VID and REQ signal lines 24.

From that point on, the RBV waits for the memory controller 12 to strobe in the data. The memory control device 12 is
Data is strobe-in using the VID and LD signal lines 23. The RBV waits indefinitely for video data to arrive (but if it waits long enough it will eventually start shifting out old data in the FIFO again). RBV accepts any number of long words strobed in, but if K many long words are strobed in, the data will eventually overwhelm the data that has not yet been shifted out. Start overriding.

After the sixth OVID, LDx trope, the RBV 14 raises the VID, REQ signal line 24. This occurs even if the request for the next eight long words has already begun. 1c before the end of the 7th degree VID-LD strobe VI
D. If the REQ signal line 24 has gone up, MD
■12 is yet another long word (8th long word) RB”
/device Hestrop, then next (DVD, RE
Q signal (7th VID.

(appears at any time after the end of the LD strobe).

The RBV device 14 has no information regarding screen mapping or video addresses, it simply provides the memory controller with the correct data in the RBV on request, often 8
It is only assumed that they will be provided as a group of long words.

At the end of each horizontal sync pulse, RBV 14 lowers VID, RES line 25 for the time between two horizontal sync signals. Memory controller 12 uses this signal to reset the video address counter back to the start of the frame buffer.

Similarly, the memory controller 12 has no information regarding the video circuit or its parameters. When the memory controller senses that the VID and REQ signal lines go low,
wait until the current bank ARAM cycle is finished;
After the cycle ends, the data bus 21 is refreshed from the CPU data bus 50 by notifying the RAM path buffer to assume three states. Next, page mode burst reading of the RAM is started.

In addition, three signal lines (VID, REQ) are required for interaction between MDU 12 and RBV14.
.

It should be noted that VID, LD and VID, RE8) are only available. RBV14ti, memory or M
Does not store information regarding DUK. Similarly, MDU1
2 does not need to obtain information about the video. Each device simply communicates with the other device according to the three-wire hard-shaking scheme described above. With the help of Jin, the configuration of the system is greatly simplified and the MDU
The internal structure of both the RBV and RBV devices is also simplified. Furthermore, the flexibility of the system is improved. As long as the handshaking method is maintained, the R
Another video device or DMA-from- instead of BV
A RAM device could be used, or an ilB
It would also be possible to change one memory address and organization without affecting VK.

MDU12ti, one CPU clock cycle is the V
By lowering the ID and LD signal lines, long words such as ID and burst reading are transmitted. The MDU continues the page mode burst indefinitely - except for VID.

After seeing that the REQ signal @24 has returned to the high state,
, only once to stop reading. The address provided by MDU 12 for video burst reading is address so
Starting from ooo oooo, each VID and LD
Increment by one long word in . This is VID
, until the MDU 12 notices (using a 24-bit counter within the memory controller) that the RE8 signal line 25 has gone low. When VID and RES (video reset) go low, the counter inside the MDU12 goes to s.
ooooo.

000K is reset.

Next, FIG. 4 will be explained. FIG. 4 is a timing diagram showing the interaction between the RBV device and the MDU's RAM control. The signal transition 101 on the VIDiEQ signal line is RA
The process of video data transfer from M43 to FIFO 54 is started. Note that if the RAM 43 is currently involved in the RAM cycle together with the CPU 13, the MD
U12 waits until the RAM cycle is completed before issuing a notification to cause the 44 to assume the three states.

1 new CPU RAM as shown
The cycle started at 102 at the time of Hiro, but VID, R
Since the EQ signal line 24 is transitioning low, the CPU cycle is held off for the length of 20 clocks due to the 8 long word video burst. The start of the video read cycle occurs at time 103. 1k, RA for at least 5 clocks after the VID, REQ signal lines go low.
The data stored in M bank A begins to be stropped to the FIFO 54. The first long word of video data is VI
D, LD is loaded at the positive going transition 104 of the LD signal.

At 1050, the VID, REQ- signals are transferred to the terminal, and the MDU is notified to supply one more word of video data at the next positive transition of VID, LDO. . As shown, the last word of video data is loaded at the transition indicated at 100.

The video burst reading cycle ends at point 101. Subsequently, the continuation of the CPURAM cycle that was held off begins at time 1011.

However, at the next positive transition of VID and LD, V
Immediately after the MDU 12 detects that ID, REQ goes high, a new video request can be initiated.

This is illustrated in FIG. 4 by the dotted line 109 representing the transition towards 10-.

As mentioned above, the video shift register is 16 bits long and has taps on both bits. 8
For pit video, all taps are used, and each of the 16 data bits appears on %1 tap after two pixel clocks. If no new data is loaded, it will take 14 more pixel clocks before the 1 is shifted from the last tap. (l is shifted in to replace the old data bit that is being shifted out.) When horizontal blanking begins, the video shift register completes the shift operation so that one of the taps in use 1
All 6 data bits are 16 1-bit pixels, or 8 2-bit pixels, or 4 4-bit pixels, or 2
It appears in the form of 8-bit pixels. Horizontal blanking prevents new data from being loaded into the shift register. However, the shift register, which is constantly shifting because it is dot clocked, continues to shift out old data until it is completely filled with l. RBV14 is 14 pixel clocks in 8-bit mode and 1 in 4-bit mode.
2 pixel clock, 2 bit mode and 1! ', the old data continues to be sent out for the length of 8 pixel clocks, and for the length of 0 pixel clock when in 1-bit mode. From that point on, the shift register shifts all 1s until it is loaded with new data again. Mac
Since intosh 8E uses only 1-bit video, there is no old data to shift out after starting erasure. In other computers, signal line 6
1 (see FIG. 2) and input to VDAC 21i prevents old data from appearing on the screen.

Vertical blanking occurs after the start of horizontal blanking and after yet another eight long word burst of data from bank A43 is loaded into FIFO 54.

Those eight long words are not loaded into shift register 59Kd, and the shift register continues to shift l throughout the vertical blanking (after shifting out any old data that still remains). Before entering the vertical blanking sequence, all pointers are reset and VID, R
Since ES is pulled low, it resets the MDU's video address counter. Then, approximately two scan lines before the end of one vertical blanking, the PIFo 54 is loaded with 16 new long words of data that are ready for the start of live video. Replaces the previously loaded data.

Hiteo simultaneous envoys (HSYNC, VSYNC, CSYNC)
and CBLANK) is generated by the video counter device 69. Video counter device 69 is comprised of a series of programmable polynomial counters of the type well known in the art for use in generating video timing signals. The video counter of the video counter device 69 can provide the correct timing signal to the associated display device, i.e. the monitor, given the type of monitor and the number of bits per pixel condition. In this sense, it is a self-constituting form.

Next, Figure @3 will be explained. FIG. 3 shows standard horizontal and vertical timing waveforms, including horizontal blanking, live video, horizontal sync signal, vertical blanking, vertical live video scan line, and vertical sync signal. It shows the relationship between As known to those skilled in the art,
Parameters associated with horizontal timing and vertical timing vary depending on the type of display device, ie, monitor, used.

The monitor supported by this video system provides monitor type identification (ID) via a set of external signal lines, ie, a digital code that appears on the bin. In the present invention, the ID bit y of the monitor 21 is coupled to the monitor j (parameter register T1) via the 3-pit signal line 35.The type of monitor is connected to the video counter device 69 via the signal line 81, The monitor parameter register T1 supplies bit number information for each pixel to the video counter device 69 and the bit order arrangement device 51 via a signal @89.

Register 11 for monitor parameters is set by software.
The type of monitor can be read and the number of bits per pixel can be read from or written to the same register.

3 bit monitor! The D type of decoding results in the selection of one of four fixed nine parameter sets - four for each supported monitor. Those parameters are ``/)-k'')4r-d'' in step
Generates signals such as H8YNC and VSYNC. The only programmable parameter is the number of bits per pixel.

-8: In another embodiment, the monitor parameter register T1 or equivalent device may be fully programmable. It is believed that doing so would provide the system with the ability to set a large number of display parameters.

However, the only limitation is the size of the internal storage capacity of the register T1. In that case, the monitor ID bits would be decoded by software and then written to register 71 to provide all of the correct parameters to the associated display device.

The following table summarizes the relevant timing parameters (as shown in FIG. 3) provided to the RBV for the four types of monitors supported by the generally preferred embodiment of the present invention.

−〈′ Eight ＾ To To Eight Eight 1
1 V -no -noI %J
Referring to FIG. 6, the relative timing of the various synchronization signals is shown along with the VID, RES, and reset signals. As shown in Figure 6, VSY
During the last two horizontal sync pulse periods of NC, video counter device 69 pulls VID, RES signal line -25 low to reset the address counter of memory controller 12. This occurs at transition 11G in diagram g6. V
ID and RES return to high at the same time as the VSYNC signal transitions from low to high. Then the first part of the live video
% RBV 14 performs two 8 long word requests just before the % scan line, so the frame can begin with the FIFO full.

As described above, one monitor 21 supplies a 3-bit identification code to the monitor parameter register 11 via the path line 35. The RBV 14 then sets appropriate video timing and synchronization parameters for the video counter device 69. Bit number information for each pixel is also supplied to the bit order arrangement device 51 and the video counter device 69 via a signal line 89. Video counter device ss includes a plurality of polynomial counters of a type well known in the art. Depending on the type of monitor decoded, the RBV sets its counters to generate video timing signals according to Table 2 for the associated monitor.

Information regarding the type of monitor is also supplied to multiplexer 88 via signal line 81. - Depending on the type of monitor connected to the computer system, the multiplexer 88 can be configured with three clocks: the dot clock supplied by the oscillators 18 and 19, and the clock divided in half from the oscillator 20. , 30.2400MHz , 57
．． 2832MHz and 1N6672MHzK compatible)
Choose one from the following.

The branch clock from oscillator 20 is supplied to multiplexer 88 via signal line 41.

For example, if the monitor identification code indicates that monitor 2T is a modified Apple 11-Os RGB display, MUX 88 may
The clock signal (i.e., 15.6
672MHz). (The clock generator 66 is
The reference frequency generated on signal line 39 from oscillator 20 is divided into two and used to generate the correct dot clock frequency on signal line 41. Clock generator 66 also generates an input/output (Ilo) clock for input/output device 45. ) On the other hand, the monitor identification code indicates whether the display device is 12 inch black and white or 13 inch RGB OMac.
11, MUX88 is the oscillator 1
8 to select the reference frequency generated on the signal line 31 (ie, 30.2400 MHz). If you are using a 15-inch portrait monitor, MUX
1m8 would result in selecting the reference frequency (ie 57.2832MH2) from the oscillator Is appearing on signal line 38.

Table 3 summarizes the video signals that are activated or deactivated for some monitors.

31st R 00009 inch 5E VID-OUT (0-
7) HSYNC=10 Zoo
CBLANK CSYNC=10 0
11 8E, HSYNC0111
VSYNC -000115 inch port) VID, OUT (0
-7) SE-HSYNC=11 001 rate (
Ruri Prefecture) CBLANK CSYNC=1
0 101 (color) HSYNC11
01VSYNC 0010 Variation 11-as VID-OUT (0-7
) SE, I (SYNC=11 010
CBLANK HSYNC=10
1101 12 (4, VID, OUT (0-7) Is
E-HSYNC=11 110 13 inch can-CBLANK HSYNC=1CSYNC
VSYNC=1 1 000 efi stop None VID-
0171(()-7)Is1 100
CBLANK=01 0
11
CSYNC-l1 111
BE-HSYNC=IHSYNC=
1 It should be appreciated that even larger numbers of monitors can be accommodated by simply increasing the number of frequency sources and/or expanding the size of the associated registers and signal lines.

Therefore, while the invention has been described in connection with illustrative embodiments, this description is not to be construed in a limiting sense.

Various modifications of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art upon reference to this description. For example, instead of hard-wiring each parameter set, multiple programmable registers may be used, in which each parameter associated with each monitor type can be set by software. It is therefore intended that the appended claims cover all such modifications or alterations that fall within the spirit of the invention.

What has been disclosed above is a computer having a self-configuring video circuit that is adaptable to a wide variety of display monitors.

[Brief explanation of the drawing]

1 is a generalized block diagram of a computer system embodying the invention; FIG. 2 is a detailed block diagram of a generally preferred embodiment of the invention; FIG. 3 is a diagram showing various video timing signals. and associated video timing parameters; FIG. 4 is a diagram illustrating video timing waveforms during one memory cycle in which video circuit video FIFO heavy geo data is transferred from system RAM; FIG. Figure 5 shows the taps used and the bit arrangement order of video data in the shift register in the case of bit/pixel video. FIG. 5C is a diagram showing the bit arrangement order of video data; FIG. , 1 for 8-bit/pixel video and the bit arrangement order of the video data in the shift register. FIG. 10...Computer system, 11...e.Random access memory (RAM), 12...Memory decoding unit (MDU), 13...Φ.Central processing unit (CP)
U), 14...RAM-based video device (RBV)
, 18.19.20---One oscillator, 26...-Video digital/analog converter (VDAC), 21---
-Moni fi-, 4G-...Computer motherboard, 42...RAM bank B143...RAM bank A14411.e.bus buffer, 45-...I/O device, 4F...ROM, 53...Latch,
54...Video FIF0, 57...Bit order arrangement device, 59...Lift register, 60...
Tap selector, 6 rows... Clock generator, 65...
...Video counter device, T1...Register for monitor parameters, 88・●●●multiplexer. Patent Applicant Apple Computer Incorporated

Claims (4)

[Claims] (1) A central processing unit (CPU) that executes a program to supply video data to be displayed on a monitor; and a random access memory (CPU) that stores the video data.
a RAM) configured to receive a signal identifying a video timing condition of the monitor, thereby being configured to be compatible with the video timing condition of the monitor, to provide a video timing signal to the monitor, and to provide a video timing signal to the monitor; a programmable video circuit for transferring video data from the RAM to the monitor for displaying the video data. (2) a central processing unit (CPU) that executes a program for supplying video data to be displayed on a monitor; and a random access memory (CPU) that stores the video data;
a RAM) for displaying the video data on the monitor that provides a signal identifying the type of monitor;
means for transferring said video data from to said monitor; register means for decoding said signal and selecting a set of monitor parameters associated with said type of monitor; a frequency source providing a plurality of frequency references; dot clock generator means responsive to said signal to generate a dot clock signal from said plurality of frequency references that is compatible with said type of monitor; configured to be compatible with the type,
a video timing circuit for generating the video timing signal for the monitor. (3) in a computer generating video signals to be displayed on different types of monitors, each providing a signal identifying the type of monitor;
storage means for storing monitor parameter information associated with each of said types of monitors used for displaying video data so as to select a set of monitor parameters associated with said types of monitors; dot clock generator means coupled to the means for generating a dot clock signal associated with the type of monitor; coupled to the storage means and the dot clock generator means;
a computer comprising a video timing circuit for generating a video timing signal associated with the type of monitor and coupling the video timing signal and the video data to the monitor. (4) A computer that displays video data on the monitor that supplies a signal that identifies the type of monitor, including a random access memory that stores the video data, and a computer that supplies a video timing signal to the monitor and responds to the identification signal. to self-configure the video timing signal to be compatible with the monitor type;
a video circuit that transfers the video data from M to the monitor and displays it on the monitor.