JPH03147153A - Cache memory device - Google Patents

Abstract

PURPOSE:To prevent the performance of a system from being lowered by receiving the next bus request after all cache memories finish bus monitoring operations and the next bus monitoring is made operatable. CONSTITUTION:A bus controller 2 inputs check completion signals 53, which are outputted from respective processors 11-1n so as to show the check operation completion of the bus monitoring, in the state of one signal connected to a wired OR. After monitoring an address bus and as the result of address collation, when the address is coincident, a set/reset circuit 24 is reset and the check completion signal 53 is made inactive. When an operation to make the signal ineffective is finished, the circuit 24 is set and the check completion signal 53 is made active. Thus, a write operation to a main memory is prevented from being executed without limit and it can be suppressed that all data are made ineffective by the overflow of a monitoring processing in the cache memory. Then, the performance of the system is prevented from being lowered.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cache memory device, and particularly to a multiprocessor/processor having a plurality of CPUs each having a cache memory.
The present invention relates to a cache memory device that controls coincidence between cache memory and main memory in a system.

[Conventional technology]

Conventionally, in a multiprocessor system consisting of a plurality of CPUs each having a cache memory, consistency control between the cache memory and main memory has been performed using a function called bus monitoring (or bus watching).

This bus monitoring was performed by each cache memory using a write pulse to capture the write address sent when a processor wrote to the main memory. In other words, at the same time as each cache memory is rewritten to the main memory, it checks whether the rewritten data in the main memory exists among the data stored within itself, and if so,
Invalidate that data.

FIG. 5 shows a block diagram of a conventional example of this device. That is, a processor 11' consisting of a CPU #1 and a cache memory #1 is replaced by a processor 12' to 1n having a similar configuration.
The main memory 3 is connected in parallel to the address bus 51 and the write pulse bus 52 through the address bus 51 and write pulse bus 52. The bus controller 2' receives bus request signals 71-7n sent from the processors 11'-1n, and outputs bus acknowledge signals 81-8n to the processors 11'-1n' in response. .

Now, the bus request signal 7 from - processor 1m'
Suppose that an access request to the main memory 3 is issued through m. In this case, upon accepting this request, the bus controller 2' sends a pass acknowledge signal 8m indicating access permission to the processor 1m. At this time, the bus controller 2 does not issue access permission even if there is a similar request from another processor.

The bus controller 2 issues access permission to the processor 1m' and at the same time sends an access acceptance signal 54 to the main memory 3. Upon receiving the pass acknowledge signal 8m, the processor 1m' outputs the address Am to the address bus 51 and at the same time outputs one write pulse to the write pulse bus 52, when attempting to execute a write access at this time, for example. Naturally, the processor 1m also outputs write data, but this is not shown in the figure because it is not related to the present invention.

Therefore, the address Am and the write pulse output to the address bus 51 and the write pulse bus 52 are sent to the main memory 3, and the address Am of the main memory 3 is accessed by the write pulse, that is, the address Am
Rewrite the data. At the same time as this rewriting, processor 1
All other processors except m input the write pulse and latch the address Am on the address bus 51. The address Am thus latched is referenced to see if it is the address of data stored in the cache memory within each processor.

In each processor, if the result of the reference is the address Am
If there is any data, invalidate it. By doing so, the consistency of data in the main memory and cache memory is maintained. This series of operations in each processor is bus monitoring.

On the other hand, when the main memory 3 completes the operation accessed by the processor 1m', it outputs a memory operation completion signal 55 to the bus controller 2.

This signal 55 returns the state to a state in which it is possible to accept the next bus request from each processor, and when a bus request from a certain processor is accepted, the same operation as described above is repeated.

[Problem to be solved by the invention]

The above-mentioned consistency control in the conventional cache memory is such that if writing to the main memory 3 is allowed without limit, the bus monitoring operations of each cache memory 11' to 10' will not be able to be processed, and all the cache data within itself will be lost. It was supposed to be disabled. Invalidating the stored cache data in this way will cause a significant drop in the hit rate for the next CPU access, and will eventually result in a block containing miss data being fetched from the main memory to the cache due to a cache miss. This caused an increase in system bus occupancy time. Therefore, it had the disadvantage of causing a significant drop in the performance of the system.

An object of the present invention is to eliminate such drawbacks and to perform unlimited writing to the main memory by accepting the next main memory access after checking that the bus monitoring operation of each cache memory is completed. It is an object of the present invention to provide a cache memory device which can normally process bus monitoring operations within a cache memory and prevent system performance from deteriorating.

[Means to solve the problem]

The configuration of the cache memory device of the present invention includes a main memory, a plurality of processors each having read/write access to a common area of the main memory and each having a cache memory, data stored in each of the cache memories, and a plurality of processors each having a cache memory. Equipped with a bus controller that controls consistency with data stored in main memory,
Each of the cache memories includes a circuit that captures a write address to the main memory using an address and a write pulse sent from one of the processors during a write operation to the main memory; A comparison circuit that compares the address of the data stored in the cache memory itself outputs a check completion signal if the address of this comparison circuit does not match, and if the address matches, the cache memory itself outputs a check completion signal. and a check completion signal generation circuit that does not output the check completion signal until the operation of invalidating the corresponding stored data is completed, and the path controller has a check completion signal generation circuit that does not output the check completion signal until the operation of invalidating the corresponding stored data is completed, and the path controller has a check completion signal generation circuit that does not output the check completion signal until the operation of invalidating the corresponding stored data The present invention is characterized in that it includes a reception circuit that does not accept the next memory access request unless all check completion signals are inputted from each of the cache memories.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention, in which only the parts related to the present invention are shown: CPU #1 and cache memory #1.
The processor 11 consisting of
2 to 1n together with address bus 51. light pulse bus 5
2 and are connected in parallel through the check completion signal 53. That is, in this embodiment, unlike the conventional example, the bus controller 2 outputs the check completion signal 53 indicating the completion of the bus monitoring check operation output from each processor 11 to 1n in the state of a single signal connected to the wired OR. The difference is in the input.

A series of bus monitoring operations in this embodiment are similar to those in the conventional example.

In this embodiment, the check completion signal 53 is output when each of the processors 11 to 1n is ready to accept the next bus monitoring operation including the invalidation process. Since the check completion signal 53 from each processor is connected to wired OR, the bus controller 2 is notified of the check completion only when all the connected processors 11 to 1n output the check completion signal 53.

On the other hand, when the main memory 3 completes the operation accessed by the processor 1m, it outputs a memory operation completion signal 55 to the bus controller 2. After the check completion signal 53 and memory operation completion signal 55 both rise, the bus controller 2 returns to a state in which it can accept the next bus request from each processor, and accepts a bus request from a certain processor, as described above. Repeat the action.

FIG. 2 is an internal block diagram of the processor 1m shown in FIG. The processor 1m includes a flip-flop 2o that fetches the address bus 51 with a write pulse on the write pulse bus 52, an address storage circuit 22 that is read accessed from a lower address 61 of the address stored in this flip-flop 20, and this tag address. Memory circuit 22
A matching circuit 21 that checks the match between the read data 64 from and the upper address 62 of the address stored in the flip-flop, and a match signal 63 output from this matching circuit 21.
It is comprised of an invalidation circuit 23 that invalidates the corresponding data by the following, and a set/reset circuit 24 that is reset by a match signal 63 and set by an invalidation end signal 65 from the invalidation circuit 23. That is, after monitoring the address bus, if the result of address verification is -, the set reset circuit 24 is reset and the check completion signal 53 is inactivated, and when the invalidation operation is completed, it is set and the check completion signal 53 is activated. Activate.

FIG. 3 is an internal block diagram of the bus controller 2.

The reception circuit 28 that receives bus request signals 71 to 7n from each processor becomes enabled when the output signal of the AND gate 30 to which the check completion signal 53 and memory operation completion signal 55 are input rises. Reception circuit 28
After accepting requests from each processor, outputs request signals 91 to 9n corresponding to bus requests 71 to 7n, one request is selected by arbiter 29, and bus acknowledge signals 81 to 8n correspond to each processor. It will be returned to you. Naturally, only one pass acknowledge signal is active and the others are inactive.

FIG. 4 is a block diagram inside a processor according to a second embodiment of the present invention. The difference between this embodiment and the first embodiment lies in the conditions under which the check completion signal 53 is generated. A flip-flop 27 is installed to make the check completion signal inactive by a bus monitoring light pulse. That is, if the OR circuit 26 detects that the verification effect of the address fetched by the output of the inverter 25 from the verification circuit 21 does not match, or that the invalidation process is completed by the output of the invalidation circuit 23 if they match. The flip-flop 27 is set and the check completion signal 53 is activated. In this embodiment, since the check completion signal 53 is immediately inactivated when a write pulse is generated, there is an advantage that generation of the next write pulse can be reliably suppressed.

〔Effect of the invention〕

As explained above, in a multi-system cache memory system, the present invention performs bus monitoring operation monitoring (of all cache memories connected to a common bus) so that all cache memories perform bus monitoring operation. By accepting the next node request after the next node monitoring becomes operational, it is possible to prevent the write operation to the main memory from being performed indefinitely, which previously occurred, and to reduce the cache memory. This has the effect of suppressing invalidation of all data due to overflow of monitoring processing, and preventing deterioration of system performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
3 is an internal block diagram of the bus controller in FIG. 1, FIG. 4 is an internal block diagram of another example of the processor in FIG. 1, and FIG. FIG. 1 is a block diagram of an example of a conventional cache memory device. 11-1n...Processor, 2...Bus controller, 3...Main memory, 20.27...Flip-flop, 21...Verification circuit, 22...Address storage circuit, 23... Invalidation circuit, 24...Set reset circuit, 25...Inverter, 26...OR circuit, 28...Reception circuit, 29...Abiter, 3o...
・AND gate, 51... bus address signal, 52.
...Write pulse signal, 53...Check completion signal,
54... Access acceptance signal, 55... Memory operation end signal, 61... Lower address signal, 62... Upper address signal, 63... Match signal, 64... Address signal, 65... - Invalidation end signal, 66... Mismatch signal, 67... Set signal, 71-7n... Bus request signal, 81-8n... Pass acknowledge signal, 90... Enable signal, 91-9n ...Acceptance signal.

Claims (1)

[Claims] A main memory, a plurality of processors each having read/write access to a common area of the main memory and each having a cache memory, and data stored in each of the cache memories and data stored in the main memory. a bus controller for controlling consistency; each cache memory determines a write address to the main memory using an address and a write pulse sent from one of the processors during a write operation to the main memory; a circuit for fetching, a comparison circuit for comparing the fetched address with an address of data stored in the cache memory itself, and outputting a check completion signal if the addresses of the comparison circuit do not match; and a check completion signal generating circuit that does not output the check completion signal until the cache memory itself completes the invalidation operation of the corresponding data stored in the cache memory when the addresses match, and the bus controller is configured to control the processor. A cache memory device comprising: a reception circuit that does not accept a next memory access request unless all check completion signals are inputted from each of the cache memories even after a write operation to the main memory is completed.