JPH0314380B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dither image data restoration circuit that restores dither image data compressed by a pattern predictive coding method.

[Conventional technology]

The dither method is known as a method for pseudo-expressing intermediaries using black and white binary values. For example, Fig. 3a,
b and c indicate the threshold values of the 4×4 Bayer type, halftone type, and spiral type dither matrices, respectively. When multivalued image data is binarized using such a dither matrix, many short white or black run lengths (the length of consecutive pixels of the same color) appear, so data compression using a standard method such as the MH method is recommended. cannot be expected. Therefore, a pattern predictive coding method has been proposed as a compression method for dithered image data.

In the pattern predictive coding method, for example, each block is divided into blocks of 2 x 4 pixels, a pattern with a high frequency of appearance among the black and white patterns in each block is used as a basic pattern, and two adjacent blocks are coded using this basic pattern. When a 4 x 4 Bayer dither matrix is used, the 4 x 4 pixels are divided into an upper row and a lower row, as shown in Figure 4. If you assign a pattern number to each, the pattern number.
Patterns 0 to 8 appear as gradation patterns, and pattern Nos. 9 to 15 are additional patterns, making a total of 32 types of basic patterns. Using these 32 basic patterns, 98% of the entire image area can be expressed.

FIG. 5 is an explanatory diagram of the coding block BL ₀ and reference blocks BL ₁ and BL ₂ of 2×4 pixels, and the prediction order of the coding block BL ₀ is the black and white of the reference blocks BL ₁ and BL ₂ . It is determined by the statistical properties of the image with respect to the pattern, for example,
The black and white pattern with the same pattern number as the black and white patterns of reference blocks BL ₁ and BL ₂ is number 1.

Figure 6 shows the correspondence between prediction ranks and codes; when the prediction rank is No. 1, the shortest code length "1" is assigned, and when the prediction rank is No. 2, a longer code length is assigned. "01" is assigned, and as the prediction rank decreases, longer codes are assigned. Also, for patterns that cannot be expressed using only basic patterns, raw data is inserted into the * mark as a non-basic pattern. Also, the line synchronization signal EOL is
It uses the same codes as the MR method, and the code length of each code is shown on the right side.

FIG. 7 shows a flowchart of data compression processing, and the encoding block input is, for example, the fifth
The encoded block _BL0 of 2×4 pixels in the figure is input. It is determined whether or not this encoded block BL ₀ corresponds to the basic pattern shown in FIG. 4. If it corresponds to the basic pattern, a pattern number is assigned to the encoded block BL ₀ . is predicted using the pattern number of the reference block, the prediction order is converted into a code as shown in Fig. 6, and the pattern number of the encoded block is predicted using the pattern number of the next reference block.
Set it as No. If it is not a basic pattern, approximate it with the basic pattern of the encoded block pattern and give it a pattern number, and then convert the raw data of that encoded block to the non-basic pattern shown in Figure 6.*
The code inserted within the mark is used as the code, and the pattern number of that encoded block is used as the pattern number of the next reference block.

FIG. 8 shows a flowchart for restoring a compressed code, in which received compressed data is input, code decoding is performed, and it is determined whether the data is a basic pattern or not. In the case of a basic pattern, prediction order code decoding is performed, the pattern number of the coding block is inversely predicted from the prediction order, the pattern number is converted to a dither image, and the pattern number of the coding block is next predicted. This is the pattern number of the reference block. If it is not a basic pattern, create a pattern number by approximating the raw data in the code with the basic pattern, output the raw data as it is as a dither image, and use the created pattern number as the next reference block. This is the pattern number.

FIG. 9 shows a block diagram of a conventional dither image data restoration circuit, in which 1 is a prediction rank code decoding circuit;
2 is a pattern No. reproduction circuit, 3 is a dither image reproduction circuit, and 4 is an output buffer memory circuit, which is composed of output buffer sections 4a and 4b (BF1, BF2). Further, numerals 5 to 8 are control circuits for controlling the aforementioned circuits 1 to 4, respectively, numerals 9 to 11 are registers whose latch timings are controlled by the respective control circuits 5 to 8, and numeral 14 is a data transfer control circuit for each block.

The received compressed data is sent to the prediction rank decoding circuit 1.
The compressed data is decoded, and it is determined whether the pattern is a basic pattern or not, and the prediction order is determined. In addition, when an error such as an error in which the corresponding code is not found in the compressed data or an error in which a synchronization signal is not present at a predetermined position is detected, this predicted order code decoding circuit 1 is used until the next one-dimensional line synchronization signal is found.
only those that continue to operate.

The output data of the predicted rank code decoding circuit 1 is latched in the register 9 and applied to the next pattern number reproducing circuit 2. The pattern number reproduction circuit 2 performs inverse prediction based on the prediction order and the pattern number of the reference block, and reproduces the pattern number of the encoded block. This pattern number is applied to the dither image reproduction circuit 3 via the register 10, and dither image data corresponding to the pattern number is reproduced. This dithered image data is applied to the output buffer memory circuit 4 via the register 11.

In the output buffer memory circuit 4, the output buffer sections 4a and 4b each have a capacity of one block line, and the control circuit 8 controls the output buffer sections 4a and 4b so that when dither image data is being written to one, it is read from the other. and in case of error detection,
Control is performed so that the data of the immediately preceding block line is output instead of the error block line data.

As described above, the prediction order code decoding circuit 1, the pattern number reproduction circuit 2, the dither image reproduction circuit 3, and the output buffer memory circuit 4 are controlled by the control circuits 5 to 8, respectively, from the data transfer control circuit 14.
Pipeline processing is performed. When a non-basic pattern is identified, the raw data of the non-basic pattern is transferred to each circuit as it is and is output from the output buffer memory circuit 4.

FIG. 10 is an explanatory diagram of the operation timing during normal operation, and shows the restoration operation of compressed data encoded at 864 blocks/line with a resolution of 16 lines/mm. Also, a, b, and c are registers 9 and 9, respectively.
10 and 11 show the timing for latching data, EOL at a is the line synchronization signal, 1
~864 indicates a block. Further, (d) indicates writing to the output buffer memory circuit 4, and e indicates reading. BF1 indicates writing and reading in the output buffer section 4a, and BF2 indicates writing and reading in the output buffer section 4b.

As mentioned above, the conventional dither image data restoration circuit performs complete pipeline processing, so, for example, the prediction order code decoding circuit 1 processes the line synchronization signal EOL of the n+1 block line and the data of block 1. At this time, the pattern number reproduction circuit 2 processes the data of block 864 of the n block line, and the dither image reproduction circuit 3 processes the data of block 863 of the n block line.

[Problem that the invention seeks to solve]

In the conventional dithered image data restoration circuit, since complete pipeline processing is performed, even if the prediction rank code decoding circuit 1 starts processing the n+1 block line, the output buffer memory circuit 4 contains n data.
This means that writing of block line data has not yet been completed. Therefore, a problem arises in operation when an error occurs. 11 and 12 show the operation timing of the conventional example when an error occurs. In each figure, a is the error clear pulse, b, c, d
indicate the timing for latching data in the registers 9, 10, and 11, respectively, e and f indicate writing and reading to the output buffer memory circuit 4, BF1 indicates the operation of the output buffer section 4a, and BF2 indicates the operation of the output buffer section 4b. shows.

As an error recovery process when an error occurs, the entire circuit is stopped, and then only the prediction order code decoding circuit 1 is operated until the next one-dimensional line synchronization signal EOL (1) is found, and the two-dimensional line synchronization that appears during that time is After counting the signal EOL(2) and then outputting instead the block line data just before the block line in which the error occurred by the counted number, normal operation is resumed.

In FIG. 11, when an error occurs in which the line synchronization signal EOL is not detected after block 864, an error clear pulse is output at time t1 due to error detection, and the code that has been decoded up to that point is By saying that there was an error in the data, the entire data recovery circuit including the output buffer section 4a that is currently being written is cleared immediately, and prediction is continued until the next one-dimensional line synchronization signal EOL(1) is detected. Only the rank code decoding circuit 1 is in operation, and counts the two-dimensional line synchronization signal EOL(2),
By detecting the one-dimensional line synchronization signal EOL(1), from the output buffer section 4b (BF2) by the number of counts,
The block line data written before the error occurrence is repeatedly read and sent out, and when the sending is finished, block 1 after the line synchronization signal EOL(1) is read out and sent out.
Start processing from. Therefore, the time from time t1 to time t2 when normal operation returns is the time for error recovery processing.

Also, in Figure 12, the two-dimensional line synchronization signal
If an error occurs such as the corresponding code not being found at time t3 after EOL(2), the data written to the output buffer section 4a is correct at this point, and the final data of the block line is Writing has not yet been completed. Therefore, at time t4 when writing of the final data of the block line to the output buffer section 4a is completed, an error clear pulse is outputted to clear the entire data recovery circuit. Then, as in the case described above, only the prediction order code decoding circuit 1 continues to operate, and counts the two-dimensional line synchronization signal EOL(2) until the one-dimensional line synchronization signal EOL(1) is detected. Then, the output buffer section 4a (BF1) has the correct data written.
The data is read out repeatedly by the count number and sent out. Therefore, the waiting time is from time t3 to time t4 when the error clear pulse is generated, and the time from time t4 to time t5 when normal operation is returned is the time for error recovery processing.

As mentioned above, in the past, complete pipeline processing has been performed, which has the disadvantage that two types of control must be performed depending on the state at the time of error occurrence.

The present invention aims to improve the above-mentioned conventional drawbacks and simplify control when an error occurs.

[Means for solving problems]

The dithered image data restoration circuit of the present invention includes a prediction order code decoding circuit, a pattern number reproducing circuit, a dithered image reproducing circuit, an output buffer memory circuit, and the processing within the block line is performed by pipeline processing in each of the circuits, and In between, each of the circuits is provided with a control circuit that causes the process to proceed to the next block line after completing the process for the same block line.

[Effect]

Processing within the same block line performs data restoration processing at high speed using pipeline processing, and after each circuit finishes processing the same block line, it starts processing the next block line.
When an error occurs, the entire circuit can be cleared immediately and error recovery processing can be performed without waiting time.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.
The same reference numerals as in FIG. 9 indicate the same parts, 12 is a block unit data transfer control circuit, and 13 is a line unit data transfer control circuit. The block unit data transfer control circuit 12 has almost the same control function as the data transfer control circuit 14 in FIG. 9, and the line unit data transfer control circuit 13 has the following functions:
After the prediction order code decoding circuit 1, pattern number reproduction circuit 2, dither image reproduction circuit 3, and output buffer memory circuit 4 have all finished processing the same block line, they are controlled to proceed to the processing of the next block line. It has a function. These block unit data transfer control circuit 12 and line unit data transfer control circuit 13 can be configured by a microprocessor or the like, and read the status information of each circuit via each control circuit 5 to 8 under program control. It is also possible to control the continuation or stop of processing in each circuit by making a judgment as to whether or not the processing is completed for each block and for each block line.

FIG. 2 is an explanatory diagram of the operation timing of the embodiment of the present invention, where a is an error clear pulse, b, c, d
indicate the timing of latching data in the registers 9, 10, and 11, respectively, and e and f indicate the write and read operations of the output buffer memory circuit 4.

After the processing of the final block 864 of a certain block line is completed and written to the output buffer section 4a (BF1), processing of the block following the line synchronization signal EOL(2) of the next block line is started.
Therefore, at time t6, even if an error such as the corresponding code is not found occurs and an error clear pulse is output as shown in a, and the entire circuit is cleared, the processing of the immediately preceding block line is Since the error has already been completed, there is no need for a waiting time, and the error can be cleared immediately upon occurrence of the error. Then, in this case, the error recovery process returns to normal operation from time t7 after sending out the repeatedly read data from the output buffer section 4a. Therefore, the period from time t6 to time t7 is the time for error recovery processing.

Also, if an error such as a line synchronization signal not being found occurs, immediately clear the entire circuit with an error clear pulse, clear the contents of the output buffer part in the middle of writing on one side of the output buffer memory circuit 4, and write the contents immediately before that. Since the restored data of the block line has been written to the other output buffer section, error recovery processing is performed by repeatedly reading this data.

Therefore, regardless of the state at the time of error occurrence, error recovery can be performed using the same control.

〔Effect of the invention〕

As described above, the present invention provides a dithered image data restoration circuit using a pattern predictive encoding method, including a prediction order code decoding circuit 1, a pattern number reproducing circuit 2, a dithered image reproducing circuit 3, an output buffer memory circuit 4, A line-by-line data transfer control circuit 13 performs pipeline processing in each of the circuits for processing within a block line, and moves to the next block line processing after all of the circuits finish processing the same block line between block lines. Since there is no period during pipeline processing where data of different block lines are being processed, it is possible to immediately clear the error when it occurs and move on to error recovery processing. This has the advantage that error recovery processing can be controlled more easily than in the conventional example.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation timing when an error occurs in the embodiment of the present invention, and FIGS. 3 a to 3 c are explanatory diagrams of a 4×4 dither matrix. Fig. 4 is an explanatory diagram of the basic pattern of the pattern predictive encoding method, Fig. 5 is an explanatory diagram of the coding block and reference block, Fig. 6 is an explanatory diagram of code assignment of the pattern predictive encoding method, and Fig. 7 is an explanatory diagram of the code assignment of the pattern predictive encoding method. Flowchart of data compression processing; FIG. 8 is a flowchart of data restoration processing; FIG. 9 is a block diagram of a conventional data restoration circuit; FIG. and FIG. 12 are explanatory diagrams of operation timing when an error occurs in the conventional example. 1 is a prediction ranking code decoding circuit, 2 is a pattern number reproducing circuit, 3 is a dither image reproducing circuit, 4 is an output buffer memory circuit, 4a and 4b are output buffer units (BF1, BF2), 5 to 8 are control circuits, 9 11 are registers, 12 is a block unit data transfer control circuit, and 13 is a line unit data transfer control circuit.

Claims (1)

[Claims] 1. In a dithered image data restoration circuit using a pattern predictive encoding method, processing in the prediction order code decoding circuit, pattern number reproducing circuit, dithered image reproducing circuit, output buffer memory circuit, and block line is performed in a pipeline by each of the circuits described above. 1. A dither image data restoration circuit comprising: a control circuit which performs processing between block lines and causes the circuits to proceed to processing of the next block line after all of the circuits have finished processing the same block line.