JPH0314378A - Signal processor for digital signal - Google Patents

Abstract

PURPOSE:To suppress the display of a screen of which part is blackened to a monitor screen even when a DAT is controlled to a stop mode on the way of video signal reproducing by mixing an audio signal and a video signal such as a static picture in accordance with the voice format of the DAT at the time of simultaneously recording reproducing both signals. CONSTITUTION:Bit inverting means for inverting an optional bit of a video signal are included in the recording and reproducing systems of digital signals. Namely, the reproduced output data inputted to a terminal 32 are all '0', but its MSB is turned to '1' by inversion processing. When all '0's are applied as a stop code part E.ID, the stop code part E.ID can not be detected during the stopped period, so that a signal processor 10 does not judge that the data are the reproduced final data of a digital video signal DSv. Thereby, change- over switches 66, 68 hold the immediately preceding state of the stop mode. Since the picture displayed immediately before the stop is continuously displayed on the monitor screen an always normal picture is displayed on the monitor screen.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a signal processing device for digital signals suitable for use as an adapter for a digital audio tape recorder. - This prevents the monitor screen from being distorted even when the tape recorder is put into stop mode.

[Prior Art] Current digital audio tape recorders (hereinafter referred to as DAT) are capable of recording and reproducing only audio signals.

However, it would be very convenient if not only audio signals but also other signals, such as video signals for still images, could be recorded and played back simultaneously.

Here, in order to record and playback video signals, it is conceivable to record each signal one channel at a time, for example, by recording audio signals on several TF tracks and recording video signals on @ several tracks. .

Alternatively, it may be possible to record in a format other than the current audio format.

[Problems to be Solved by the Invention] However, if an audio signal is recorded on one channel and a video signal is recorded on the other channel in the DAT audio format, unless a playback device that can also play back the video signal is used. , the video signal is also lost at the same time.

In a DAT having only an audio signal reproducing device, when a video signal is reproduced, excessive noise is generated in the DAT, making it unusable.

If the audio ε number is recorded in a format other than the FM line audio format, it will not be compatible with the current DAT, and therefore it will not be possible to play back even the audio {= issue with a general DAT.

In order to solve these problems, it is necessary to be able to record and reproduce video signals without adversely affecting audio signals while maintaining compatibility with current models.

In addition, if a signal processing device that meets this purpose is realized, there will be times when the DAT will be controlled to a stop mode while monitoring a reproduced video signal. In that case, since the output data of the reproduced video ε will be zero, there is a risk that part of the monitor screen will appear black. It is necessary to devise ways to avoid such unsightly screens as much as possible.

Therefore, the present invention takes these points into consideration, and particularly proposes a signal processing device that prevents the monitor screen from becoming unsightly under any circumstances.

[Means for Solving the Problems] In order to solve the above-mentioned problems, in the present invention, the upper N bits (N is an integer) are used as an audio signal, the lower M bits (M is an integer) are used as a video signal, and this In the digital signal No. 8 processing device which adds or separates the video signal to the audio signal and processes the signal, each of the recording system and the reproduction system of the digital signal includes an arbitrary bit of the video signal. It is characterized in that a bit inverting means is provided for the data.

[Function] As shown in FIG. 1, in the signal processing circuits 82 and 90 provided in the recording system and reproduction system of the digital signal DS,
In addition to data parallel/serial conversion and inverse conversion processing, bit inversion processing is performed on arbitrary bits of the video signal, in this example the most significant bit.

Since the time during which the digital video signal DSv is not inserted is constant, the ending point can be determined by counting the playback time from the insertion start point. DSv
The identification code (stack code section E-ID) inserted into the rear end of the machine is detected, and only when this is detected is the end point determined.

Even if the DAT playback mode stops during playback of the digital video signal DSv, the counter installed in the device does not stop, so when a predetermined period of time elapses after the stop, it is determined that the digital video signal DSv has ended. do.

On the other hand, the reproduced output data input to the terminal 32 is all "0" as shown in FIG. 8, but the MSB becomes "1" by the above-mentioned inversion process.

If all "0"s are assigned as the stop code section E-ID, the stop code section E-ID cannot be detected while the motor is stopped. Therefore, the signal processing device 10 does not determine that the final data of the digital video signal DSv has been reproduced. As a result, the changeover switches 66 and 68 maintain the state immediately before the stop mode.

In other words, the monitor screen continues to display the screen immediately before the stoppage. As a result, a normal screen is always displayed on the monitor screen.

[Embodiment] Next, an example of a signal processing device for digital signals according to the present invention will be described in detail with reference to FIG. 1 and subsequent figures.

Figure 2 shows the format (bit structure) of the digital signal DS, which is a mixture of the audio signal Sa and the video signal Sv.
An example is shown below.

In this invention, in consideration of both compatibility with conventional models and the playback quality of audio signals, the D
Although the number of bits of the AT original digital signal DS is used, this is the same as A. The signal is divided into two as shown in B, and the digital audio signal DSa is applied to the upper pit side, and the digital video signal DSv is applied to the lower bit side.

According to the audio format, the total number of pits is T (T is an integer), and this is selected as T = 16, the number of bits of the digital audio signal DSa is N (N is an integer), and the remaining number of pits is When M (=T-N) is the digital video signal DSv, better results can be obtained by selecting N to 1/2T. Among these, a practical value is about N=8 to 10 (Fig. 2A). As a result, the digital video signal DSV has a 6- to 8-bit configuration (FIG. 2B). In this example, N=10 and M=6.

Then, if the digital audio signal DSa and the digital video signal DSv are mixed so that the digital audio signal DSa is on the upper bit side, the upper 10 bits become the area of the digital audio signal DSa,
The lower 6 bits are the area of the digital video signal DSv (FIG. 2C).

When mixing the audio signal Sa with the video signal SV after applying noise countermeasures such as noise reduction, the relationship between the audio signal Sa and the video signal Sv is not limited to the above-mentioned relational expression; It is also possible to further reduce the number of bits of the signal Sa.

The digital signal DS having such a bit configuration is supplied to a rotating magnetic head (not shown) provided on the DAT, where it is recorded and reproduced.

48kHz as audio sampling clock fs
On the other hand, if the video sampling clock is 3fsc (fsc is 3.58MHz), the frequency difference between the two is about 112 times, so one field of video signal takes about 2 seconds to record. Ru. Also,
The audio signal corresponding to the image content of that video signal (
Since narrations and BGM are usually longer than 2 seconds, the audio signal for one image can usually be recorded for 2 seconds or more. As a result, if the audio signal is used as a reference, a plurality of images can be inserted before the audio signal ends.

Considering the later search processing and the like, it is preferable to add the video signal to the audio signal with some kind of identification code added to the video signal (image data). Signal formats are constructed from this perspective.

FIG. 3 shows an example.

Identification code IDs are added before and after the video signal (image data) inserted into audio number 3 (audio data). As shown in the figure, the Seibetsu code D is composed of a start code section S-ID that is added immediately before the video signal and a stop code section E-ID that is added immediately after the video signal. .

Examples of how the start code section S/ID can be used include (1) the identification code of the video signal data, that is, the image data itself, (2) the format of the video signal, that is, whether it is a composite video, or Y Identification code for {ε and C{' video or R, G, B component video, (3) quantization bit number of image data, (4) cue code for image data (LS/10), etc. can be mentioned. However, this is just one example.

To realize such a usage example, start code part S
- It may be possible to configure the ID as follows.

Figure 4 is an example. First, as shown in the figure, a 6-bit code in which only the least significant bit is "1" is used as a start code. Similarly, a code consisting of all "O's" is used as a stop code.

Treating 6 bits as 1 block B, (4800
+1) A start code section S-ID is constructed using blocks (approximately 50 isec), of which 6o○ blocks are used as main blocks, and the same code data is inserted into each main block. This is so that the start code section S-ID can be searched no matter where in the start code section it is played back.

The main block is divided into 20 sub-blocks of 30 blocks, of which the first 12 sub-blocks F
O to Fil are used as framing codes. Then, when the codes of the blocks that make up each sub-block are all start codes, "O" is selected for the first time.
If all sub-blocks FO to Fil are "O", this is determined as a framing code.

Furthermore, the remaining eight subblocks DO to D7 are used as mode codes.

An example of the mode code is shown in FIG. The content of the mode code is an example.

As shown in FIG. 4, the stop code section E/ID is composed of 8 blocks (approximately 93 μsec) in this example.

Then, a certain blank period is placed in the latter half of this stop code part E-ID, and this start code part S
- The period from the beginning of the ID to the end of the blank period (approximately 2 seconds) is defined as one unit area of image data. The time of this unit area also corresponds to 120 times the vertical period.

The phase of the subcarrier fsc goes around in four fields, so if the unit area is set to approximately 120 times the subcarrier fsc, the phase of the still image video signal Sv recorded before and after will always be O phase, and the subcarrier f
sc discontinuity can be avoided.

Now, FIG. 1 shows how the digital signal DS is processed so as to adopt such a signal form, and then recorded on the DAT and reproduced from the digital signal DS, which is separated into the original audio signal Sa and video signal Sv. A8 for processing
An example of the main parts of the signal processing device is shown below.

The signal processing system for the audio signal Sa will be explained first.

The audio signal Sa supplied to the audio input terminal 12 is supplied to the low-pass filter 16 via the amplifier 14 to be band-limited, and then supplied to the A/D converter 18 and converted into a 10-bit digital audio signal DSa. Zareru. The audio sampling clock used at that time is fs (48 kHz).

The digital audio signal DSa is supplied to a mixing means (adder) 20 constituting the mixing/separating means 86 and mixed with a digital video signal DSv, which will be described later. The mixed digital signal DS (FIG. 2C) is supplied to the digital out processing circuit 22 and converted into a digital signal conforming to the audio format.

As is well known, the digital out processing circuit 22 is provided with clock generation means for generating a pit clock BCK.

The formatted digital signal DS is finally supplied to the rotating magnetic head via the terminal 24 and is recorded.

The digital signal DS reproduced by the rotating magnetic head is supplied to a digital-in processing circuit 34 via a reproduction terminal 32, and subjected to digital-in processing.

For example, a PLL circuit (not shown) is driven to generate a master clock synchronized with the reproduced pit clock BCK.

A separation signal for separating the digital audio signal DSa and the digital video signal DSv is generated based on this master clock, and the digital audio signal DSa and the digital video signal DSv are separated from the separation means 36 at the next stage. is output (Fig. 2 A, B).

Separated 10-bit digital audio signal DS
a is converted into an analog signal by the D/A converter 38, limited to a predetermined band by the low-pass filter 40, and then outputted to the audio out terminal 44 via the amplifier 42.

The signal processing system for the video signal Sv has the following configuration.

The still image video signal Sv supplied to the video in terminal 50 is supplied to the A/D converter 54 via the amplifier 52, and in this example, a 6-bit digital video signal DSv is supplied to the A/D converter 54.
It is converted to . The sampling clock used at that time has a frequency that is an integral multiple of the subcarrier fsc,
In this example, it is 3fSC.

The digital video signal DSv is supplied to the memory means 60 via a changeover switch 56 for switching between an input signal and a reproduction signal and a changeover switch 58 for after-recording.

The memory means 60 serves as a time axis conversion means for the digital video signal DSV. It is possible.

In other words, in order to combine the digital video signal DSv with the digital audio signal DSa, it is used for time axis expansion when reading out the digital video 4g DSv in synchronization with the pit clock BCK, and for the time axis of the digital video signal DSv that has been completely reproduced. Used for axial compression.

The memory means 60 has a pair of memories 62, 64, and a memory control circuit 70, 64 provided in association therewith.
72, control is performed such that l fields (or one frame) are stored in the corresponding memories 62 and 64.

When only one image is inserted one-shot, only one field of video signal is stored in one of the memories. If the same screen is to be inserted continuously, the stored video signal may be read out repeatedly. When inserting different screens successively, video signals are captured at predetermined time intervals and are stored alternately. memory 62
．． Since it takes about 2 seconds to read data from 64, the predetermined time is any time longer than 2 seconds.

Here, writing to the memories 62 and 64 is performed using a 3fSC clock. The readout is performed with a 2fs clock.

This is to synchronize the time axis of the digital video signal DSv with the time axis of the digital audio signal ε DSa while maintaining synchronization therewith. As shown in Figure 6,
Since both the digital audio signal DSaLtL and R channels are recorded sequentially, a 2fs clock instead of fs is used during reading.

Reference numeral 100 denotes a control means for a memory, etc., to which the subcarrier fsc extracted by the subcarrier extraction circuit 110 is first supplied. The control means 100 supplies control signals to the respective memory control circuits 70 and 72 based on this subcarrier fsc.

Reference numeral 124 denotes a changeover switch that is controlled in relation to the recording mode and playback mode in the signal processing device 10, and the mode is determined based on the switching state.

The control means 100 is supplied with a pit clock BCK from the digital out processing circuit 22 and the digital in processing circuit R34. Therefore, the read clock RCK (=2 fs
) is generated by the memory control circuit 70 .
72, a predetermined control signal is supplied.

As a result, the digital audio signal DSa and the digital video signal DSv are input to the mixing means 20 in complete synchronization with this bit clock BCK.

Further, in the digital out processing circuit 22, the detailed explanation is omitted, but based on the pit clock BCK,
A bit switching signal BS of 0 bit and 6 bit is created,
This bit switching signal BS is supplied to the mixing means 20,
A 10-bit digital audio signal DSa and a 6-bit digital video signal DSV are mixed as shown in FIG. 2C.

Reference numeral 112 is a vertical synchronization signal separation circuit, and a vertical synchronization signal extracted and separated from the digital video signal DSv is supplied to the control circuit 1100. This allows the memory 62
．． The digital video signal DSv for one field is always stored in the memory 64 based on the vertical period.

A pair of output changeover switches 66 and 68 that are switched in conjunction with each other are provided downstream of the memories 62 and 64. The output changeover switch 68 is used during signal recording, and the other output changeover switch 66 is used during signal reproduction.

The digital video signals DSV alternately read out from the memories 62 and 64 by the output changeover switch 68 are supplied to a sync bit shift encoder 76 to perform sync pit shift processing.

Originally, a video signal is A/D converted into 6 bits, so its sync bits are all "O" digital data. However, the above-mentioned identification code ID
Considering this, as shown in FIG. 7, since the identification code ID is assigned to the pit that does not affect the image, processing is performed to shift the bits of only the sink pit, and the identification code ID is assigned to the pit that does not affect the image. and the sync bit can be distinguished from each other.

Therefore, during recording, the sync bit is shifted by one bit, and then the adder 78 adds the identification code ID. 80 is this identification code ID
It is a generator of

Digital video signal DS with identification code ID added
Parallel/serial conversion processing is completed for v in the processing circuit 82, and pit inversion processing is performed on any bit of the digital video signal DSv, in this example, the most significant bit MSB. This process will be described later.

Digital video signal DSv that has undergone predetermined signal processing
is converted by the format conversion circuit 84 into a format conforming to the DAT signal format, and then mixed with the digital audio signal DSa as shown in FIG. 2C and sent to the DAT side.

When the digital signal DS is reproduced, the separating means 36 separates it into a digital audio signal DSa and a digital video signal DSv. The separated digital video signal ε DSv is converted to the original format by a format inversion circuit 88, which is subjected to serial/parallel conversion processing by a signal processing circuit 90, and the most significant bit of the digital video signal DSv is re-inverted. Processing is performed.

Thereafter, in the sync bit shift decoder 92, only the sync bits are shifted in the opposite direction to that during recording, and returned to the original sync bits (see FIG. 7).

After that, the memory 62
．． 64, and the reproduced digital video signal DSv is synchronized with the pit clock BCK.
K (= 2 fs) and the read clock RCK (= 3
fsc).

The digital video signal DSv output from the output changeover switch 66 passes through a changeover switch 102 for human output monitor, is converted into an analog signal by a D/A converter 104, and is outputted as video out to an output terminal 108 via an amplifier 106. . There is a monitor means (not shown) on the video out side.

An identification code (D) detection means 94 is provided on the output stage side of the signal processing circuit 90, and the detected identification code ID is supplied to the control circuit 100. The memory control circuits 70 and 72 are controlled by this identification code ID, and signal processing is changed based on mode information.

Now, when the digital video coded DSV to which the identification code ID has been added is reproduced and stored in the memory means 60, only the image data is stored. At this time, the final image data is obtained when a predetermined period of time has elapsed from the first data of the image data, but in order to more accurately detect this final image data, in addition to time management, the stop code section E-ID is also detected. However, it is preferable to judge it as the final image data when the two match. Then, when the storage of this final image data is completed, writing to the memory 62, 64,
When the read mode is reversed, the output selector switch 6
6.68 also switches.

On the other hand, when the playback mode of the DAT is stopped during playback of the digital video signal DSv, the playback output data input to the terminal 32 is all "O" as shown in FIG.
”. Since time management (count-up processing) for image data is performed on the signal processing device 10 side, D
Even if the AT mode enters the stop mode, the count-up process will not stop in conjunction with this.

Therefore, since the memory means 6o is still in the write mode, all "O" data is stored in the corresponding memory, for example 64, as original image data.

Then, when a predetermined period of time has elapsed from the stop mode, the playback time for the final image data has arrived, and since the playback data at that time is always all "O", this may be mistakenly judged as a stop code. Put it away. In that case,
The signal processing device 10 side assumes that the final image data has arrived and instructs the memory means 60 to write and read modes and to switch the changeover switches 66 and 68, so the memory 64 is controlled to the read mode. Ru.

Then, after DAT goes into stop mode, memory 6
Since the data ``O'' written in 4 is not read out and is monitored as an image, the data ``O'' portion appears black, resulting in an unsightly image being monitored.

In order to avoid this, arbitrary bits of the image data, in this example the most significant bit, are inverted and recorded, and then re-inverted during playback. Then, as shown in FIG. 8, even if the reproduction output at the time of mid-stop is all "O", the most significant bit becomes "1" when the re-inversion process is performed.

As a result, on the signal processing device 10 side, (1) there is no misjudgment that the final image data has arrived;

(2) Therefore, the memory means 60 is not controlled to switch.

Therefore, according to (2), the previous screen is always monitored in this case, and the above-mentioned drawback is eliminated.

Note that even if the DAT is in the stop mode, the re-inverted data (pseudo-reproduction data) is written in the memory means 60. Therefore, when the DAT returns to the playback mode, this written pseudo playback data is read out, making the monitor screen unsightly.

However, when the playback mode is entered, the count value is different from the specified value (the count value corresponding to the normal playback time), so even when the playback mode is entered, the writing and reading states of the memory means 60 are not switched. Then, when the next start code section S/ID is detected, the counter is cleared and a new digital video signal DSv is reproduced and stored in the memory, so that the pseudo reproduction data disappears without being read out. Therefore, the monitor screen is not disturbed by the pseudo reproduction data.

The operation of dubbing will be explained next.

Before that, this signal processing device 10 includes at least two function switches 120. as shown in FIG.
122 is provided. One is a mode switch and the other is a shirt switch.

The mode switch 120 is for selecting whether the screen to be inserted is single or continuous, and the shutter switch 122 is for selecting the screen to be inserted when the screen to be inserted is a single shot. .

When dubbing an audio signal, the insertion screen remains as it is, so put the DAT in a playback state, monitor the screen, and switch to dubbing mode when the desired screen for dubbing appears.

Writing and reading from the memories 62 and 64 are repeated alternately, but when performing post-recording of audio signals, the switching state is fixed.

For example, if the dubbing mode is selected while image data in the memory 62 is being monitored, the image data in the memory 62 is always monitored, whereas the image data in the memory 64 is
It is in a state where it can be recorded on AT.

The image data in memories 62 and 64 do not match in most cases. On the other hand, since the operator performs dubbing operations while looking at the monitor screen, the monitor screen during dubbing and the screen actually recorded by dubbing end up being different.

In order to eliminate this problem, it is sufficient to match the image being monitored with the image to be recorded when in the post-recording mode.

Therefore, in terms of hardware, the changeover switch 58 for dubbing
is provided.

The dubbing mode will be explained with reference to FIG.

It is assumed that the changeover switches 66 and 68 are switched to the state shown in FIG. 1 (FIG. 9F).

The write enable signal W is used so that the identification code ID added to the digital video signal DSv is not stored in memory.
T is output (A and C in the same figure).

When the cue code LS-ID is detected among the identification codes ID, an address clear signal is output (B in the same figure).
. When the shutter switch 122 is pressed while the memory 64 is in the writing state (D in the same figure), the control circuit 100 determines that it is the post-recording mode and fixes the operation mode of the memory means 60 to the previous operation mode.

Then, the dubbing switch 58 is switched to the terminal C side in FIG. At the same time, the frequency of the write clock RCK for the memory 64 is changed from 2fs to 3fsc (
Figure E). Then, the image data in the memory 62 is supplied to the memory 64 via the dubbing switch 58, and is rewritten at high speed.

Now, the image data in the memories 62 and 64 match, and the monitor screen and the image data to be recorded match.

When writing is completed, the write enable signal WT for the memory 64 is inverted, and thereafter the Vt of the image data is
I can't get into it. The dubbing switch 58 also automatically returns to its original state and switches to the terminal d side (G in the same figure). The dubbing mode can be canceled by pressing the shutter switch 122 again during playback or by switching the mode switch 120 to the continuous side.

With the above configuration, the audio signal Sa and the video 13
No. Sv can be adapted and mixed with the current audio format. In this case, although the number of quantizations of the audio signal Sa is reduced from the current 16-bit configuration to a 10-bit configuration, there is little deterioration in sound quality due to this decrease in the number of quantizations. Furthermore, since the video is a still image, 6-bit quantization is sufficient.

When the digital signal DS, which is a mixture of the audio signal Sa and the video signal Sv, is to be reproduced using the current DAT, that is, as shown in FIG. When DSv is reproduced as a digital audio signal DSa, there is almost no effect on the audio signal Sa.

In that case, for the audio signal Sa, the video signal Sv
is nothing but a noise component. However, as is clear from FIG. 2C, since the digital video signal DSv is inserted into the lower bit side of the digital audio signal DSa, the audio signal Sa can have a dynamic range of about 6NdB.

Therefore, as mentioned above, if the quantization number N is selected to be about 10 bits, compact cassette, Dolby B (
Trademark) The dynamic range is comparable to recording and playback. For this reason, even if the video signal Sv is played back at the same time, there is almost no effect on the audio signal Sa, and there is little deterioration in quality.

If the bit combination position is reversed so that the least significant bit data ■O of the digital video signal DSv comes to the least significant bit data AO side of the digital audio signal DSa as shown in FIG. The effect of this can be practically ignored.

As for the post-recording process, although this is an example of post-recording an audio signal, it can also be configured to post-record a video signal, or it can be configured so that either one of these can be selected.

In the above, T=16. N=10. Although the explanation has been made assuming that M=6, the values of N and M are not limited to this as described above.

[Effects of the Invention] As explained above, according to the present invention, when recording and reproducing video signals such as still images in addition to audio signals at the same time, the two are mixed in accordance with the DAT audio format. It is something.

Therefore, compatibility with the current model (DAT) can be achieved. Of course, efforts have been made to minimize deterioration in the sound quality of the reproduced audio signal.

Furthermore, in the present invention, the DAT is
Even if the computer is controlled to stop mode, the monitor screen does not display a partially black screen.

This has the feature of effectively preventing unsightly images from being displayed.

Therefore, the signal processing device according to the present invention is extremely suitable for use as an accessory device such as a DAT for events.

[Brief explanation of the drawing]

FIG. 1 is a system diagram showing an example of the digital signal processing device No. 3 according to the present invention, FIG. 2 is a configuration diagram showing an example of the audio format of the digital signal, and FIGS. 3 to 7 are identification diagrams, respectively. FIG. 8 is an explanatory diagram of a code, FIG. 8 is an explanatory diagram of bit inversion processing of a digital video signal, FIG. 9 is a waveform diagram of post-recording processing, and FIG. 10 is a system diagram showing an example of a current DAT. 1 0 ◆ 20 ・ 36 ・ 58 ・ 60 ・ 76 ・ 80 ◆ 82, 90 ・ 92 ◆ 94 ・ Sa ・ DSa ・ Sv ・ DSv ・Signal processing device・Mixing means・Separation means・Dub recording switch・Video signal memory means・Sync bit shift encoder ・Identification code generator ・Signal processing circuit ・Sync bit shift decoder ・Identification code detection circuit ・Audio signal ・Digital audio signal ・Video signal ・Digital video signal

Claims (1)

[Claims] (1) A digital device in which the upper N bits (N is an integer) are used as an audio signal, the lower M bits (M is an integer) are used as a video signal, and this video signal is added to the audio signal or separated from the audio signal for signal processing. A signal processing device for a signal, wherein each of the recording system and the reproducing system for the digital signal is provided with a bit inversion means for an arbitrary bit of the video signal.