JPH03142373A - Peak hold circuit - Google Patents

Abstract

PURPOSE:To enable an efficient peak hold by providing a 2nd comparator generating and an output signal when a lower pulse of input signal voltage exceeds an output signal of inverse circuit and an OR circuit generating an output signal from an OR of outputs of the 1st and 2nd comparators. CONSTITUTION:The output signal is generated by the 1st comparator 2 when an upper pulse of the input signal voltage exceeds a peak holding voltage of a capacitor 1. The output signal voltage by which the peak holding voltage of capacitor 1 is inverted taking a center value of input signal voltage as the reference, is generated by the inverse circuit 6, and the output signal is generated by the 2nd comparator 10 when the lower pulse of input signal voltage exceeds an output signal voltage of the circuit 6. Then, the output signal for OR of output signals for both comparators 2, 10 is generated by the OR circuit 11, and the capacitor 1 is charged with a constant current 3 through a connected switch 4 to generate the peak holding voltage by which the input signal is subjected to peak-hold, on the capacitor 1. The peak hold for the input signal can be thereby performed efficiently.

Description

[Detailed Description of the Invention] [Summary] Regarding a circuit that performs peak hold of an input signal, an object of the present invention is to provide a peak hold circuit that can efficiently perform peak hold. a first comparator that generates an output signal when the peak hold voltage exceeds the peak hold voltage; an inverting circuit that generates an output signal voltage that is the peak hold voltage inverted with respect to the center value of the input signal voltage; a second comparator that generates an output signal when the lower pulse exceeds the output signal voltage of the inversion circuit; and an output signal obtained by logically ORing the output signal of the first comparator and the output signal of the second comparator. and a switch that connects a constant current source to a capacitor in accordance with the output signal of the OR circuit, and generates the peak hold voltage in the capacitor.

[Industrial application field]

The present invention relates to a circuit that performs peak hold of an input signal, and more particularly to a peak hold circuit that can efficiently perform peak hold of an input signal consisting of an AMI signal.

To receive the AMI signal, input AM using an appropriate dark value signal.
This is done by identifying the I signal.

However, since the peak value of the input AMI signal changes depending on the system configuration and the like and is not uniform, a dark value signal that changes depending on the input signal level is required.

Therefore, the optimal dark value signal for identifying the AMI signal is usually created from a signal obtained by peak-holding the input AMI signal.

It is desired that such a peak hold circuit can efficiently hold the peak of the input AM signal.

[Prior Art] Figure 4 shows an example of a conventional peak hold circuit, where l is a capacitor for holding the peak value of an input signal, and 2 is a capacitor for comparing the hold voltage of capacitor 1 with the input signal. 3 is a constant current source for charging the comparator l, 4 is a switch for connecting the constant current source 13 to the capacitor 1, and 5 is a constant current for discharging the charge of the capacitor l. It is the source.

FIG. 5 is a diagram explaining the operation of the conventional peak hold circuit shown in FIG. 4, in which (a) shows the input signal Vl, (b) shows the peak hold voltage V p K, ( C
) is the control signal V, for the switch 4.

As shown in FIG. 5(a), the input signal V, is AMI
It consists of signals and is denoted by V, =v, +VR.

Here, V is a reference voltage equal to the center value of the input AMI signal, and ■ is an amplitude value based on voltage ■8.

For the sake of simplicity, it is assumed that the peak hold voltage at the capacitor l is set to the reference voltage ■8 as an initial value before receiving the input signal V1 consisting of the AMI signal.

The comparator 2 compares the input signal v1 with the hold voltage at the capacitor l.
Only when the positive side pulse (upper pulse) of 1 is input,
The control signal V output from the comparator 2 to the switch 4 becomes low level.

The switch 4 is turned on when the control signal V becomes low level, and connects the constant current source 3 to the capacitor 1, thereby charging the capacitor 1.

In this way, the capacitor 1 is charged each time the upper pulse of the input signal V1 arrives, so that the peak hold voltage V□ is the initial value vll before receiving the input signal V1.
, gradually increases as time t passes, and finally reaches a constant voltage equal to the peak value of the input signal V,
Peak hold is completed. From the peak hold voltage at this time, a dark value signal for identifying the input signal V1 consisting of the AMI signal is created.

In FIG. 4, a constant current source 5 is provided for discharging the capacitor l with a constant current, but since it is not essential to the present invention, detailed explanation will be omitted.

[Problem to be solved by the invention]

In the conventional peak hold circuit illustrated in FIGS. 4 and 5, the peak hold of the AMI signal reception input signal is performed only when receiving the upper pulse, and
No peak hold operation is performed on the negative side pulse (lower pulse) of the I signal.

Therefore, the conventional peak hold circuit has a problem in that it cannot efficiently handle the peak hold.

The present invention aims to solve the problems of the prior art as described above, by making it possible to perform a peak hold operation even for the lower pulse of an input AMI signal, thereby efficiently performing a peak hold. The purpose of this invention is to provide a peak hold circuit that can perform

[Means to solve the problem]

As shown in FIG. 1, the present invention includes a first comparator 2, an inverting circuit 6, a second comparator 10, an OR circuit 11, and a switch 4. A peak hold voltage is generated at l.

Here, the first comparator 2 generates an output signal when the upper pulse of the input signal voltage exceeds the peak hold voltage, and the inverting circuit 6 generates the peak hold voltage with reference to the center value of the input signal voltage. It generates an inverted output signal voltage.

The second comparator 10 generates an output signal when the lower pulse of the input signal voltage exceeds the output signal voltage of the inverting circuit 6, and the OR circuit 11 connects the first comparator 2 and the second An output signal is generated by performing a logical sum with the output signal of the comparator 10.

The switch 4 generates a peak hold voltage in the capacitor 1 by connecting the constant current source 3 to the capacitor 1 in accordance with the output signal of the OR circuit 11.

[Effect]

The first comparator 2 generates an output signal when the positive pulse (upper pulse) of the input signal voltage, such as the AMI signal, exceeds the peak hold voltage at the capacitor l.

Further, the inverting circuit 6 generates an output signal voltage obtained by inverting the peak hold voltage at the capacitor 1 with respect to the center value of the input signal voltage, and the second comparator 10
When the negative side pulse (lower pulse) of the input signal voltage exceeds the output signal voltage of this inversion circuit 6, an output signal is generated.

Then, by the OR circuit 11, the first comparator 2
The output signal of the second comparator 10 is logically summed with the output signal of the second comparator 10.

This output signal controls the switch 4, connects the constant current source 3 to the capacitor 1, and charges the capacitor l, thereby generating a peak hold voltage in which the input signal is peak held in the capacitor 1.

In this way, the peak hold circuit of the present invention charges the capacitor with both the upper and lower pulses of the input signal and generates the peak hold voltage, so it can efficiently hold the peak of the input signal. be able to.

〔Example〕

FIG. 2 is a diagram showing an embodiment of the present invention, in which the same parts as in FIG. and a reference voltage VR. Further, IO is a comparator, and 11 is an OR circuit.

FIG. 3 is a diagram explaining the operation of the peak hold circuit of the present invention, in which (a) shows the input signal v consisting of the AMI signal.
1 and (b) respectively indicate the peak hold voltage VPK% (C) and the control signal V for the switch 4.

For simplicity, as in the case of Fig. 4, input signal VI
It is assumed that the peak hold voltage at capacitor 1 is set to reference voltage VR as an initial value before receiving .

When the input signal v1 consisting of the AMI signal is input to the peak hold circuit shown in FIG.
By comparing the values, the output voltage becomes low level only when the positive pulse (upper pulse) of the input signal V1 is input.

On the other hand, the inverting circuit 6 generates an output voltage obtained by inverting the peak hold voltage at the capacitor l with reference to the voltage VR. The comparator 10 compares the output voltage of the inverting circuit 6 with the input signal V1 to generate the input signal V1.
, only when the negative side pulse (lower pulse) is manually applied,
Its output voltage becomes low level.

36. The logical sum circuit 11 calculates the logical sum of the low level output voltages of the comparator 2 and the comparator 10, and generates a control signal V for the switch 4.

The switch 4 is turned on when the control signal (2) becomes low level, and connects the constant current source 3 to the capacitor 1, thereby charging the capacitor 1.

In this way, the capacitor l is charged for each arrival of the upper and lower pulses of the input signal VI, so that the peak-hold voltage VPK is initially (from J V R to , gradually increases over time, and peak hold is completed when it finally reaches a constant voltage equal to the peak value of the input signal v1.This voltage is the desired peak hold voltage, and
From this, a dark value is created for identifying the input signal V1 consisting of the AMl signal.

In this way, in the peak hold circuit of the present invention, the input A
Since capacitor 1 is charged by both the upper and lower pulses of the MI signal, the time required to complete peak halt can be shortened compared to the conventional circuit shown in FIG. -Hold efficiency can be improved.

It goes without saying that the peak hold circuit of the present invention is not limited to generating a dark value voltage for identifying AMI signals, but can also be used for other purposes.

〔Effect of the invention〕

As explained above, according to the peak hold of the present invention, by simply adding a simple circuit to the conventional circuit, the peak hold operation can be performed for both the upper pulse and the lower pulse of the input AMI signal. This makes it possible to efficiently perform peak hold on the input AMI signal.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic configuration of the present invention, FIG. 2 is a diagram showing an embodiment of the present invention, FIG. 3 is a diagram explaining the operation of the peak hold circuit of the present invention, and FIG. 4 is a diagram showing the operation of the peak hold circuit of the present invention. FIG. 5 is a diagram illustrating the conventional peak hold circuit. FIG. 5 is a diagram illustrating the operation of the conventional peak hold circuit. 1 is a capacitor, 2 is a first comparator, 3 is a constant current source, 4 is a switch, 6 is an inverting circuit, 10 is a second comparator, and 11 is an OR circuit.

Claims (1)

[Claims] A first comparator (2) that generates an output signal when an upper pulse of the input signal voltage exceeds a peak hold voltage; and a first comparator (2) that inverts the peak hold voltage with respect to the center value of the input signal voltage. a second comparator (10) that generates an output signal when the lower pulse of the input signal voltage exceeds the output signal voltage of the inverting circuit (6); an OR circuit (11) that generates an output signal by ORing the output signal of the first comparator (2) and the output signal of the second comparator (10);
a switch (4) for connecting the constant current source (3) to the capacitor (1) according to the output signal of the peak capacitor (11), and generating the peak hold voltage in the capacitor (1).・Hold circuit.