JPH03139863A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To realize the determination or the change of logic at a high gate using rate with a chip occupying rate being suppressed low by adopting programmable logic circuit blocks, holding data for determining logic states in electrically writable built-in nonvolatile memories, and constituting a semiconductor integrated circuit in this way. CONSTITUTION:Input/output circuit blocks IOB are arranged around logic circuit blocks LCBs which are arranged in a matrix pattern. The logic states are determined or changed based on data stored in volatile storage elements. Connecting logic blocks MS are arranged so that the blocks are positioned at the intersection of wiring groups NL, and the interconnecting state of the wiring groups NL is determined. The determination or the change of the interconnecting state is performed with an individually contained volatile storage element. A nonvolatile ROM is constituted of an electrically writable EPROM or an electrically writable/erasable EEPROM and provided with various kinds of peripheral circuits.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a technology for controlling the logic state of a logic circuit block in a semiconductor integrated circuit equipped with a logic circuit block. The present invention relates to techniques that are effective when applied to custom or semi-custom semiconductor integrated circuits.

[Prior art]

Master slicing technology and gate array technology have traditionally been provided as technologies for quickly manufacturing low-volume, high-mix LSIs such as custom or semi-custom semiconductor integrated circuits, but PLD (Prog.
rammable Logic Device) technology and LCA (L.

gic Cell Array) technology is known. For example, the former is described in Japanese Patent Application Laid-Open No. 58-85638, and the latter is described in Nikkei Electronics No. NQ403 published by Nikkei McGraw-Hill (September 1986).
August 8th issue) pages 245 to 265, I.E.E. 1988 Custom Ingrated Circuit Conference, pages 15.3.1 to 1
5.3゜7 pages (IEEE 1988 Custom
Integrated C1rcuits C
onference pp15.3.1-15.3.
7), and USP (United States Patent) 4642
487. According to these techniques, a semiconductor integrated circuit equipped with a general-purpose logic circuit block is manufactured in advance, and a desired logic is configured by programming the logic circuit block later. As a result, even semiconductor integrated circuits that are mass-produced as standard products can be used as custom or semi-custom semiconductor integrated circuits produced in a wide variety of small quantities.

[Problem to be solved by the invention]

However, the inventors have discovered that conventional PLDs and LCAs have the following problems.

(1) In order to construct a large logic using PLO, it is necessary to increase the number of product terms. However, when the number of product terms is increased, the gate usage rate generally decreases, which is particularly noticeable when configuring a plurality of logics that are highly independent of each other. Therefore, it has been revealed that it is not desirable to configure the desired logic only with PLDs from the viewpoint of gate usage efficiency. Furthermore, when a large number of relatively small-scale PLDs are formed in order to improve gate utilization, a peripheral circuit for programming the nonvolatile memory elements that constitute the PLD must be formed for each PLD. On the contrary, the chip area occupied by such peripheral circuits increases significantly.

(2) LCA is PL in terms of gate usage rate
A logic circuit can be configured more efficiently than D.

This is because programmable logic blocks are arranged regularly, and the intersections of wiring placed in the wiring area between blocks are connected by a program, and its structure is similar to a gate array. be. However, programs for LCA logic circuit blocks and wiring intersections are stored in non-volatile EPRO external to LCA.
This is done by transferring program data from a memory such as M or EEPROM to the cells of a built-in volatile static RAM. For this reason, program data must be transferred from the outside each time the power is turned on or data in static RAM is lost, and two semiconductor integrated circuits, LCA and external memory, are always required. This poses a problem in that it becomes inconvenient to handle and operate. Furthermore, there is a problem in that an external bus master must be used for data transfer from the outside, and the exclusive period of the external bus due to such program operations cannot be ignored.

The purpose of the present invention is to perform TAT (Turn Around
It is possible to reduce the time required (time) and to determine or change the logic after LSI manufacturing with a higher gate utilization rate and lower chip occupation rate than with PLD technology, and with a lower chip occupancy rate than with LCA technology. An object of the present invention is to provide a semiconductor integrated circuit device that can be easily handled and implemented in a system.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, it employs a programmable logic circuit block whose logic state is variably set according to the information stored in the volatile memory element, and a built-in non-volatile logic circuit block in which information for determining the logic state of the logic circuit block can be electrically written. A semiconductor integrated circuit is constructed by holding the information in a memory.

Here, in order to increase the flexibility or versatility of the logic that can be set in a programmable logic circuit block to be comparable to a gate array, it is necessary to arrange a plurality of relatively small-scale programmable logic circuit blocks and to It is preferable that the circuit blocks are connected by wiring for connection between blocks, and the connection state between the wirings is determined by some of the programmable logic circuit blocks.

In order to enable the semiconductor integrated circuit mill to load the logic decision information stored in the non-volatile memory into the volatile memory element of the programmable logic circuit block, it is necessary to It is desirable to incorporate access control means.

Furthermore, in order to reduce the number of signal lines for transferring logic determination information to the volatile memory element, the volatile memory element may be configured with a serial-in/parallel-out type shift register. At this time, the access control means performs selection control for the shift register and serial transfer control of information.

Further, when the semiconductor integrated circuit of the present invention is applied to a microcomputer, a central processing unit that performs logic control operations using the programmable logic circuit block is included. Therefore, the programmable logic circuit block is used to implement the peripheral functions of the central processing unit, and since it is programmable, it can also be used as redundancy for the peripheral functions.

[For production]

According to the above-described means, the volatile memory element for determining the logic state of the programmable logic circuit block does not require various peripheral circuits such as are required for programming a non-volatile memory element. This means that even if you increase the efficiency of gate usage by giving a degree of freedom to the internal configuration of a programmable logic circuit block and the arrangement between multiple programmable logic circuit blocks in terms of the number of inputs and outputs and the number of product terms, etc. This works to suppress a significant increase in the chip occupation rate due to The built-in non-volatile memory, which holds the information to be stored in the volatile memory element to determine the logic state of the programmable logic circuit block, eliminates the need to transfer program data from the outside, which was conventionally required every time the power is turned on. This facilitates the handling of semiconductor integrated circuits incorporating programmable logic circuit blocks.

〔Example〕

FIG. 1 shows a semiconductor integrated circuit according to an embodiment of the present invention. This semiconductor integrated circuit is formed on a single semiconductor substrate such as silicon, and is positioned as a programmable logic LSI that shortens TAT and allows logic to be determined after the LSI is manufactured.

The semiconductor integrated circuit of this embodiment includes a large number of logic circuit blocks LC as programmable logic circuit blocks whose logic states are variably set according to information stored in a volatile memory element.
B, a turnout circuit block IOB, and a connection logic block MS. And then there is the programmable logic circuit block LCB.

As a dedicated circuit block for determining the logic state of IOB and MS, electrically writable EPROM and EE
A non-volatile memory ROM such as P ROM, an input/output interface I10 for supplying logic determination information of the programmable logic circuit blocks LCB, IOB, and MS to the non-volatile memory ROM from the outside, and a It includes an access control circuit ACONT that controls writing of the read logic determination information into the volatile storage elements of the programmable logic circuit blocks LCB, IOB, and MS.

The logic circuit blocks LCB are regularly arranged in a matrix, and the logic state thereof is determined or changed according to the information stored in the built-in volatile memory element.

Each logic circuit block LCB includes at least one data input terminal and at least one data output terminal to perform a desired logic operation, as well as various control terminals and power supply terminals. Further, each logic circuit block LCB is provided with various control terminals and data input terminals for transferring program data for determining or changing its logic state. Note that the respective logic circuit blocks LCB may have the same configuration, or may have different logic configurations or numbers of input/output terminals.

The input/output circuit block IOB is arranged around the logic circuit block LCB arranged in a matrix, and the logic state thereof is determined or changed according to the storage information of the volatile storage element included in each input/output circuit block IOB. Like the logic circuit block LCB, each block ○B has data input/output terminals, various control terminals, and power supply terminals for performing a predetermined logic operation, that is, in this case, a predetermined input/output operation, and transfers program data. It is equipped with various control terminals and data input terminals. The respective input/output circuit blocks IOB may have mutually different circuit configurations. Further, the input/output circuit block IOB includes electrode pads connected to external terminals.

NL is a group of wires used for connecting between the logic circuit blocks LCB and between the logic circuit blocks LCB and the input/output circuit block IOB, and the connection logic block MS is located at the intersection of the many wire groups NL. The connection logic blocks MS determine the interconnection state of the wiring group NL. Determination or modification of the connection state by each connection logic block MS is performed in an individually built-in volatile memory element. Each connection logic block MS also has data terminals and power supply terminals.

It is provided with various control terminals and data input terminals for transferring program data.

In FIG. 1, SL is a wiring group similar to the wiring group NL, and the difference between the two is the length of the wiring distance or the number of wirings. It is connected to the connection logic block MS over a long wiring distance.

The programmable logic circuit block LCB.

The volatile memory for determining the logical state of MS and I'OB is not particularly limited, but it constitutes a serial-in/parallel-out type shift register SR, and a selector SE.
Paired with L, respective logic circuit blocks LCB, MS,
Included in I○B.

The input/output interface I10. Non-volatile memory RO
M. The access control circuit ACONT is connected to a program bus PB including an address bus, a data bus, and a control bus.
Commonly connected to US.

The non-volatile memory ROM is an electrically writable EP.
ROM or electrically writable/erasable E E P
It is composed of a ROM and includes various peripheral circuits such as an address decoder, a sense amplifier, and a write or write/erase circuit. Writing to this nonvolatile memory ROM is performed, for example, by an external writing device such as an EPROM writer, a host processor on the system, etc. via the input/output interface I10. According to this embodiment, each shift register SR is assigned a unique address, and the logic determining information to be supplied to each shift register SR is paired with the individual address and stored in the nonvolatile memory ROM. written.

The address control circuit ACONT includes a non-volatile memory ROM in order to determine or change the logic states of the logic circuit block LCB and input/output block E○B, and to determine or change the connection state of the connection logic block MS.
It performs access control such as read access to the non-volatile memory ROM and write access to a predetermined shift register SR with information read from the nonvolatile memory ROM. For example, it decodes address information for selecting a shift register SR, and thereby The obtained selection signal is sent to the selector SE
Output to L. Then, the logic decision information is serially output to the shift register SR. The selection signal is applied to programmable logic circuit blocks LCB, I arranged in a matrix.
It consists of a row selection signal for selecting rows of OB and MS, and a column selection signal for selecting columns, and is located at the intersection of the row selected by the row selection signal and the column selected by the column selection signal. Shift register SR of the logic circuit block is selected.

Next, an example of a programming method for determining the logic state of the programmable logic circuit block will be described.

(1) When programming for the first time after manufacturing a semiconductor integrated circuit [A], to determine the logic states of the logic circuit block LCB and input/output circuit block EOB and the connection state of the connection logic block MS according to the required specifications. 6 [B] Select the first programmable logic circuit block LCB, IOB or MS to be programmed from outside the semiconductor integrated circuit.

The access control circuit ACONT built in the semiconductor integrated circuit can also be used for this selection operation.

[618 Next, by an external control device or via the access control circuit ACONT, information for logic determination is sent to the programmable logic circuit block LC selected by the address.
B, IOB or MS shift register SR. As a result, the programmable logic circuit block LC
B.

The logic state of the IOB or MS is determined.

[D] For all programmable logic circuit blocks LCB, IOB, and MS to be programmed, the above CB
) to [C] are sequentially repeated to determine the logic of the entire semiconductor integrated circuit. (E) Next, it is verified whether there are any problems with the logic state and connection state determined by the above method.

[F] If there is no problem with the logical state or connection state,
The series of logic determination information is written to the nonvolatile memory ROM by an external control device such as a general-purpose EPROM writer. In this case, the data stored in the nonvolatile memory ROM includes at least the logic determination information and this information. It includes addresses of programmable logic circuit blocks LCB, IOB, and MS whose logic states or connection states are determined. Verification is performed for this write operation. If it is found that there is a problem with the programmed logic state or connection state, the LC with the problem will be
B.

The above processing is performed on the IOB or MS to rewrite its program data. Non-volatile memory ROM is EPR
In the case of OM, all program data is rewritten after erasing with ultraviolet light.

The above operations determine the logic of the semiconductor integrated circuit,
It becomes possible to execute a desired operation.

(2) System operation after programming After the program data is stored in the non-volatile memory ROM, there is no need to transfer the program data from the outside, and the program data is sequentially transferred from the non-volatile memory ROM under the control of the access control circuit ACONT. programmable logic circuit block LC at the specified address.
Transfer logic determination information to B, JOB or MS. All programmable logic circuit blocks LCB, IOB to be programmed with this process.

As a result, the logic of the entire semiconductor integrated circuit is determined according to the information stored in the nonvolatile memory ROM, and thereafter the semiconductor integrated circuit can perform system operation according to the logic.

(3) Subsequent modification of program data Reuse the method described in (1) above. At this time, if it is possible to separate the semiconductor integrated circuit from the system, EPRO
M writer can be used. Alternatively, the semiconductor integrated circuit may be replaced with a new reprogrammed semiconductor integrated circuit. If separation is not possible, electrical rewriting can be performed using a host processor on the system.

FIG. 2A shows an example of a logic circuit block LCB.

This logic circuit block LCB includes a logic circuit section LC, a switch circuit SWI including a volatile element for connecting the output side of the logic circuit section LC to a desired wiring included in a wiring group NL, and a logic circuit section LC. The switch circuit SW2 includes a volatile element for connecting the input side of the switch to a desired wiring included in the wiring group NL. In this embodiment, a predetermined output among the outputs of the logic circuit section LC is fed back to the switch circuit SW2. Logic circuit section LC
If switch circuits (not shown) are also included inside the circuit, a desired logic can be constructed using these switch circuits as well. Furthermore, even if the logic circuit section LC does not include such a switch circuit, the switch circuit S
By determining the connection logic between the input side wiring NL and the output side wiring NL using WI and SW2, the logic of the logic circuit section LC can also be determined6.
A similar configuration can be adopted for the input/output circuit block IOB.

The basic logic circuits that make up the logic circuit section LC include a NOT circuit that means inversion or negation, an OR circuit or NOR circuit that is made up of at least two people, an AND circuit or a NAND AND circuit that is made up of at least two people, and an exclusive OR circuit. These include exclusive NOR circuits, as well as various flip-flop circuits, registers, latch circuits, and the like. The logic circuit section LC includes these basic logic circuits, a circuit that combines these basic logic circuits, or a sequential circuit, and also passive elements such as resistors and capacitors, operational amplifiers, etc. can also be included. By combining these basic circuits, it is possible to configure a circuit that can perform not only digital processing but also analog processing. Logic circuit section L
C is not limited to these circuits, but may be any circuit as long as it has at least one input and at least one output.

FIG. 2B shows an example of the switch circuit SW2. Three wires INLI to IN included in wire group NL
A total of five wires, L3 and two wires ILCI and ILC2 connected to the output terminal of the logic circuit LC, are input to the switch circuit SW2, and three wires 0LCI to
0LC3 is connected to the input terminal of the logic circuit section LC. The output side wirings 0LCI to 0LC3 and the input side wirings INLI to INL3. There is a MISFE between ILCI and ILC2 to determine the mutual connection status.
Switches T1 to T15 consisting of T are provided. Each terminal is connected to the source or drain of the MISFET, and by controlling the potential of the gate electrode, it becomes conductive when the MISFET is on, and the MISFET becomes conductive when the MISFET is on.
When the FET is off, it is in a non-conducting state, which determines the interconnection state of the wires.

FIG. 2C shows the switches T1 to T1 consisting of MISFETs.
An example of a circuit for controlling the potential of the gate electrode of T15 is shown. This example corresponds to an example of the shift register SR and selector SEL explained in FIG. Shift register SR consists of 15 static latches 5LATI~
It has a serial-in/parallel-out format with 5 LAT15s connected in series. Here those static latches 5L
ATL to S LAT 15 are examples of volatile memory elements. In this example, the logic determination information is 15 bits, but in reality, a larger amount of data is required depending on the logic state of the LCB. In such a case, if such information were transferred in parallel, the number of wires for transfer would be enormous and the control thereof would be complicated. By using the serial-in/parallel-out type shift register SR as in this example, the number of data lines can be reduced and the control thereof can be simplified.

The selector SEL controls the input of the logic decision information PDATA to the shift register SR. This selector SEL
has a selection switch (not shown) which is controlled by the row selection signal Ri and column selection signal Ci in the logic decision information input path or operation selection control system, and also has a timing clock for serially inputting the logic decision information. Signal CLK and logic decision information PDATA
is supplied from the access control circuit ACONT.

Next, an example of the program operation by the shift register SR when the access control circuit ACONT is used will be described in detail. Note that even when an external control device is used, the program operation can be performed in the same manner as described below. The information necessary to perform program operations is
Address information indicating the address of each shift register SR (
a-D), data indicating the number of shifts or stages of the shift register SR, that is, the number of switch elements such as MISFETs to be programmed; (c-D); and actual program data (p-D).

5tepl: Under the control of the access control circuit ACONT, the first data consisting of the data (a-D), (c-D), and (p-D) is transferred from, for example, the nonvolatile memory ROM to the internal register. .

5tep2: The access control circuit ACONT receives address information (a-D
) selects the selector SEL connected to the desired shift register SR. As a result, the selected selector SEL becomes operable, and the shift register S
Various control signals such as a timing clock signal CLK and a reset signal to the shift register SR are transmitted to the shift register SR.

5tep3: The access control circuit ACONT is a non-volatile memory ROM
Loads the data (P-D) read from the internal register into the internal register, generates a clock pulse corresponding to the data (c-D), and uses this clock pulse to shift the data (p-D) from the internal register to the shift register SR. to control serial transfer.

5tep4: The transferred data (p-D) determines the input state to the gate electrode of the switch consisting of MISFET, and as a result, the logic state is determined or changed.

Furthermore, the access control circuit ACONT has a built-in register for storing the number of program data, and detects that the program data has been transferred to all shift registers SR and that the program has been completed. Upon detecting the completion of the program, the access control circuit ACONT sends a status or status signal to that effect to the previous input/output interface I.
10 and is externally detectably controlled.

Note that the method for controlling the gate electrode of the switch made of MISFET is not limited to this. Also,
There is no need to provide one shift register SR in a single circuit block such as one switch circuit SW2, but there may be two in one switch circuit, or one in two switch circuits. Furthermore, it is desirable that a signal input to the drain of the MISFET that actually determines or changes the logic state be transmitted to the source side without delay.

Therefore, it is preferable for the structure of the MISFET to be a depletion type in which there is no potential drop in the input signal, or an enhancement type in which the gate electrode is boosted. Of course, the present invention is not limited to this, and a normal enhancement type may be used.

An example of a connection logic block MS is shown in FIGS. 3A-3E.

3A is an example of connecting two wires, FIG. 3B is an example of connecting three wires, FIG. 3C is an example of connecting four wires, and 3D is an example of connecting four wires. The figure shows an example in which six wires are connected, and FIG. 3E shows an example in which eight wires are connected. In these examples, when connecting all the wires, one wire is used in the case of Figure 3A, and three wires are connected in the case of Figure 3B.
6 pieces in the case of Figure 3C, 15 pieces in the case of Figure 3D,
In the case of Fig. 3E, 28 switches MISFE
T is required. That is, to connect n wires, n(n-1)/2 switch MISFETs are required.

Connection logic block MS shown in FIGS. 3D and 3E
In actuality, interconnects included in the same interconnect group NL are rarely connected to each other. Therefore, in order to reduce the number of practically unnecessary switch MIS-FETs, it is necessary to not provide the MISFET for connecting the terminals ■ and ■ and the MISFET for connecting the terminals ■ and ■ in Fig. 3D. Can be done. In the case of Figure 3E, the terminal ■
It is possible to avoid providing MISF and ET for connecting and ■, ■ and ■, ■ and ■, and ■ and ■, respectively.

Other examples of connection logic blocks MS are shown in FIGS. 4A and 4B. The connection logic block MS shown in FIG. 4A is connected to the vertical and horizontal wiring groups via switches SWR and SWC, respectively, and the wiring connecting the horizontal switch SWR and the vertical switch SW.
It is configured by arranging switches SWM for connecting vertical and horizontal wiring at each intersection with the wiring connecting C.

According to this, although the degree of freedom of connection between wirings is reduced compared to the previous example, the number of switch MISFETs can be reduced.

The example shown in FIG. 4B is one in which specific intersections, for example, diagonal intersections, are directly coupled instead of the switches SWM at the intersections. In such a configuration, the degree of freedom of connection between wires is further reduced, but by combining it with the switch circuit of the logic circuit block LCB, the same result as the overall degree of freedom of connection between wires can be obtained. Can be done.

According to the above embodiment, the following effects can be obtained.

(1) Non-volatile memory ROM after manufacturing semiconductor integrated circuit
By programming, the logic states of the programmable logic circuit blocks LCB, IOB, and MS can be determined or changed, so that a semi-custom or custom semiconductor integrated circuit with desired functions can be quickly obtained.

(2) Programmable logic circuit block LCB.

Since the logical states of the IOB and MS are determined by the data stored in the non-volatile memory ROM, the logical state determining information can be retained internally even after the power is turned off without receiving program data transfer from the outside. Therefore, compared to the conventional LCA technique, handling of the LSI in terms of system operation and processing for determining logic becomes easier. That is, there is no need to transfer program data via the host processor of the system each time the system is started up by turning on the power, and the system can be operated in a relatively short time.

(3) A large number of programmable logic circuit blocks, CB,
Even if IOBs and MSs are arranged in an array to increase gate usage efficiency, the information that determines each logic state is held in a single nonvolatile memory ROM, and the information read from this ROM is individually volatile. Since the digital memory element latches, the overall circuit configuration for maintaining such a logic state is smaller than that of a conventional PLD, and the chip occupation rate by ancillary peripheral circuits can be kept low.

(4) Programmable logic circuit block LCB.

Since program data for determining or changing the logical states of IOB and MS is serially transferred to the serial-in/parallel-out type shift register SR, the number of data lines or control lines can be reduced.

(5) With the above effect (4), program control of the programmable logic circuit block can be facilitated.

(6) The nonvolatile memory ROM used to store program data is an EPROM that is electrically written and erased with ultraviolet light;
Alternatively, since it is composed of an electrically writable/erasable EEPROM, the logical state can be easily changed.

(7) The above effect (6) makes it easy to obtain various logics depending on the purpose of use even with the same semiconductor integrated circuit.

(8) Since the semiconductor integrated circuit includes the access control circuit ACONT for reading access to the nonvolatile memory ROM and programming the programmable logic circuit block, the semiconductor integrated circuit can easily perform the programming by itself.

Next, a second embodiment of the present invention will be described.

FIG. 5 is a circuit diagram of an example of a programmable logic circuit block when the semiconductor integrated circuit according to the present invention is applied to a programmable logic device. In the same figure,
AND is the AND of programmable logic devices
The logic circuit block forming the plane, OR, is the logic circuit block forming the OR plane of the programmable logic device.

The logic circuit block AND includes a programmable logic function determining element M made of a non-volatile memory element arranged in a matrix, for example an EPROM, and a logic function determining element M arranged in columns.
A plurality of word lines W a n coupled to the gate electrodes of W an
d, and a plurality of data lines Dand coupled to data input/output terminals of the logic function determining element M on a row-by-row basis. Furthermore, a separation switch 5WDand made of a switch MISFET is interposed in the middle of the word line W a and d, and both ends of the word line W a and are input terminals IM1 and IN2.

The logic circuit block OR includes a programmable logic function determining element M made of a non-volatile memory element arranged in a matrix, such as an EPROM, a plurality of word lines Wor coupled to gate electrodes of the logic function determining element M in rows, and columns. Each unit is composed of a plurality of data lines Dor coupled to data input/output terminals of the logic function determining element M. A separation switch 5Wor made of a switch MISFET is interposed in the middle of the data line Dor, and the data line D
Both ends of or are output terminals ○UTI and 0UT2. The word line Wor of the logic circuit block OR is
Data line Da of the corresponding row in the logic circuit block AND
nd through a transfer switch SWT such as a transfer MISFET.

The plurality of separation switches SWD and 5W
Dor is a convolutional PLD (Folded Prog
rammable Logic Device
). Convolutional PLA, which is normally performed to reduce the PLA chip size, blocks cell transistor groups at arbitrary locations in the semiconductor integrated circuit manufacturing process to improve gate utilization. Instead of allowing disconnection at any point during the manufacturing process, the separation switch 5WDand, 5
The switch state of WDor can be arbitrarily programmed via a volatile storage element such as a shift register. If a non-volatile memory element such as MNOS is used as a switch element instead of the volatile switches 5WDan d and 5WDor, the peripheral circuitry for individually programming such a non-volatile switch element becomes complicated. Furthermore, this increases the chip size and increases the convolutional PL.
The significance of configuring D will decrease.

FIG. 6 shows an overall block diagram of a programmable logic device using the circuit of FIG.

In the example shown in FIG. 6, in order to prevent an increase in the number of peripheral circuits, the programming circuit for the logic function determining element M made of a nonvolatile memory element is shared across the entire AND plane.

Moreover, it is common throughout the entire OR plane. That is, AND
Program circuits PWand, PDand are provided for the OR surface, and program circuits PWor, PWor, and PWor are provided for the OR surface.
PDor is provided.

In addition, in the configuration shown in FIG. 6, the separation switches 5WDand,
Although volatile memory elements that hold information that determines the switch state of 5WDor are not shown, for example, each AND plane and OR plane has a register or latch circuit, and for these, a non-volatile memory element similar to that shown in Fig. 1 is provided. It includes a memory ROM, an access control circuit ACONT, etc.

Next, a method of programming the programmable logic device shown in FIG. 6 will be explained.

5tepl: Transfer the program data to the logic function determining element M consisting of a non-volatile memory element and determine the logic state. At this time, the separation switches 5WDand and 5WDor are kept in a conductive state. Further, the transfer switch SWT is used to program the AND side and the OR side separately,
It is turned off during programming and turned on during logic operation.

5tep2: Program data for determining the switch states of the separation switches 5WD and 5WDor is stored in a non-volatile memory (not shown) such as a ROM.

5tep3: The program data stored in the non-volatile memory is transferred to a volatile storage element that constitutes a register, the switch states of the 1-separation switches SWD and 5WDor are determined, and 1-convolution is performed.

In particular, according to this embodiment, programmable logic
Separation switches 5WDand and 5WDor are provided on the word line on the AND side and the data line on the OR side of the device, and these can be controlled arbitrarily based on the information stored in the volatile memory element and nonvolatile memory to create a convolutional structure. By making this possible, a programmable logic device with high gate utilization can be obtained.

Next, a third embodiment of the present invention will be described based on FIG. 7.

In FIG. 7, the MLCB is a programmable large-scale logic circuit block that includes a plurality of LCBs and MSs. The LCB and MS included in this, as well as other LCBs and MSs placed outside the MLCB, are configured in the same manner as described based on FIG. 1. In this configuration, the large-scale logic circuit block MLCB is not a programmable logic circuit block that is independent of other LCBs and MSs, but is rather a
It can be considered to be configured as an LCB. In other words, a functionally coherent logic circuit is a distributed LC.
By configuring it with MLCB rather than configuring it with B and MS,
It becomes possible to eliminate waste of LCB and MS. For example, when configuring an 8-bit register, a remote LC
By configuring the LCB and MS adjacent to each other rather than configuring the LCB and MS, the wirings NL and SL can be used more efficiently. The area of the MLCB may be determined at the time of programming for each required logic circuit. Alternatively, program data necessary to configure a standard logic circuit may be determined in advance, and a logic circuit corresponding to the MLCB may be determined using this data.

The latter is preferable from the viewpoint of usage rate of MS etc. and efficiency of development of program data.

According to this embodiment, there are the following effects.

(1) Since a functionally coherent logic circuit is constructed from adjacent programmable logic circuits and wiring, circuit usage efficiency or gate usage rate is improved.

(2) Since the program data necessary to construct a functionally coherent logic circuit is determined in advance, the overall program data development efficiency is improved.

Next, a fourth embodiment of the present invention will be described based on FIG. 8.

In FIG. 8, NPLC is a programmable circuit block. That is, it is a circuit block whose function is determined in the manufacturing process of a semiconductor integrated circuit. In the same figure,
The configurations of the LCB, MS, etc. are the same as those explained in FIG.

Constructing a logic circuit using only programmable logic circuit blocks such as LCBs and MSs may be inefficient in terms of gate usage rate of semiconductor integrated circuits. For example, logic circuits configured as large-scale memories have recently come into widespread use.

In such a case, constructing a large-scale memory only from programmable logic circuit blocks will result in a very poor gate utilization rate. Therefore, in the logic circuit, a general-purpose circuit block is determined in advance at the manufacturing stage of the semiconductor integrated circuit to configure the circuit block NPLC, and more detailed specifications are determined by the program for the LCB, MS, etc. .

According to this embodiment, the logic configuration of a general-purpose circuit block is fixed or dedicated in advance at the manufacturing stage, and other circuit blocks are configured with programmable logic circuit blocks, so that the gate The utilization rate can be increased, and the overall program data development efficiency can also be improved.

Next, a fifth embodiment of the present invention will be described based on FIG. 9.

In FIG. 9, PLD is a program logic device using a programmable non-volatile memory element as a logic function determining element. The PLD in this embodiment includes a sequential circuit such as a flip-flop. Of course, a PLD having the same configuration as the second embodiment may be used.

Like PLA, PLD is composed of an AND array and an OR array, so basically any combinational circuit can be constructed. LCB, IOB, instead of PLD
Although a desired logic circuit may be configured using a programmable logic circuit block such as an MS, depending on the configuration of the logic circuit to be programmed, there is a possibility that the gate usage rate may be extremely poor. In such a case, by configuring a part of the programmable logic circuit block using a PLD, it is possible to meet the demand for configuring random logic using a PLD.

Next, a sixth embodiment of the present invention will be described based on FIG. 10.

In this embodiment, the programmable logic circuit block LCB
A PLD using a programmable non-volatile memory element
It consists of As this PLD, the one described in the second embodiment or one having another configuration can be adopted.

According to this embodiment, convolution as explained in FIGS. 5 and 6 can be performed on the entire scale of the semiconductor integrated circuit.

Next, a seventh embodiment of the present invention will be described based on FIG. 11.

The example in FIG. 11 is an embodiment applied to a microcomputer. The microcomputer shown in the figure is formed on a single semiconductor substrate such as silicon, and includes a central processing unit (hereinafter simply referred to as central processing unit) CPU, nonvolatile memory ROM, volatile memory RAM, and programmable logic. It includes a circuit PL and an input/output interface I10.

The central processing unit CPU has the function of a microprocessor and is composed of a control section, an arithmetic section, and various registers. The non-volatile memory ROM stores programs for executing calculations and various data, and is constituted by, for example, an EPROM or an EEPROM. The volatile memory RAM is used as a temporary storage area or a work area for temporarily storing data during calculation. Input/output interface E/○ is interfaced with the outside.

The programmable logic circuit PL is shown in FIGS. 1, 5, and 6.
The configuration shown in the figure or FIG. 10 is adopted. That is, it is configured to include at least a volatile storage element for receiving and receiving information from the nonvolatile memory ROM and determining a logical state. Each functional module included in this microcomputer) Lt CU P, ROM
, RAM, PL, and Ilo are interconnected by an internal bus BUS for exchanging address, data, and control signals. In particular, the interface section BP in the programmable logic circuit PL is used exclusively for transmitting information for determining the logical operation of the programmable logic circuit PL. Further, the other interface section BA is used when performing a logical operation after the logical state is determined. The access control means for read accessing the nonvolatile memory ROM and providing logic determination information to the programmable logic circuit PL in a program operation for the programmable logic circuit PL is configured to control the access control means for providing logic determination information to the programmable logic circuit PL.
This is realized by the functions of U.

Next, the operation of the above microcomputer will be explained.

When programmable logic circuit PL is used as a fixed logic circuit, the logic state of programmable logic circuit PL is determined by a method similar to the embodiment shown in FIG. For example, the central processing unit cpU accesses the nonvolatile memory ROM, reads logic determination information onto the internal bus BUS, and transfers this to the volatile storage element of the programmable logic circuit PL via the interface section BP. As a result, a desired logic state is set in the programmable logic circuit PL. After the logical state is determined in this way,
A microcomputer performs logical operations based on an operation program stored in a nonvolatile memory ROM. Therefore, during operation from power-on to power-off,
The logic state of the PL is fixed and is the same as the logic state determined during the manufacturing process. In this embodiment, the nonvolatile memory ROM functions as a memory that stores programs and various data for executing normal operations, and also functions as a data memory that stores program data for the programmable logic circuit PL.

It is also possible to change the logic state of the programmable logic circuit PL during the operation of the microcomputer. The process for changing the logical state can be performed in the same manner as described above.

Therefore, between the time the power is turned on and the time the power is turned off, +'
Since the logic state of PL can be changed, one logic circuit PL can be used as a plurality of logic circuits, which is apparently the same as having a plurality of logic circuits whose logic states are determined in the manufacturing process.

Of course, the above-mentioned operation is for determining or changing the external logical state of the CPU, but can also be applied when determining or changing the internal logical state of the cPU.

According to this embodiment, there are the following effects.

(1) Since the state of the programmable logic circuit PL mounted on the microcomputer can be determined or changed after manufacturing the semiconductor integrated circuit device, microcomputers with a plurality of specifications can be obtained from the same microcomputer LSI. In other words, any peripheral function can be realized by the programmable logic circuit block PL.

(2) Since the state of the programmable logic circuit PL mounted on the microcomputer can be changed during the operation of the microcomputer, even a single logic circuit is essentially the same as mounting multiple logic circuits.

(3) According to (2) above, the software processing of the microcomputer can be replaced with processing by hardware arbitrarily set in the programmable logic circuit PL, so high-speed processing becomes possible.

(4) According to (2) above, the degree of integration of the microcomputer can be improved.

(5) Access control for determining or changing the state of the programmable logic circuit PL installed in the microcomputer is performed by the central processing unit CPU, and program data is stored in the installed nonvolatile memory ROM, so unnecessary No control circuit or memory circuit is required.

(6) According to (5) above, the control circuit and memory circuit are shared for the program for the programmable logic circuit PL and the logical operation of the microcomputer, so the degree of integration of the microcomputer is improved and the system configuration is also simplified. become.

Next, an embodiment in which the programmable logic circuit PL is used as a redundant configuration will be described by applying it to a microcomputer or the like.

The semiconductor integrated circuit shown in FIGS. 12A to 12C is
In a logic integrated circuit such as a microcomputer, the logic circuit blocks 61 to C8 included in the area surrounded by broken lines have their respective logics fixedly determined, for example, in the manufacturing process of semiconductor integrated circuits, and these logic circuit blocks 01 to C8 constitute a logic integrated circuit having one function. The programmable logic circuit PL is a logic block whose logic state can be determined or changed after the semiconductor integrated circuit is manufactured, as described in the previous embodiment.

The logic integrated circuit shown in FIG. 12A is an example of a microcomputer in which logic circuit blocks 01 to C6 are commonly connected to an internal bus BUS. The programmable logic circuit PL is also connected to the internal bus BUS.

The logic integrated circuit shown in FIG. 12B is an example in which logic circuit blocks C1 to C4 are connected in series. Each logic circuit block 01 to C4 is connected to a serial connection bus BUS.
I, BUS2. Connected by BUS3. Programmable logic circuit PL is serially connected buses BUSI, BUS
2. It is connected to the logic circuit blocks 01 to C4 by a redundant bus RBUS different from BUS3.

The logic integrated circuit shown in FIG. 12C is an example in which logic circuit blocks C1 to C8 have a portion commonly connected to the internal bus BUS and a portion connected by serially connected buses BUS1 to BUS4. be. The programmable logic circuit PL is connected to the logic circuit blocks 01 to C8 by a redundant bus RBUS. In this case, an internal bus BUS to which logic circuit blocks are commonly connected may be partially utilized.

Next, a method for repairing a faulty circuit using the redundant programmable logic circuit PL will be described.

If a logic circuit block fails or does not perform the desired operation during an operation test after manufacturing a semiconductor integrated circuit or during subsequent operation, the logic circuit block is repaired as follows.

(1) Program the logic of the programmable logic circuit PL so that it has the same logic function as the logic circuit block that has failed or no longer performs the desired operation.

(2) Inactivate the logic circuit block that has failed or is no longer performing the desired operation.

(3) Connect input/output signals and various control signals for a logic circuit block that has failed or is no longer performing the desired operation to the programmable logic circuit PL. For example, the 12th
In the case of FIG. A, similar to the case of FIG. 11, this is done via the common internal bus BUS. In the case of FIG. 12B, this is done via a dedicated redundant bus RBUS. That is, when the logic circuit block C2 is in failure, C2 is made inactive and the route leading to C1, BUS 1, C2, BUS2, and C3 is changed to the route of C1, RBUS, PL, RBUS, and C3. In the case of FIG. 12C, the processes in FIGS. 12A and 12B may be combined.

In this embodiment, the case where one logic circuit block is repaired has been described, but it is also possible to rescue a plurality of logic circuit blocks. Furthermore, although this embodiment has described the repair within a single semiconductor integrated circuit, the method of this embodiment can also be used to repair a failed semiconductor integrated circuit itself in a system consisting of a plurality of semiconductor integrated circuits. Needless to say.

According to this embodiment, there are the following effects.

(1) Since it is equipped with a programmable logic circuit PL that can be programmed after manufacturing, if a logic circuit whose logic state is determined during the manufacturing process is out of order, it can be repaired using the programmable logic circuit PL.

(2) From the above, the yield of semiconductor integrated circuits can be improved. Furthermore, it is possible to rapidly manufacture and provide a wide variety of semi-custom semiconductor integrated circuits in small quantities.

Although the present invention has been specifically described above based on examples, the present invention is not limited thereto, and can be modified in various ways without departing from the gist thereof.

For example, the method of transmitting the logic decision information of the nonvolatile memory to the volatile storage element of the programmable logic circuit block is not limited to serial transfer, but may be parallel data transfer.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, it employs a programmable logic circuit block whose logic state is variably set according to the information stored in the volatile memory element, and a built-in non-volatile logic circuit block in which information for determining the logic state of the logic circuit block can be electrically written. By configuring a semiconductor integrated circuit in such a way that it is stored in memory, flexibility is gained in the internal configuration of programmable logic circuit blocks in terms of the number of inputs and outputs and the number of product terms, as well as in the arrangement between multiple programmable logic circuit blocks. Even if gate usage efficiency is increased, the resulting significant increase in chip occupation rate can be suppressed, and
This eliminates the need to transfer program data from the outside, which was conventionally required every time the power is turned on, and has the effect of facilitating the handling of a semiconductor integrated circuit incorporating a programmable logic circuit block.

A plurality of the programmable logic circuit blocks are arranged and connected by wiring for connection between the programmable logic circuit blocks, and the connection state between the wirings is determined by some of the programmable logic circuit blocks. By doing so, the flexibility or versatility of the logic that can be set in the programmable logic circuit can be increased to a level comparable to that of a gate array.

In addition, by configuring a semiconductor integrated circuit including an access control means that is dedicated or used for other processing, logic determination information stored in nonvolatile memory can be loaded into the volatile storage element of the programmable logic circuit block. Processing can now be performed from a semiconductor integrated circuit mill. Therefore, it is no longer necessary to burden the host processor of the system with such processing every time the power is turned on.

Furthermore, at this time, by making it possible to notify the end of the program operation by the built-in access control means to the outside,
System operation can be started immediately after the program operation is completed.

Further, by configuring the volatile memory element using a serial-in/parallel-out type shift register, the number of signal wires for transferring logic determination information to the volatile memory element can be reduced.

Furthermore, when the semiconductor integrated circuit of the present invention is applied to a microcomputer, a central computer that performs logic control operations using the programmable logic circuit block may be used.
By including the processing unit, its programmable logic circuit block can be used to implement the desired peripheral functions for the central processing unit, and since it is programmable, it can also be used as a redundant function for peripheral functions. It has the advantage that it can also be used.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a semiconductor integrated circuit according to an embodiment of the present invention, FIG. 2A is a block diagram of a logic circuit block that is an example of a programmable logic circuit block, and FIG. 2B is a switch circuit included in the logic circuit block. Example Block Diagram FIG. 2C is an example block diagram of a shift register configured with volatile memory elements. 3A to 3E are circuit diagrams of connection logic blocks which are other examples of programmable logic circuit blocks, and FIGS. 4A and 4B are circuit diagrams showing other examples of connection logic blocks. Figure 5 is a circuit diagram of an example of a programmable logic circuit block when the present invention is applied to a programmable logic device, and Figure 6 is an overall block diagram of a programmable logic device using the circuit shown in Figure 5. FIG. 7 is a block diagram of another embodiment of the invention, FIG. 8 is a block diagram of another embodiment of the invention, and FIG. 9 is a block diagram of still another embodiment of the invention. FIG. 10 is a block diagram of yet another embodiment of the present invention, FIG. 11 is a block diagram of an embodiment in which the present invention is applied to a microcomputer, and FIGS. 12A to 12C are programmable semiconductor integrated circuits according to the present invention. FIG. 2 is a block diagram of an embodiment in which logic circuit blocks are used as a redundant configuration. LCB...logic circuit block, IOB...input/output circuit block, MS...connection logic block, NL...
Wiring group, SR...shift register, 5LAT1~5L
AT15...Static latch, SEL...Selector, ACONT...Access control circuit, ROM...
・Non-volatile memory, LC...logic circuit section, SWI, S
W2...Switch circuit, AND...Logic circuit block, ○R...Logic circuit block, 5WDan d,
5WDor...separation switch, MLCB...large scale logic circuit block, CPU...central processing unit, PL...programmable logic circuit. A Fig. 2B Fig. C Fig. 30 Fig. 1 Fig. A Fig. L-1 Fig. B Fig. C Fig. 4A Fig. N and L Fig. 4B L Fig. 8 Fig. L Fig. 10 Fig. 1 Fig. 12A figure

Claims (1)

[Claims] 1. A non-volatile memory in which information can be written electrically; and a volatile memory element for retaining information according to the information stored in the non-volatile memory; A semiconductor integrated circuit that includes a programmable logic circuit block whose logic state is variably set according to stored information on a single semiconductor substrate. 2. A plurality of the programmable logic circuit blocks are arranged, and the programmable logic circuit blocks are connected by wiring for connecting between the blocks, and the mutual connection state of the wiring is determined by some of the programmable logic circuit blocks. 2. The semiconductor integrated circuit according to claim 1, comprising: 3. The semiconductor integrated circuit according to claim 1, further comprising access control means for writing logic determination information read from the nonvolatile memory into a required volatile storage element. 4. The semiconductor integrated circuit according to claim 3, further comprising interface means for notifying the outside of a state in which the logic states of the programmable logic circuit blocks have been determined by the access control means. 5. The volatile storage element of the programmable logic circuit block is included in a serial-in/parallel-out type shift register, and the access control means is capable of controlling selection of the shift register and controlling serial transfer of information. 4. The semiconductor integrated circuit according to claim 3. 6. The semiconductor integrated circuit according to claim 1, further comprising a central processing unit that performs logical operations using the programmable logic circuit block.