JPH03127104A - Data link device of programmable controller - Google Patents

Abstract

PURPOSE:To effectively utilize a common link register and to improve the transmission/reception processing efficiency by providing a means which can transmit data to an arbitrary area of a specific PC, when a sequence program is being executed. CONSTITUTION:In a CPU unit part 3, a link table 35 for storing link register allocating information, a parameter table 33 which is used for transmitting separate data and a link actuation program 38 refers to, a separate data transmitting request flag 30, a separate data transmitting buffer 31, a separate data link condition register 32, and a bus buffer 40 are connected. In such a state, in the case a link register being common to all programmable controllers (PC) whose size is limited is divided as a transmitting register range of every PC, the division and allocation are executed by detaining them to a link register range used in common by all the PCs to the utmost and a data link is executed, and in accordance with necessity, separate data is also transmitted. In such a way, the common link register is utilized effectively and the transmission/ reception processing efficiency can be improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides data for a PC that is suitable for realizing distributed control such as line control and plant control using a programmable controller (hereinafter referred to as PC) used for various types of control. Regarding a link device.

[Conventional technology]

Traditionally, a data link between 20
have a common link register, divide the common link register in advance as a transmission register range for each PC, and set the division information for the total 40 minutes in the link table of the master PC, or set it separately in the link table of each PC. Set the transmit register range. After that, each PC transmits the data of the link register assigned to its own machine using the broadcasting method, so that all other PCs
refreshes the link register range assigned to the source PC in the common link register of the own machine. By repeating this process, the linking method was such that all PCs shared common data.

In addition, a related data link method for this type of programmable controller is disclosed in Japanese Patent Application Laid-Open No. 62-121.
505 and those described in JP-A-62-200839.

[Invention tries to solve! +11 problems] In the above conventional technology, the common link register is divided among all PCs by the register range that each sends, so if the link register range used only among a certain small number of 20 is large, it will be difficult for many other PCs to use the common link register. The unnecessary range became large, and the range of the transmission link register of the own machine was severely limited, which caused problems in terms of the efficiency of use of the common link register.

An object of the present invention is to effectively utilize a common link register and improve transmission/reception processing efficiency in a PC data link using a common link register.

Another object of the present invention is to improve single line efficiency and speed up data transmission.

[Means to solve the problem]

In order to achieve the above purpose, a link activation program as one command of the sequence program and a parameter table for individual data transmission to be referred to by the link activation program are provided, and a certain arbitrary This system employs means that can transmit data to any memory area of a specific PC.

In order to achieve the other objectives mentioned above, a communication type code is provided in the transmission frame to distinguish three types: common data only, individual data only, and common data and individual data simultaneously. This method employs a method of detecting and discriminating.

[Effect]

When dividing a link register common to all PCs whose size is limited as a transmission register range for each PC, perform data linking by dividing and allocating the link register range that is commonly used by all PCs as much as possible. By means of transmitting data in the arbitrary memory area of the own PC to the arbitrary memory area of the arbitrary PC at the user's arbitrary timing, individual data can also be transmitted as needed, which improves the effective use of common link registers and the efficiency of transmission/reception processing. can be improved.

In addition, line efficiency is improved by adding individual data to be transmitted at a user's arbitrary timing to the transmission frame in the data link using the common link register by repeating transmission by each PC in one cycle. , it is possible to speed up data transmission in terms of common data and individual data.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the overall configuration of a data link device for a PC, which is a feature of the present invention.

Each PCI consists of a link unit section 2 and a CPU unit section 3, and is connected to other PCs via a serial bus 4.

The link unit section 2 and the CPU unit section 3 are connected by a bus 28 and a bus 39 via a bus buffer 40.

In the link unit section 2, the data link processing CPU 23. A link register 25 in the link unit section for temporarily storing common link registers received from other PCs, a link table 26 in the link unit section for storing information about link register allocation, and an individual data transmission flag 22 used for individual data transmission. Individual data importing flag 21. Transmission buffer 24. A receive buffer 20 and a serial bus controller 27 consisting of DMAC and ADLC are connected.

In the CPU unit section 3, the bus 39 is connected.

Sequence program memory 37 for storing sequence programs. A CPU 36 for sequence program processing that reads and repeats execution of sequence programs, a link register 34 for common data links shared by all programmable controllers, a link table 35 for storing information for the link register allocation of the own PC, and a link for individual data transmission. A parameter table 33 referenced by the startup program 38, an individual data transmission request flag 30 for individual data transmission, an individual data transmission buffer 31, an individual data link condition register 32, and the path buffer 40.
is connected.

Data transmission and reception operations are performed by r) MA transfer between the serial bus 4, the transmission buffer 24, and the reception buffer 20 by the serial bus controller 27 under the control of the data link processing CPU 23. Ru.

Further, the transfer of common link register data and individual data between the link unit section 2 and the CPU unit section 3 is executed by the data link processing CPU 23, so that the sequence program processing CPU
U36 can concentrate on sequence program processing and continue smooth control.

The processing of the data link processing CPU 23 is roughly divided into transmission processing, reception processing, and idle processing.

The transmission process is a timer interrupt process, and a timer counter for transmission timing is set for each transmission and reception based on the sequential transmission method in ascending order of PC numbers and a certain transmission interval between consecutive numbers pc.

The reception process is an interrupt process by detecting a flag of a transmission frame, and transfers the received link register data from the reception buffer 20 to the link register 2 of the link unit section.
5, the received individual data is directly transferred to the designated area and the process ends.

In the idle process, the contents of the link unit 91 to unit link register 25 are transferred to the link register 34, and the final stage link register 34, which is reflected in the sequence program, is refreshed.

Further, the contents of the own PC transmission register range in the link register 34 and, if there is an individual data transmission request, the individual data are transferred to the transmission buffer.

In FIG. 2, it is provided as one command of the sequence program. A method of starting the link starting program 38 will be described.

In FIG. 2, the sequence program 50 is executed in a scanning manner. Control system condition program 51
After determining in step a that it is necessary to send certain individual data to a specific PC, the destination PC number, individual data, number of words to be sent, transmission data storage address within the own PC, and destination PC are entered in the parameter table 33. The internal transmission data storage address is set by means such as a DST (data set) command.

Next, ask if you want to start the link startup program 5END.
The control system condition program 51b determines the necessary control conditions, and the link system condition program 52 determines that the link unit section 2 can be linked and that the individual data transmission due to the previous activation is completed.

The others are determined and the link activation program 5END is activated. At this time, the parameter table top address 53 needs to be programmed in advance;
This is not necessary if the parameter table is fixed. Further, if the content of the parameter table 33 is programmed in advance, the DST command is not required.

However, as shown in FIG. 2, a system in which parameters can be dynamically set and changed by executing a sequence program enables flexible control.

FIG. 3 shows the sequence program processing CPU 36.
The movements of each table and data related to the link activation program processing by the data link processing CPU 23, and the idle processing, transmission processing, and reception processing by the data link processing CPU 23 are shown in (1) to (4) below.

In FIG. 3, the common link register transmission range assigned to the own PCG number j set in the link table 35 is taken into the link table 26 in the initial processing.

(1) The link starting program started by the sequence program checks the rationality of the parameter table 33 in step H8I according to the processing procedure shown in FIG. 4, and checks the contents of the parameter table 33 and the individual data in step H82. Based on the contents of the link condition register 32, it is determined whether the link unit section 2 is capable of link operation and whether the individual data transmission buffer 31 is empty, etc., and if the current transmission of individual data is not possible, step H56 is performed.
Then, error information is set in the individual data link condition register 32, and the process returns to the sequence program. It should be noted that the individual data link condition register 32 includes a link activation program and the data link processing CPU 23.
The link system condition program 52 shown in FIG. 2 incorporates this internal contact as a condition.

After it is determined in step H52 that transmission is possible, the individual data link condition register 32 is immediately set to disable transmission in step H83. This is important as a means to avoid multiple activations from sequence programs executed in the scanning method. Further, the data link processing CPU 23 switches the information indicating that transmission is not possible to possible when the current individual data transmission is completed. Step H3
4, according to the contents of the parameter table 33, individual data is sent from the individual data storage area 41 of the address specification to the individual data transmission buffer 31, and separate data is sent from the parameter table 33 to the destination PC number 2. The number of words and the data storage address in the destination PC are respectively imported.

Furthermore, set individual data available as the communication type code,
The number of link register words is calculated from the link register allocation range information of the own PC in the link table 35 as the number of common group words, and the value obtained by adding the number of words of the link table information to that is set, and the number of individual data transmission words is set as the number of individual group words. Set the total number of words for the destination PC's transmission data storage Natres information and individual data. Finally, in step H35, the individual data transmission request flag 30 is set to ONL, and the process returns to the sequence program.

(2) The idle processing of the data link processing CPU 23 repeats steps ISI to IS7 in accordance with the processing procedure shown in FIG.

In the data link of the common link register according to the prior art described above, only step IS7 is repeated.

At step ISI, the individual data transmission request flag 30
0N10FF is determined, and if it is ON.

Set the individual data importing flag 21 to O in step IS2.
NL, the contents of the individual data transmission buffer 31 are taken into the transmission buffer 24 in step IS3. Here 1
The area for capturing the contents from the individual data transmission word count information to the individual data changes depending on the number of common words, and if the number of common words is O, the area for link table information and common data in the transmission buffer 24 will be deleted. Furthermore, in step IS3, the own PC number is set as the source PC number. Steps IS4 to IS6
Then, the individual data transmission flag 22 is turned on, the individual data transmission request flag 30 is turned off, and the individual data fetching flag 21 is turned off. Step I so far
S2゜IS4. Each processing result of IS6 is used to select a transmission means in a transmission processing procedure described later. Step I
In S7, link register information received from another PC is transferred from the link register 25 of the link unit section to the link register 34 of the CPU unit section, and if there is a transmission link register assignment for the own PC, the link register information in the assigned range is transferred. Transfer information from the link register 34 to the transmit buffer 24.

(3) The transmission process is a processing procedure shown in FIG. 6, in which link register common data single transmission, two-group data single transmission, and common data and individual data simultaneous transmission are performed. In the data link of the common link register according to the prior art described above, only step TS4 is processed.

At step TS1, the individual data transmission flag 22 is checked, and if it is OFF, at step TS2, the individual data fetching flag 21 is checked and turned OFF.
In this case, in step TS3, the link table 2
Check if there is own PC transmission link register allocation in 6. If there is, no individual data as communication type code, own PC number as sender PC number, own PC transmission link from link table 26 as link table information. The register allocation range and the total number of words of link table information and common data as the number of common words and O as the number of individual words are set in the transmission buffer 24, and step TS
4, the data is sent to the serial bus 4 as only common data.

If it is ON in step TS1, it is checked in step TS5 whether there is any own PC transmission link register assignment in the link table 26, and if not, step T
Only the individual data is transmitted in S6. In addition, if there is own PC transmission link register allocation, the own PC transmission link register allocation range of the link table 26 is set in the transmission buffer 24 as link table information, and common data and individual data are simultaneously sent out in step TS7. do.

Note that the individual data transmission flag 22 is reset to OFF when the transmission of individual data is completed.

(4) In the data link of the common link register according to the prior art described above, whose reception processing procedure is shown in FIG.
84 to R86.

If the presence of individual data is detected based on the communication type code of the reception buffer 20 in step R8I.

Only the PC that detects that the destination PC number matches its own PC number in step R32 refers to the number of individual data transmission words in the reception buffer 20 and the transmission data storage address in the destination PC in step R83, and Data to CP
Transfer to the designated area of the U unit section 3. Step R8
4, the presence/absence of common data is further detected from the number of common words, and if common data is present, link table information is transferred to the source PC of the link table 26 in step R35.
The area corresponding to the number is set, and in step R86, the common data in the reception buffer 20 is transferred to the link register 25 according to the contents of the link table information, and the reception processing is completed.

As is clear from the above data link example, by providing a link activation program in the sequence program instruction and providing a means to easily combine the individual data resulting from the link activation program with the data of the common link register that is transmitted at a constant cycle, the line In addition to improving the memory efficiency of the common link register area, it also enables address-free data linking while online, allowing even small PCs that cannot secure a large common link register area to perform data links comparable to large-capacity large PCs. It has the effect of being able to.

In addition, in the data link using the common link register, the receiving PC
There is no simultaneity in the contents of the transmission register range of other PCs that are referenced by the PC, and a complicated sequence program is required to handle them as text data. On the other hand, individual data generated by the link activation program has the effect of maintaining simultaneity.

In addition, in the above embodiment, the transmission of individual data was limited to a certain specific PC, but the type of communication type code is added, and the destination PC number in that case is set as a group number that is set in advance to multiple PCs. By doing so, it is also possible to specify multiple PCs.
It is also possible to use all PCs.

〔Effect of the invention〕

As described above, according to the present invention, in the data link of PCs, each PC can transmit data to other specific PCs when necessary according to its control state, improving line usage efficiency and internal processing. This has the effect of improving efficiency.

In addition, by not being limited by the limited data link area, memory efficiency of the data link area is improved, and sequence programs can be simplified by making it possible to send text data simultaneously. There is.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the overall configuration of a PC data link device,
Fig. 2 is a diagram showing the starting method of the link starting program, Fig. 3 is a diagram showing various tables and data movements related to data link processing, Fig. 4 is a diagram showing the processing procedure of the link starting program, and Fig. 5 is a diagram showing the processing procedure of the link starting program. The figure shows the idle processing procedure,
FIG. 6 is a diagram showing the transmission processing procedure, and FIG. 7 is a diagram showing the reception processing procedure. 21...Individual data capture in progress flag, 22...Individual data transmission flag. 24... Transmission buffer, 33... Parameter table, 38... Link activation program 2nd prisoner S mouth figure

Claims (1)

[Claims] 1. A sequence program memory that stores a sequence program, a sequence program processing CPU that repeatedly reads and executes the sequence program, a data ring processing dedicated CPU, and a common data link that is shared by all programmable controllers. A plurality of programmable controllers are connected to a serial bus and each programmable controller is connected to a serial bus, and each programmable controller receives the common data of the link register assigned to its own programmable controller based on the contents of the link table. A common data transmission means that a programmable controller periodically transmits to all other programmable controllers is provided with a parameter table for individual data transmission and a link activation program as one command of the sequence program, and the parameter table is provided with a link start program as one command of the sequence program. Based on the destination programmable controller number, the number of words to be sent, the data storage address of the destination programmable controller, and the data storage address of the own programmable controller written in the table, the link startup program sends the edited and prepared individual data. A data link device for a programmable controller, characterized in that it also includes individual data transmission means for transmitting individual data. 2. In the programmable controller data link device, a communication type code is provided in the transmission frame, and the common data sent to all other programmable controllers and the individual data sent to a specific programmable controller are transmitted alone or in combination. 1. A data link device for a programmable controller, comprising means for transmitting data in the same transmission frame, and receiving means for selecting received common data and individual data.