JPH03117986A - Signal processing system - Google Patents

Abstract

PURPOSE:To obtain a satisfactory video signal without reset noise, etc., by once forming an output signal from a solid-state image pickup device to be a digital signal and forming it to be an analog signal with a prescribed data rate. CONSTITUTION:The analog signals outputted from horizontal CCD 11-13 are respectively formed to be the digital signals with a clock rate 1/3fc by an A/D 14 to 16. The reset noise, and the information of amplitudes and phases are not included in the obtained digital signals. Next, these digital signals are outputted as one digital signal through a rearranging means, which arranges the signals in a prescribed suitable order, namely, through a rearranging circuit 17. This once digital signal is converted to one analog signal with a clock frequency fc, for example, by a digital/analog converting means, namely, by a digital/analog conversion circuit (D/A). Thus, the reset noise is removed.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a solid-state imaging device used in, for example, a television camera, and more particularly, to a solid-state imaging device signal from which clock noise has been removed. Regarding processing method.

(Prior Art) FIG. 8 is a block diagram of a currently used solid-state imaging device, that is, an interline transfer type CCD image sensor.

The photoelectrically converted signal charges are accumulated in the light reception accumulation section 81. The signal charges transferred via the vertical CCD 82 and the horizontal CCD 83 are converted into voltage at the output section 84 and output to the outside.

In the CCD image sensor having the above configuration, in order to improve the resolution characteristics of the sensor, the light receiving accumulation section 81 in the light receiving surface is
A method is used to increase the number of For this purpose, it is necessary to increase the frequency at which signal charges are read out, that is, the data rate fc. Alternatively, there is a method of leaving the data rate fc as it is and providing a plurality of output sections to substantially increase the data rate fc. Next, an example will be shown in which a plurality of output units are provided. Figure 9 shows a CC with three output sections.
It is a block diagram of a D image sensor. In the figure, signal charges transferred from horizontal CCDs 91, 92 and 93 are outputted via output sections 94, 95 and 96, respectively. The horizontal CCDs 91, 92 and 93 operate at a data rate fc/3. FIG. 10 is a diagram of an adder circuit that converts the signals output from the output sections 94, 95 and 96 into one signal. In this case, outputs 94, 95 and 96
The signal with a data rate f c /3 output from
The adder circuit 101 integrates the signals into one analog signal having a data rate fc.

Figure 11 shows a CCD with three horizontal CCDs as shown in Figure 9.
It is an output waveform diagram of a CD image sensor.

11(a) shows the output waveform of the output section 94, FIG. 11(b) shows the output waveform of the output section 95, and FIG. 11(c) shows the output waveform of the output section 96. FIG. 11(d) shows the above-mentioned addition circuit 101.
The output waveform of is shown. Furthermore, the phases of these output waveforms are shifted by 120°. 111 is reset noise,
112 is an O level signal after reset, and 113 is a signal.

Conventionally, as shown in FIG. 11(d), a small noise 114 is generated.
occurred in the output waveform, causing a problem.

12(a) shows the noise of the signal from one output section 84 shown in FIG. 8, and FIG. 12(b) shows the noise of the signal from the three output sections 94, 95, 96 shown in FIG. shows the noise in the signal from. As shown in the same figure, one horizontal C shown in FIG.
If there is noise in the clock frequency fc when using a CD, the signal is below 1/2 fc, so this noise can be easily separated through a filter. However, as shown in FIG. 9, three output sections 94,
When the angle is 95°96, noise of 1/3 f c is mixed in the signal of 1/2 f c or less. There is a problem in that it is difficult to separate this even if a filter is used.

(Problem to be Solved by the Invention) As described above, in the past, multiple horizontal CCD sensors were used to increase the resolution, and a method was used in which the outputs of these sensors were integrated into one output signal via an adder circuit. ing. However, in the case of such an image sensor, there is a problem in that the reset noise cannot be separated because it handles signals of up to 6 OdB in reset noise.

The present invention has been made in view of the above problems, and an object thereof is to provide a signal processing method that can remove reset noise.

[Structure of the Invention] (Means for Solving Issues) The signal processing method according to claim 1 of the present invention includes a plurality of light receiving and accumulating means arranged two-dimensionally on a semiconductor substrate; A vertical transfer CCD and a horizontal transfer CCD for transferring the signal charge accumulated in the accumulation means, and n pieces (n≧2) for converting the transferred signal charge into a voltage signal with a data rate f c /n. In the solid-state imaging device, the voltage signal is converted into n signals through n analog-to-digital conversion means under the control of a clock frequency fc, and the n digital signals are converted into n signals. The method is characterized in that after the signals are rearranged into a predetermined number of digital signals through a rearrangement means, the predetermined number of digital signals are converted into one analog signal at a data rate fc by a digital-to-analog conversion means. The signal processing method according to claim 2 is the signal processing method according to claim 1, wherein adjusting means is provided between the analog-to-digital converting means and the rearranging means, thereby adjusting the offset and gain of the n digital signals to a predetermined value. The signal processing method according to claim 3 is characterized in that the signal processing method according to claim 1 is a three-element color camera equipped with only three of the solid-state imaging devices, in which the analog and digital After 3n conversion means are provided and the 3n digital signals obtained by these are rearranged into a predetermined number of digital signals via the rearrangement means, the predetermined number of digital signals are converted into data by the digital-to-analog conversion means. It is characterized by performing rate 2fc or 3fc digital-to-analog conversion and converting it into a single analog luminance signal.

(Function) In the signal processing method of the present invention, a plurality of horizontal CCDs
The output signal is converted into a digital signal using, for example, an analog-to-digital converter. Next, after passing through a rearranging means, these digital signals are converted into one analog signal via a digital-to-analog converter at a clock rate of 2fc or 3fc depending on the number of horizontal CCDs.

Since the output signal is digitized in this way, reset noise and the like can be removed at that point.

(Example) Examples of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a solid-state imaging device using the signal processing method of the present invention.

In the figure, the light receiving and accumulating means for accumulating signal charges, that is, the light receiving and accumulating section, and the vertical transfer CCD, that is, the vertical CCD are omitted. In this embodiment, a case will be explained in which three horizontal CCDs are used.

11. 12 and 13 are the outputs of the horizontal CCD, each operating at a clock rate of 1/3 f c.

Reference numerals 14, 15, and 16 are analog-to-digital conversion means, ie, analog-to-digital conversion circuits (A/D), for converting the output signals (analog signals) from the horizontal CGDs 11, 12 and 13 into digital signals.

The signal processing operation in the solid-state imaging device having the above configuration will be explained.

First, the analog signals output from the horizontal CCD IIs, 12 and 13 are
It is converted into a digital signal at D14, 15 and 16. The resulting digital signal does not contain reset noise, amplitude and phase information. Next, these digital signals are outputted as a single digital signal through a rearrangement means, ie, a rearrangement circuit 17, for arranging them in a predetermined appropriate order. Then, this one digital signal is converted into a digital-to-analog converter at a clock frequency fc, for example.
That is, it is converted into one analog signal by a digital-to-analog conversion circuit (D/A).

In this way, by using the signal processing method shown in this embodiment, the amplitude and phase of reset noise can be removed when converting into a digital signal.

FIG. 2 is a configuration diagram of a solid-state imaging device using a signal processing method according to another embodiment of the present invention. In this embodiment, A/D
Between the converters 14, 15 and 16 and the reordering circuit 17 there are provided primary conversion circuits 21, 22 and 23. Other than this, the structure is similar to that of the embodiment shown in FIG. This primary conversion circuit includes A/D converters 14, 15 and 16.
The offset and gain of the digital signal output from the digital signal are adjusted to have the same level. This makes it possible to equalize the digital signals.

FIG. 3 shows a configuration diagram of an embodiment in which the signal processing method of the present invention is applied to a three-lens color camera.

This three-element color camera uses a pixel shifting configuration. In the figure, the light enters the prism 39 and becomes green (G).
, red (R), and blue (B).

The separated lights enter image sensors 31, 32, and 33, respectively. The image sensors 31, 32, and 33 are slightly shifted relative to the incident light. The outputs from the image sensors 31, 32 and 33 are converted into digital signals by A/D converters 34, 35 and 36. Thereafter, these digital signals are rearranged via a rearrangement circuit 37. Next, the rearranged single digital signal is converted into an analog signal via the D/A converter 38.

The clock rate at which this D/A converter 38 operates is
Determined according to the picture element shifting method. For example, the output signals of A/D converters 34, 35 and 36 are each 120'
If the phase difference is A, the data rate is 3fc, for example, A
A/D converters 35 and 3
If the output signal of No. 6 has a phase difference of 180', the data rate is 2fc.

The light receiving and accumulating sections 54, 55 in the three image sensors 31, 32 and 33 described above. and 56 are shifted from each other by a predetermined distance as shown in FIG. FIG. 5(a) is a block diagram of the image sensor 31, which receives, for example, separated green (G) light. Fifth
Figure (b) is a configuration diagram of the image sensor 32, which receives separated red (R) light. FIG. 5(C) is a block diagram of the image sensor 33, which receives the separated blue (B) light. Since one horizontal CCD 57 is provided for these image sensors, a signal having a reset signal at fc can be obtained. Therefore, conventionally, one signal obtained by adding these signals is the fifth signal.
As shown in Figure (d), reset noise occurred at the fc position.

Conventionally, this reset noise could not be removed even through a filter. However, in this embodiment, the output signals are converted into digital signals before being added, so
This reset noise can be eliminated.

FIG. 4 shows a configuration diagram when the signal processing method of the present invention is applied to a three-lens color camera. The difference from the embodiment of FIG. 3 is that the image sensors 41, 42 and 43 each have two outputs 41 and 42, 43 and 44, and 45 and 46.

Further, in this embodiment, R and G are treated as the same signal as shown in FIG. Even when two output sections 61.62 and 63.64 are provided for one image sensor in this way, conventionally, a signal with a data rate of 2fc has reset noise at the fc position. It was difficult to remove it easily even with a filter. However, in this embodiment, since the signal is converted into a digital signal, this reset noise can be removed.

FIG. 7 is a diagram showing the state of reset noise in the embodiment of FIG. 4 in the case of a data rate of 3fc in which R, G, and B signals are treated independently. Even in this case, reset noise appears at the fc position. but,
If the signal processing method of the present invention is used, these signals are converted into digital signals, so this reset noise can be easily removed.

The other operations are the same as those in the embodiment shown in FIG. 3, so their explanation will be omitted.

In the above embodiments, a three-lens type camera has been described, but it goes without saying that the present invention can also be applied to a two-lens type camera.

[Effects of the Invention] As described above, the signal processing method of the present invention converts the output signal from the solid-state imaging device into a digital signal and then converts it into an analog signal at a predetermined data rate.

Therefore, a good video signal without reset noise etc. can be obtained. In particular, the signal processing method of the present invention can bring great effects to the field of signal processing for high-definition TVs, cameras, and the like.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a signal processing circuit which is an embodiment of the signal processing method of the present invention. Fig. 2 is a block diagram of a signal processing circuit which shows another embodiment of the signal processing scheme of the present invention. 4 is a configuration diagram of a signal processing circuit in a three-lens color camera which is another embodiment of the signal processing method of the present invention; FIG. 5 is a diagram showing the signal addition situation in the embodiment of FIG. 3; 6 and 7 are diagrams showing the state of signal addition in the embodiment of FIG. 4, FIGS. 8 and 9 are plan views of a conventional solid-state imaging device, and FIG. 10 is a conventional diagram of the embodiment of FIG. FIG. 11 is a diagram showing the signal addition situation in the conventional example of FIG. 9. FIGS. 12(a) and (b) are the conventional example of FIG. 8 and the conventional example of FIG. 9, respectively. FIG. 2 is a diagram showing a reset noise situation in a conventional example. 11.12.13...Horizontal CCD output section 14.15
,16,34,35.36.41゜42.43.44,
45, 46°...Analog-digital conversion circuit (means) 17.3
7.47... Rearrangement circuit (means) 18.38.48.
...Digital to analog conversion circuit (means) Patent attorney Hidekazu Fuyoshi Figure 1 Figure 2 Figure 3 Figure 4 2,000c, Me Figure 6 Frequency - Figure 7 Figure 8 Figure 9 Figure 1 /2・fc e Frequency - 173・rc 1/2・rc fc Frequency Figure 12

Claims (3)

[Claims] (1) a plurality of light receiving and accumulating means arranged two-dimensionally on a semiconductor substrate; a vertical transfer CCD and a horizontal transfer CCD for transferring signal charges accumulated in the light receiving and accumulating means; In the solid-state imaging device, the solid-state imaging device includes n output means (n≧2) for converting the signal charge into a voltage signal with a data rate fc/n. The voltage signal is converted into n signals through a digital conversion means, and the n digital signals are rearranged into a predetermined number of digital signals through a rearrangement means. A signal processing method characterized by converting several digital signals into one analog signal at a data rate fc. (2) A signal according to claim 1, characterized in that adjustment means is provided between the analog-to-digital conversion means and the rearrangement means, thereby adjusting the offset and gain of the n digital signals to predetermined values. Processing method. (3) In a three-frame color camera equipped with three of the solid-state imaging devices, 3n of the analog-to-digital conversion means are provided, and the 3n digital signals obtained by these are converted into a predetermined number of digital signals through the re-arranging means. After rearranging into a digital signal,
2. The signal processing method according to claim 1, wherein said digital-to-analog conversion means converts said predetermined number of digital signals into one analog luminance signal by performing digital-to-analog conversion at a data rate of 2fc or 3fc.