JPH03112151A - Active layer stacked element - Google Patents

Abstract

PURPOSE:To reduce a contact resistance by forming a contact hole in an insulting film on source, drain and gate of a lower layer transistor, and then forming a columnar electrode made of first metal and an interconnection made of second metal. CONSTITUTION:After an element isolating oxide film 2 is formed on a silicon substrate 1, a lower layer transistor formed of a drain 5, a gate 6 and a source 7 and an upper layer transistor formed of a drain 5A, a gate 6A and a source 7A are formed. Then, a first contact hole is formed in oxide films 4, 3 on the source 7, the drain 5 and the gate 6 of the lower transistor, and a columnar electrode 8 made of a tungsten layer is formed in the first hole. Then, after an oxide film 9 is deposited on the whole surface, a second contact hole is so formed as to expose the top of the electrode 8. Thereafter, an interconnection 10 made of aluminum is buried in the second hole.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an active layer stacked device, and particularly to the structure of electrode wiring.

[Conventional technology]

Conventionally, the formation of each electrode on the lower transistor of a 5OI (semiconductor-on-insulator) I element having a two-layer active layer structure has been carried out as follows. FIG. 2 is a schematic cross-sectional view of an active layer laminated device produced by a conventional technique.

First, a lower transistor consisting of a drain 5, a source 7, and a gate 6 is formed on a silicon substrate 1, and then a first oxide 1113 is formed on the entire surface. Next, a silicon film is formed on this first oxide I3!3, and an upper layer transistor consisting of a drain 5A, a source 7A, and a gate 6A is formed on this silicon film, and then a second oxide film 4 is formed on the entire surface. .

Next, contact holes are formed in the second and first oxide films 4, 3 on the gate 6, drain 5, and source 7 of the lower transistor by dry etching, and tungsten is filled into the holes by selective CVD to form a columnar shape. An electrode 8A is formed. After that, a tungsten film is further deposited to surround the contact hole and connect the pedestal 1 to the columnar electrode 8A.
Shape 1. Finally, after depositing a third oxide film 7 on the entire surface and forming a contact hole in the third oxide M9 on the pedestal 11, aluminum is deposited and patterned to form wiring 10A between elements. was.

[Problem to be solved by the invention]

However, in the conventional active layer stacked device described above, the gate 6, drain 5, and source 7 in the lower layer transistor are
Between the wiring 10A made of silicon and aluminum at the position, there is silicon and a columnar type @8A, a columnar electrode 8A and a pedestal 11.
There are also interfaces between the pedestal 11 and the wiring 10A, and if the interface condition is poor, the contact resistance at each electrode of the lower transistor increases.

Further, the contact area between the pedestal 11 made of tungsten and the wiring 10A made of aluminum is small, and therefore there is a problem that the contact resistance at each electrode of the lower layer transistor increases more and more.

[Means to solve the problem]

The active layer stacked device of the present invention includes a lower transistor including a source and a drain formed on the surface of a semiconductor substrate, and a gate formed on the semiconductor substrate with a gate insulating film interposed therebetween;
a first insulating film formed on the lower transistor;
An upper layer transistor consisting of a source and a drain formed in a semiconductor film on this first insulating film, and a gate formed on the semiconductor film with a gate insulating film interposed therebetween; a third insulating film formed on the second insulating film, and a first insulating film formed on the second and first insulating films on the source, drain, and gate of the lower transistor. a contact hole, a columnar electrode made of a first metal buried in the first contact hole, and a columnar electrode formed in the third and second insulating films so as to expose an upper part of the columnar electrode. The contact hole is formed to include a second contact hole and a wiring made of a second metal buried in the second contact hole.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. In this embodiment, a silicon film is used as the semiconductor film, a silicon oxide film is used as the insulating film, a silicon substrate is used as the semiconductor substrate, aluminum is used as the wiring material, and tungsten is used as the columnar metal buried in the contact hole.

FIG. 1 is a schematic sectional view of an embodiment of the present invention. The manufacturing steps will be explained below in order.

First, an element isolation oxide film 2 is formed on a silicon substrate 1, and then a gate 6 made of polycrystalline silicon is formed via the gate oxide film, and then impurities are introduced to form a lower layer transistor consisting of a drain 5 and a source 7. Form. Next, a first oxide film 3 made of SiO2 or the like is formed over the entire surface. Next, a polycrystalline silicon film is formed on this first oxide film 3, and then a single crystal silicon film is formed by a method such as laser annealing, and a gate 6A made of polycrystalline silicon is placed on top of the polycrystalline silicon film via a gate oxide film. Then, impurities are introduced into the silicon film to form a drain 5A and a source 7A to form an upper layer transistor. Next, the entire surface is covered with a second oxide film 4.

Next, first contact holes are formed in the second and first oxide films 4, 3 at respective electrode positions on the gate 6, drain 5, and source 7 of the lower transistor by dry etching, and then H2 is applied as a carrier gas. WF with a mixing ratio of 1:1
CVD growth of tungsten is performed using a mixed gas of 6 and SiH4 at a temperature of 300°C. Under this condition, tungsten is deposited only on the silicon film and not on the silicon oxide film, and as a result, the columnar electrode 8 made of the tungsten layer is formed only in the contact hole.

Next, after depositing a third oxide film 9 on the entire surface, a second contact hole is formed by dry etching so as to expose the upper part of the columnar electrode 8. At this time, the dry etching exposes the upper surface and part of the side surfaces of the columnar electrode 8, and also exposes the gate 6, drain 5, and source 7 of the lower layer transistor.
Do this to a depth that does not expose the silicon at the location. Finally, aluminum is deposited and the aluminum film is patterned to fill the mask margin with the columnar electrodes 8, thereby forming interconnections 10 between elements.

As described above, according to this embodiment, only the interface between silicon, the columnar electrode 8, and the wiring 10 exists between the wiring 10 made of silicon and aluminum at the gate 6, drain 5, and source 7 positions in the lower transistor. Since the interface between the columnar electrode 8A and the pedestal 11, which existed conventionally, does not exist, the contact resistance at each electrode of the lower layer transistor is reduced accordingly. In addition, since the wiring 10 made of aluminum is in contact with a part of the upper surface and side surface of the columnar electrode 8 made of tungsten, the contact area between the wiring 10 and the columnar electrode 8 is larger than in the past. The contact at each electrode of the transistor becomes increasingly poor.

〔Effect of the invention〕

As explained above, in the present invention, after contact holes are formed in the insulating film on the source, drain, and gate of the lower transistor, a columnar electrode made of the first metal is formed in the contact hole, and then the columnar electrode By forming the wiring made of the second metal that connects to the upper surface and side surface of the upper part of the electrode, an active layer stacked element with lower contact resistance of each electrode of the lower layer transistor can be obtained.

[Brief explanation of drawings]

FIG. 1 is a schematic sectional view of an embodiment of the present invention, and FIG. 2 is a schematic sectional view of a conventional example. DESCRIPTION OF SYMBOLS 1...Silicon substrate, 2...Element intervening oxide film, 3.
...First oxide film, 4...Second oxide film, 5,5A.
...Drain, 6.6A...Gate, 7,7A...
Source, 8.8A... Column electrode, 9... Third oxide film, 10... Wiring.

Claims (1)

[Claims] a lower layer transistor consisting of a source and a drain formed on the surface of a semiconductor substrate, and a gate formed on the semiconductor substrate with a gate insulating film interposed therebetween; a first insulating film formed on the lower transistor; an upper layer transistor consisting of a source and a drain formed in a semiconductor film on an insulating film, and a gate formed on the semiconductor film with a gate insulating film interposed therebetween; and a second insulator formed on the entire surface including this upper layer transistor. a third insulating film formed on the second insulating film, and a first contact hole formed in the second and first insulating films on the source, drain, and gate of the lower transistor. a columnar electrode made of a first metal buried in the first contact hole; and a second columnar electrode formed in the third and second insulating films so as to expose the upper part of the columnar electrode. contact hole,
and a wiring made of a second metal buried in the second contact hole.