JPH03109762A - Gate protective circuit device for field-effect transistor - Google Patents

Abstract

PURPOSE:To enhance protection effect for a gate of a field effect transistor by inserting a protection resistor between the gate of the field effect transistor and the input terminal. CONSTITUTION:Protective resistors R1 and R2 are inserted in series between a gate 4 of a field effect transistor and the input terminal Ti. Thus, by providing a plurality of protective resistors and enabling impurity concentrations of resistance layers for them differ mutually, a current-limiting function is given to the protective resistor consisting of a resistance layer with the lower impurity concentration and a current shunting function is given to a protective diode which is available with the protective resistor consisting of a resistance layer with a higher impurity concentration, thus enhancing protection effect while maintaining the current limiting performance and current shunting performance to be given to the protective circuit device.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a method for incorporating a field-effect transistor into an integrated circuit device together with a field-effect transistor in order to protect the gate of the field-effect transistor from overvoltage caused by static electricity or the like that enters from its input terminal. The present invention relates to a suitable gate protection circuit device.

[Conventional technology]

As is well known, field effect transistor or MOS)
In transistors, in order to lower the operating threshold as much as possible, the thickness of the oxide film under the gate needs to be thin, usually less than 1000 Å, which causes the problem that the gate is easily destroyed by overvoltage. In a field effect transistor for an input circuit that is built into an integrated circuit device and receives a signal directly from its input terminal, if a sharp pulse-like overvoltage due to the discharge of an electrostatically charged human body enters from the input terminal, the gate will close. Since damage is likely to occur, it is customary to insert an overvoltage protection circuit between the input terminal and its gate.

An overview of this prior art will be explained below with reference to FIGS. 3 and 4.

The input circuit in FIG. 3 is a well-known CMO3 inverter circuit, in which p-channel field effect transistors tp and n are connected in series between a pair of power supply potential points Vd and Vs.
It is composed of a channel field effect transistor Tr+, and an output terminal To is led out from the interconnection point of both transistors.

A protection circuit consisting of a resistor R and a pair of diodes Dd and Ds is inserted between the common gate of both transistors rp and Tn and the input terminal ti. The protection resistor R is a high resistance made of a polycrystalline silicon film or the like, and limits the current flowing into the gate when an overvoltage pulse enters.

The protection diodes Dd and O3 are built in the semiconductor region in which the transistors rp and Tn are incorporated, and when a positive overvoltage enters, the diode Dd becomes conductive and the diode D
When s breaks down and a negative overvoltage enters, diode Dd breaks down and diode D3 conducts to prevent gate breakdown by shunting current to potential points Vd and Vs of voltage a, respectively.

In the conventional example of FIG. 4, the protection diode O3 is the same as above, but the protection resistor R is composed of a resistance layer built in the semiconductor region, and the protection diode Dd is formed between this resistance layer and the semiconductor region. Since a pn junction is utilized, the protection circuit can be more easily built into a smaller chip area than in the previous prior art. The present invention also relates to a protection resistor made of such a resistance layer and a protection diode attached thereto.

Note that since the diode attached to the resistive layer is formed by a pn junction between the resistive layer and the semiconductor region, the connection point between the protective diode Dd and the protective resistor R is shown by the horizontal line in FIG. It is a diode that is so to speak distributed-connected from one end of the protection resistor R to the other end, and therefore has the advantage that it is more effective in shunting the current flowing into the gate when an overvoltage enters than the protection diode Dd shown in FIG. 3.

[Problem to be solved by the invention]

As mentioned above, if the protective resistor is a so-called diffused resistor, the ρn junction between the resistive layer and the semiconductor region can be used as a protective diode, but if the sheet resistance of the resistive layer is increased to improve current limiting performance, the protective diode becomes There is a problem that the shunt performance of the 2nd side decreases.

This is because when the impurity concentration is lowered to increase the sheet resistance of the resistance layer for the protection resistor, the voltage-current characteristics of the pn junction for the protection diode become flat, and the current capacity that can be shunted decreases. Of course, it is possible to increase the size of the resistance layer without lowering the impurity concentration, but this naturally requires a large chip area.

The present invention aims to resolve this contradiction and improve the performance of protecting the gate of a field effect transistor from overvoltage.

[Means to solve the problem]

This purpose, according to the present invention, is a gate protection circuit device for a field effect transistor, in which a semiconductor region of one conductivity type to which a power supply potential is applied to the field effect transistor is diffused with different impurity concentrations. Each consists of a resistance layer? ! A plurality of protection resistors and a plurality of protection diodes each formed by a pn junction between each resistance layer and a semiconductor region are provided, and the plurality of protection resistances are connected in series between a gate and an input terminal thereof. This is accomplished by inserting.

It should be noted that, of course, protective resistors with various resistance values can be formed by using the above-mentioned resistive layers with different impurity concentrations, but of course, the resistive layer with higher impurity concentration can form a protective resistor with a high resistance value, and the resistive layer with lower impurity concentration can form a protective resistor with a higher resistance value. It is reasonable in terms of quantity to form a protective resistor with a low resistance value using each resistor layer.

At this time, p between the resistive layer with high impurity concentration and the semiconductor region
A protection diode that uses an n-junction has higher current shunting performance, and whether to connect a high-resistance protection resistor or a low-resistance protection resistor to the input terminal side depends on the current limiting performance and current for gate protection. The decision depends on which of the shunting performance is given priority, but it is usually advantageous to give priority to the former and connect a high-resistance protection resistor to the input terminal side.

In the case of integrated circuit devices, input terminals have a connection terminal structure such as connection pads or bump electrodes, and a considerable portion of the chip area is allocated to these, so the space for them can be used effectively to connect the semiconductor underneath. It is advantageous for implementing the invention to build a resistive layer for a protective resistor or a protective diode in the region.

It should be noted that it is easiest to provide the protection diode attached to the resistance layer for the protection resistor on one side of the pair of power supply potential points to the field effect transistor, but it can of course be provided on the other side as well. In this case, it is desirable that the resistance layer be used as a low-resistance protection resistor connected to the gate side.

In implementing the present invention, it is desirable to integrate the process of forming the resistance layer for the protective resistor with the process for forming the field effect transistor, and the resistance layer with a lower impurity concentration is formed in the well of the field effect transistor. At the same time as diffusion, it is advantageous in practical terms to create a resistance layer with a higher impurity concentration at the same time as the diffusion of its source and drain layers.

[Effect]

The present invention solves the problem of impurities in the resistance layer for protective resistance. ! l Focusing on the fact that they have contradictory effects on the current limiting performance and current shunting performance of the concentration force protection circuit device, providing a plurality of protective resistors and making the impurity concentrations of their resistance layers different from each other. Therefore, the protective resistor consisting of the resistive layer with the lower impurity concentration has current limiting performance, and the protective resistor consisting of the resistive layer with the higher impurity concentration has the primary current shunting function to the accompanying protective diode. In this way, we succeeded in solving the problem by increasing the protection effect while achieving both the 11 J current limit performance and current shunting performance that should be given to the protection circuit device.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings. 1st
The figures are a sectional view, an equivalent circuit diagram, and a top view showing an embodiment of the gate protection circuit device according to the present invention together with a field effect transistor to be protected, and FIG. 2 is a top view of a different embodiment.
Portions in these figures corresponding to those in FIGS. 3 and 4 described above are given the same reference numerals.

FIG. 1(a) shows a pair of complementary field effect transistors "9"
*Semiconductor region l is an n-type semiconductor substrate in this example. or an epitaxial layer, and has a specific resistance of, for example, 2 to 10 ΩCM. From the surface of this semiconductor $I region 1, a well 2 for an n-channel field effect transistor Tn is first made of p-type, and in this embodiment, at the same time, a resistance layer 3 for protection resistor R1 is made of the same p-type. The concentration of these impurities is relatively low, about 101 atoms/cd, and the diffusion depth is, for example, 5-.

Next, gates 4 made of polycrystalline silicon or the like for field effect transistors ↑p and Tn are provided on the surfaces of the semiconductor region 1 and the well 2 through thin gate oxide films of 0.1- or less thickness, respectively. This gate 4 is not used as a part of the mask as usual, but is used as the source of the p-channel field effect transistor T9.
The drain layer 5 and the substrate connection layer 6 of the n-channel field effect transistor Tn are made of p-type, and in this embodiment, this process is used to form the resistor layer 7 for the protective resistor R2 and the resistive layer 7 for the protective resistor R1. The resistive connection layer 8 is made of the same p-type. All of these are diffused to a depth of about 0.5 mm with an impurity concentration of, for example, about 101 atoms/d.

In this example, the protective resistance $
11. ! :I? 2 to each other.

Furthermore, the source/drain layer drive of the n-channel field effect transistor Tn and the p-channel field effect transistor T
P substrate contacts 1110 are both n-type and made at the same time with the same impurity concentration and diffusion depth as above.

In FIG. 1(a), a wiring film made of aluminum or the like is simply shown by a connecting line, and the gates 4 of both field effect transistors Tp and Tn are commonly connected and connected via a wiring film 13 to a resistor for the protective resistor R2. It is connected to one end of layer 7.

In this example, the input terminal TI is a connection pad 12 formed on the oxide film ll using a metal for wiring film, and the resistance at the end of the resistance layer 3 for the protection resistor $II is connected to the connection pad 12 through its extension 12a. It is connected to the connection layer 8.

As usual, a power supply potential Vs is applied to one source/drain layer 9 and the substrate connection layer 6 of one n-channel field effect transistor, and therefore the well 2 is placed at the power supply potential Vs. Similarly, the p-channel tN effect) A power supply potential Vd is applied to one source/drain layer 5 of the transistor Tp and the substrate contact 11110, and therefore the semiconductor region 1 is placed at the power supply potential Vd.6 Protection diode D1 in the present invention and D2 are n-type semiconductor regions 1 in this example placed at this power supply potential Vd as shown.
and p-type resistance layers 3 and 7 for protection resistors R1 and R2.
are formed by pn junctions between them.

FIG. 1(b) is an equivalent circuit diagram corresponding to the integrated circuit device chip of FIG. 1(a) in which such protective resistors R1 and R2 and protective diodes DI and D2 are incorporated.

The gate protection circuit device according to the present invention includes protection resistors R1 and R2 inserted in series between the input terminal Ti and the common connection gate of the complementary field effect transistor pair rp and Tn;
It consists of protection diodes D1 and 02 connected equivalently to the power supply potential point Vd along with these protection resistors.

In this embodiment, the resistor layer 3 for the protective resistor R1 has a lower impurity concentration than the resistive layer 7 for the protective resistor R2 (therefore, the sheet resistance is high), so the protective resistor R1 is made to have a high resistance and is gated by an overvoltage pulse. The protection resistor R2 on the low resistance side mainly shares the current limiting function.However, since the impurity concentration of the corresponding resistor Ji7 is high, the accompanying protection diode D2 can take a larger forward current than the protection diode D1 attached to the protection resistor R1, so the current can be lowered to the power supply potential point V.
It mainly shares the function of dividing the flow toward d.

In addition, in order to completely protect the gate from overvoltage that can have both positive and negative polarities, a protection diode Da shown in FIG.
It is necessary to connect between the power supply potential point v3 and the gate,
Of course, instead of using a normal diode as before, it is also possible to insert a low resistance made of a resistive layer with a high impurity concentration similar to the protective resistor R2 between the protective resistor R2 and the gate and use the accompanying protective diode. I can do it. For this purpose, the p-type well 2 of the n-channel field effect transistor pair n shown in FIG.
It is advantageous to build in the resistive layer with a high concentration.

FIG. 1(C) shows an example of the diffusion pattern of the resistive layers 3 and 7. In this example, the sheet resistances of the resistive layers 3 and 7 are on the order of a few Ω/min and several tens of Ω/min, respectively. The resistance layer 3 is formed in a wide short coral shape, and the resistance layer 7 is formed in an elongated folded shape.The two resistance layers are interconnected at the overlapping part, and the end of the resistance layer 3 is formed in the extension part 12a of the connection pad 12. Parts of the ends of the resistance layer 7 are respectively connected to the wiring film 13 for the gate.

FIG. 2 shows an embodiment in which protective resistors R1 and R2 are formed under the connection pad 12. A resistive layer 3 with a low impurity concentration in a strip-like pattern for the protective resistor R1 is formed under the connection pad 12. one end is connected to the connection pad 1 through the resistance connection layer 8.
It is connected to the corner of 2. One end of the highly impurity-concentrated resistance layer 7 with an elongated folded pattern for the protection resistor R2 is overlapped with the other end of the resistor N3, and is located under the connection pad 12 except for the other end connected to the gate wiring film 13. Built into the side. Unless the connection pad is particularly small, the protection resistors R1 and R2 and their associated protection diodes can thus be fabricated on the underside, reducing the chip requirement for incorporating the gate protection circuit arrangement according to the invention. The area can be minimized.

In any of the above embodiments, the protective resistor R1 has a high resistance of several ohms, and the protective resistor R2 has a relatively low resistance of several hundred ohms, so that the current limiting function in the event of an overvoltage is protected. It is desirable that the current shunting function is mainly shared by the resistor R1 and the protective diode D2 attached to the protective resistor R2.

In the equivalent circuit of Fig. 1 (c), when a positive overvoltage pulse higher than the power supply potential Vd is applied to the input terminal Ti, the protection diodes DI and D2 conduct in the forward direction, and the gates of the field effect transistors ↑p and Tn The current flowing into the circuit is mainly limited by the protective resistor R1, and mainly by the protective diode D2.
This prevents the gate from being destroyed while diverting the flow through the gate. At this time, the protection diode Ds also breaks down and plays the role of shunting the current. When a negative overvoltage pulse lower than the power supply potential Va is applied to the input terminal ↑l, the protection diode Ds becomes conductive and the current is transferred to both protection resistances. The current is limited by R1 and R2, and the current is shunted by the protection diode D3 to prevent damage to the gate L. At this time, the protection diodes 01 and D2 are set to have a voltage of about 10 or more V, for example, based on the difference in impurity concentration of their corresponding resistance layers.
.

The latter has a breakdown voltage about half that, but since a high-resistance protection resistor R1 is inserted on the input terminal TI side, both protection diodes D1 and D2 break down almost simultaneously and serve to shunt the current. The gate withstand voltage is normally about 10-odd V, but with the present invention, the overvoltage withstand voltage has been reduced (total of 20 V).
It can be improved to 0V.

〔Effect of the invention〕

As explained above, in the present invention, in order to protect the gate of the field effect transistor, the resistance layer of the other conductivity type is diffused with different impurity concentrations in the semiconductor 6N region of one conductivity type to which the power supply potential for the field effect transistor is applied. and a plurality of protection diodes each formed by a put+J combination between each resistance layer and a semiconductor area, and these protection resistances are connected to the gate of the field edge transistor. By inserting the protective diode between the resistor layer and its input terminal in a row, the current capacity of the protective diode formed along with the resistive layer with the higher impurity concentration during conduction is increased, and this protective diode is protected against overvoltage intrusion. The current shunting performance and the current shunting performance are mainly assigned to the protection resistor, which is composed of a resistance layer with a lower impurity concentration, and the current shunting function for the current C that flows into the gate. By achieving both of these, the protection effect for the gate of the field effect transistor can be significantly increased compared to the conventional method.

[Brief explanation of drawings]

1 and 2 relate to the present invention; FIG. 1 is a cross-sectional view showing an embodiment of a gate protection circuit device according to the present invention together with a field effect transistor as a protection target; FIG. 2 is an equivalent circuit diagram and a top view; FIG. 4 is a top view of a different embodiment of the invention. 3 and 4 are equivalent circuit diagrams of different conventional gate protection circuits, respectively. In these figures,
1: Semiconductor region, 2: Well for field effect transistor,
3: resistance layer, 4: gate, 5: source/drain layer of field effect transistor, substrate connection layer of SZI field effect transistor, 7: resistance layer, 8: resistance connection layer, 9:
Source/drain layer of field effect transistor, 10: Substrate connection layer of field effect transistor, ll: Oxide film, 12: Connection pad for input terminal, 12a: Extension of connection pad, 13+resistance wiring film, Dp, Ds: Conventional protection diode, Dl, D2 + protection diode according to the present invention, R: conventional protection resistor, R1, R2: protection resistor, T
it input terminal, To+ output terminal, Tn: n-channel field effect transistor, Tp: p-channel field effect transistor, Fig. 1

Claims (1)

[Claims] A plurality of protective resistors each consisting of a resistor layer of the other conductivity type diffused with different impurity concentrations in a semiconductor region of one conductivity type to which a power supply potential is applied to the field effect transistor; A gate protection circuit for a field effect transistor, comprising a plurality of protection diodes each formed by a pn junction between the two, and a plurality of protection resistors inserted in series between the gate of the field effect transistor and its input terminal. Device.