JPH03102917A - A/d converter - Google Patents

Abstract

PURPOSE:To facilitate the setting of an expected value for test decision and to simplify and to speed up the test by providing a D/A converter section converting a digital output signal of an A/D converter section into an analog signal and a test signal input terminal or the like. CONSTITUTION:In the case of conducting the test of an A/D converter 1, a digital signal Dout (expected value) outputted from an A/D converter section 2 is inputted to a D/A converter section 3 with a test signal from a test signal input terminal 7. Then the conversion section 3 converts the signal Dout into an analog signal and an analog signal Tout is outputted from a test output terminal 8. That is, since the expected value to test the converter 1 is converted into the signal Tout by the test signal, it is possible to conduct the test with the correspondence of nearly 1:1 of input and output and the expected value for test decision is easily set. In the case of conducting the AC test, since the output is an analog signal, the timing and the calculation are facilitated and the test time is reduced. Thus, the simplified and quickened test is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an A/D converter, and particularly to an 8/D converter that outputs a test signal for confirming operation.

In recent years, in analog integrated circuits, A/D converters have become higher in resolution and are being used in a wider range of applications. Therefore, A/D converters are tested to see if they have predetermined characteristics at the time of production, and there is a demand for simpler and faster testing methods.

[Prior Art] In general, an A/D converter converts the instantaneous value (sample value) of a continuously changing analog quantity into a discontinuous digital quantity, and the digital quantity is a quantized and encoded individual value. Analog quantities are approximated by sample values. Conventionally, when testing this A/D converter, a preset analog signal is input to the A/D converter, and this analog input signal is matched with a digital output code (individual encoded sample values). This is done by comparing the digital output code with a predetermined digital expected value.

In addition, when performing an AC test of an A/D converter, when comparing the digital output code and the digital expected value, the output digital pattern is captured at a predetermined timing,
Predetermined calculations (eg frequency, voltage) were performed.

[Problem to be Solved by the Invention] However, since it is difficult to judge the error between the digital output code of the A/D converter and the sample value of the analog input signal, it is difficult to determine the error between the digital output code of the A/D converter and the sample value of the analog input signal. There is a problem that setting the value is difficult.

Furthermore, when performing an AC test, there is a problem in that the timing and calculation for acquiring the digital pattern of the A/D converter are difficult, and the test takes time.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide an A/D converter that can simplify and speed up testing.

(Means for Solving the Problems) FIG. 1 is a diagram illustrating the principle of the present invention. In the figure, 1 is A/D
The converter includes an A/D converter 2 and a D/A converter 3. The A/D converter 2 converts an analog input signal AIM from an input terminal 4 into a digital signal using a clock CLK of a predetermined frequency from a clock terminal 5, and outputs a signal D from an output terminal 6. Outputs 0. On the other hand, the D/A converter 3
Digital output signal D of A/D converter 2. Convert ut into an analog signal 'out.

The A/D converter 1 also has a test signal input terminal 7 and a D
A test output terminal 8 from the /A converter 3 is provided. The digital output signal D of the A/D converter 2 is generated by a predetermined test signal of the test signal input terminal 7. ut to D/A converter 3
input. On the other hand, the analog signal from the D/A converter 3 is lower than the test output terminal 8. , t.

[Effect]

As shown in FIG. 1, when the test is not performed, the A/D converter 2 converts the analog signal AIN from the input pane 4 into a digital signal using the clock CLK, and outputs the digital signal D from the output terminal 6. , t. On the other hand, when testing the A/D converter 1, the digital signal D (expected value) output from the A/D converter 2 is sent to the D/A converter by the test signal from the test signal input terminal 7. 3.

Out Then, the D/A converter 3 receives the digital signal D. , , are converted into analog signals, and a real analog signal T is obtained from the test output pane 8. Output ut.

In this way, the expected value (
Digital signal D for test judgment. Ut) is converted into an analog signal T by the test signal. , , , it is possible to test with an approximately one-to-one correspondence between input and output, and it is possible to easily set a time limit for test judgment.

Further, when performing an AC test, since the output is an analog signal, timing and calculation are easy, and the test time is shortened.

〔Example〕

FIG. 2 shows a circuit diagram of an embodiment of the present invention. In this embodiment, a case is shown in which the A/D converter outputs a digital signal in 3 bits. In FIG. 2, the analog signal AIN from the input terminal 4 is connected to each converter CP.
It is input to the positive input terminals of CP1 to CP3. Further, the outputs of the comparators CP1 to CP3 are inputted to the D input terminals of the flip-flops FF1 to FF3, respectively. A clock of a predetermined frequency is input from the clock terminal 5 to the clock CLK terminal of each of the Norip 7 lobes FFI to FF3, and each Q output terminal is connected to the output terminal 6 to output digital signals DOut1, Do.
ut 2" out 3 digital patterns are output, respectively.

On the other hand, a resistor R is connected between the first power source Vo and the second power source GND.
＋． R2, R3. R4 is connected in series.

The voltages divided by the resistors R1 to R4 are supplied to the negative input terminals of the comparators CP1 to CP3, respectively, and are also supplied to the analog switches SW21 to SW23 and SW1.
1 to SW13, the signal is supplied to the positive input terminal of the switch SW3 and the operational amplifier OP1, which are configured of n-type MOS transistors.

In addition, the NAND gate circuit NAND1 receives the Q output of the flip-flop FFI, the Q output of the flip-flop FF2, and the Q output of the flip-flop FF3, and
The output controls the gate of analog switch SW11. NAND gate circuit NAND2 is flip-flop F
The Q output of F2, the σ output of flip-flop FF1, and the Q output of flip-flop FF3 are input, and the gate of analog switch SW12 is controlled by the output.

Further, the NAND gate circuit NAND3 inputs the Q output of the flip-flop FF3, the 0 output of the flip-flop F1, and the σ output of the flip-flop FF2, respectively, and controls the gate of the analog switch SWI3 with the output. Analog switches SW21 to SW23.Switch S by the test signal from input terminal 7
The gates of W3 and analog switch SW4 are controlled respectively. On the other hand, the output of the operational amplifier OP1 is fed back to the negative input terminal and becomes a test output from the test output terminal 8 via the analog switch SW4.

Here, resistors R1 to R4, comparators CP1 to CP3
The A/D converter 2 is composed of the control blocks FFI to FF3. Also, the NAND gate circuit NANDI~
NAND3, resistance R+~R4. Analog switch SW1
1 to 13 and SW21 to SW22, the D/A converter 3
Construct.

In this case, the resistors R1 to R4 are shared during A/D conversion and D/A conversion.

Next, the operation of the A/D converter 1 will be explained. First, when the A/D converter 1 operates normally without being tested, the test signal input to the test signal input terminal 7 is at a low level. At this time, analog switch SW2
1 to SW23 are in the on state, switch SW3 is in the on state,
Analog switch SW4 is in the on state. Therefore, the test output terminal 8 becomes open. Further, the comparators CP1 to CP3 are connected to the first power supply V by the resistors R1 to R4.
The divided voltage of o is inputted to the negative input terminal as a reference voltage, and compared with the analog input signal A■ from the input terminal 4. The outputs of the comparators CP1 to CP3 are input to the D input terminals of the flip-flops FF1 to FF3, respectively, and sampled at the timing of the clock CLK from the clock terminal 5. A 3-bit digital signal D corresponding to the analog input signal is output from the Q output terminals of the flipflops FF1 to FF3. ut'〜oou
A digital pattern at t3 is output from the output pane 6.

Next, when testing the A/D converter 1, the test signal input to the test signal input terminal 7 is at a high level. At this time, analog switches SW21 to SW23 are in the on state, switch SW3 is in the off state, and analog switch 4
turns on.

Even in this case, the Noritubu float FF1-・F'3
From is a digital signal (D1~Doo, 3) Ou
t is output, but it is fed back to the analog switches SWII-SW13 via the NAND circuits NAND1-3. As a result, the first power supply V due to the low resistance R1 to R4
The divided voltage of o is selected by analog switches SW11 to SW13, that is, D/A converted. The analog signals converted by the analog switches SW11 to SW13 are the operational amplifiers OPI and ? Nalog Suitsuji SW
4 from the test output terminal 8 to the test signal T. It is output as at. That is, a digital pattern output from the A/D converter 2 is input to the D/A converter 3 during testing, and an analog signal is output from the test output terminal 8.

In this way, when testing the A/D converter 1, an analog test output signal is obtained for an analog input signal, so testing can be performed with a one-to-one correspondence between inputs and outputs. Expected values for judgment can be easily set. Furthermore, even when testing AC characteristics, the timing and calculations are easy and the test time is shortened. Furthermore, in the present invention, the O/DIM device 1 includes
Although the A converter 3 is provided, since part of its configuration is shared with the A/D converter 2, the circuit structure is not complicated.

In addition, in this embodiment, the digital pattern to be output is 3.
Although the case of bits is shown, the present invention is not limited to this. In addition, in FIG. 2, switch SW3 and analog switch SW4 are provided to prevent the test output terminal 8 from being in the output state during normal times, but if a constant output state is to be maintained during normal times, switch SW3 is provided. And the analog switch SW4 may be omitted.

(Effects of the Invention) As described above, according to the present invention, by providing the A/D converter with a D/A converter for testing, an analog test output can be obtained for an analog input signal, and a test D/A converter can be provided in the A/D converter. simplification,
It is possible to increase the speed.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention, FIG. 2 is a circuit diagram of one embodiment of the present invention. In the figure, 1 is an A/D converter, 2 is an AID conversion unit, 3 is a D/A conversion section; 4 is an input terminal, 5 is the clock terminal, 6 is the output terminal, 7 is a test signal input terminal, 8 is the test output terminal shows.

Claims (1)

[Claims] An A/D converter (2) that converts an analog input signal into a digital signal at a predetermined frequency and outputs the digital signal;
D converting the digital output signal of 2) into an analog signal
/A converter (3) and the A/A converter (3) by a predetermined test signal.
A test signal input terminal (7) for inputting the digital output signal of the D converter (2) to the D/A converter (3), and a test output for outputting the analog signal from the D/A converter (3). An A/D converter comprising: a terminal (8);