JPH03101533A - Pn clock synchronization maintaining device - Google Patents

Abstract

PURPOSE:To attain stable PN clock synchronization maintenance by using a sampling pulse generated by a differentiation pulse resulting from differentiating a local PN signal to sample the transmission PN signal of a reception base band signal. CONSTITUTION:A reception base band signal Z outputted from a frequency converter 22 includes a transmission data and a transmission side PN signal. A local PN signal S is differentiated by a differentiation circuit 51, a differentiation pulse U representing a change point of the local PN signal S is generated and multiplied with a demodulation data outputted from an adder 43 at a sampling pulse generator 52 and sampling pulses V<+>, V<-> are outputted. A sample signal W outputted from a sampling circuit 53 is integrated by an LPF 54 and fed to a VCO 40 through a changeover switch 55 as a phase detection signal X to control the phase of a PN clock Y outputted from the VCO 40. Thus, even when the phase comparison characteristic is deviated from the ideal characteristic due to the effect of the interference between other stations and multi-path, the phase of the PN clock Y is subjected to the stable synchronization maintenance.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to a PN clock synchronization maintaining device in a direct spread spectrum communication receiving device used not only in communications such as radio telephones, but also in navigation and identification systems. .

Conventional technology Spread spectrum communication has been used for communication within relatively narrow ranges such as inside buildings and factories, and for communication within relatively short ranges while moving, due to the recent social and economic development and advances in telecommunications technology. The demand for wireless equipment used over long distances is increasing.

The conventional direct spread spectrum communication system will be explained below.

FIG. 5 is a block diagram showing the basic configuration of a conventional spread spectrum communication system, and includes FIGS. 6(aHb)(c), FIGS. 7(a)(b)(c) and FIG. b)(c)
are signal waveform diagrams at each main part of FIG. 5, respectively.

In Figures 5 to 8, a data signal A to be subjected to spectrum spreading is combined with a PN signal (P
seudo No. 1se) B is generated by the PN generator 1 and multiplied by the multiplier 2 to perform spectrum spreading. In this case, the PNN signal is generated by the PN clock of the oscillator (O3C).
+1.
It is a digital signal that takes a value of -1. In this manner, a carrier wave signal E is generated by the carrier wave signal generator 3 based on the baseband signal obtained by spectrum spreading, multiplied by the multiplier 4, and transmitted by the antenna 5.

On the other hand, the received signal received by the antenna 6 is encoded with P N , which is similar to the PNN signal generated on the transmitting side.
, a signal F is generated by a local PN generator 7, and is multiplied by the received signal by a multiplier 8 to perform PN despreading, thereby performing demodulation by removing the PNN signal from the received signal <PN despreading. However, at this time, P N on the PNN signal,
, , it is necessary to synchronize the signals F, and this PN synchronization control is performed as follows. P N , , A PN signal H is generated from the local PN generator 7 for the signal F, and after being multiplied with the received signal by multipliers 9 and 10 and despread, the envelope detector 11 .12 to perform envelope detection, and furthermore, a low pass filter (hereinafter referred to as LP
When smoothed by F > 13.14, the PN of the received signal is
Correlation output characteristics J and K as shown in FIGS. 8(a) and (b) are obtained as correlation outputs during despreading using + signals and PN− signals.
is obtained. These correlation output characteristics J.

When the correlation output at K is added or subtracted by the adder 15, a composite correlation output characteristic as shown in FIG. 8(C) is obtained as a composite correlation output. After filtering this composite correlation output with a loop filter (LF) 16, it is transferred to a voltage controlled g1 oscillator (hereinafter referred to as ■CO) 17, which is a PN clock oscillator.
is used as a control signal to control the phase of the PN clock C'. As a result, the PN of the local PN generator 7,...
The signal F operates to track and synchronize with the PNN signal included in the received signal, and the point LQ'''C''P N , where the signal F intersects the horizontal axis between the maximum and minimum values of the composite correlation output characteristic ,
The generation of signal F is stabilized.

Furthermore, the signal from which the PN signal has been removed by the PN despreading in the multiplier 8 is input to the two-phase PSK demodulator 19, and the carrier wave signal E extracted by the carrier wave extractor 18 is used to generate the data signal A. is demodulated.

However, in the above conventional configuration, the despreading demodulator and P
The signal processing in the N synchronization control section is based on the carrier wave E of the high frequency signal.
The signal processing includes

Such high-frequency signal processing has had the problem that it is difficult to incorporate the circuit into an LSI, and therefore it is difficult to make the device more compact and cost-effective.

Therefore, a receiving apparatus using a direct spread spectrum communication system as shown in FIG. 9 has been proposed which is improved in this respect. This will be explained below. In FIG. 9, 21 is an IP other signal input terminal obtained from a transmission signal in direct spread spectrum communication, 22.23 is a first and second frequency converter consisting of a multiplier connected to the IF signal input terminal 21,
24 is a local oscillator that generates a signal with almost the same frequency as that of the IP and other signals; the output of the local oscillator 24 is directly input to the first frequency converter 22, and the output of the local oscillator 24 is input directly to the second frequency converter 23. The output is inputted through the filter 25, and signals of the I component of the in-phase component of the IP signal and the Q component of the orthogonal component are output, respectively. 26 to 28 are first to third multipliers connected to the output end of the first frequency converter 22, and 29 to 31 are fourth to sixth multipliers connected to the output end of the second frequency converter 23. The local PN signal of the local PN generator 32 is input to the first and fourth multipliers 26, 29, and the second and fifth multipliers 27, .
A local PN generator signal is input to the third and sixth multipliers 28 and 30, and the local PN signals of the first and second multipliers are input to the third and sixth multipliers 28 and 31, which operate to perform data demodulation and PN phase comparison. Further, the output ends of the second and third multipliers 27.28 are connected to the adder 37 via LPFs 33 and 34, respectively, and the output ends of the fifth and sixth multipliers 30.31 are connected to LPFs 35 and 36, respectively. connected to adder 38 via
The PN phase comparison and synthesis correlation signals IO and Qo output from these adders 37 and 38 are input to an arithmetic circuit 39.

In the arithmetic circuit 39, a PN phase comparison correlation value C(φ) for phase comparison determined by the phase difference φ between the transmitted PN signal and the local PN signal, and an IP other signal local The phase difference θ between the oscillator 24 and the local signal is calculated. This PN phase comparison correlation value C(φ) is the VC that drives the local PN generator 32.
The phase of the PN clock output from the VCO 40 is controlled so as to synchronize the transmitted PN signal and the local PN signal.
The phase of the local signal is controlled so as to be synchronized with the local signal of the IP multiplied signal local oscillator 24. Further, the first and fourth multipliers 26 and 29 are connected to an adder 43 via LPFs 41 and 42, respectively,
Demodulated data is obtained from the adder 43.

In the above configuration, the first and second frequency converters 22, 2
3. The local oscillator 24 and the i-shifter 25 constitute a quasi-synchronous detection section M, the first to sixth multipliers 26 to 31 constitute a despreading demodulation section N, the local PN generator 32, and the LPF
33 to 36, adder 37, 38, arithmetic circuit 39 and V
CO40 constitutes PN synchronization control unit P, and LPF41,4
2 and the adder 43 constitute a data demodulation section R.

Next, its operation will be explained. Now, the IP multiplied signal is expressed by the following equation.

A (t) sin (W, t+θ+)”
""(1) Also, the first and second frequency converters 22.23
The quasi-synchronous detection signal of the local oscillator 24 input to I
The flaw signal is a signal with almost the same frequency, and (W, -
Assuming that it has a frequency of Δw t ), the quasi-synchronous detection signal can be expressed by the following equation.

Bcos (Wit−Δwt+θo) --−
−−−(2) Bsin (W, −Δwt+θo
) −・−・−・(3) Therefore, the in-phase component I ft output from the first and second frequency converters 22.23
) and the orthogonal component Q (t) are expressed as follows.

・・・・・・(4) Qm=A−J÷l! Lcos (Δwt+θ1−θ0
)...(5) The signals of I it) and Q(t) do not contain the high frequency component of the TF signal, but the beat component of the difference between the IF flaw signal and the quasi-synchronous detection signal is included. Contains “ζ” and sends P
An N signal is also included. This I (t), Qft) is multiplied by two local PN signals of leading phase and lagging phase, and P
When N despreading modulation is applied and the differential output is taken, PN phase comparison combined correlation signals IQ and Qo as shown in the following equations are obtained.

Io = C(φ) sinθ ・・・・・・
(6) Qo = C(φ) cosθ...
...(7) Here, θ=Δwt+θ1−θ0 In the above equations (6) and (7), φ is the phase difference between the transmitted PN signal and the local PN signal, and C(φ) is the phase comparison determined by this phase difference φ. This is the PN phase comparison correlation value for , and its size is the same as the phase comparison characteristic shown by the solid line in FIG. IO and Qo are obtained as beat signals with an angular velocity θ formed by the local signal of the IP multiplied signal local oscillator 24, and the amplitude thereof is C(φ).

If C(φ) and θ are determined from this relationship, as shown in FIG. 11, the following is obtained. This calculation is performed in the calculation circuit 39 by inputting the PN phase comparison and synthesis correlation signals Io and Qo output from the adders 37 and 38.

The VCO 40 receives the PN phase comparison correlation value C(
φ) is input, the phase of the PN clock is controlled so that C(φ)=0, and the local PN generator 32 receives this P
A local PN signal and local PN signals of lagging phase and leading phase are generated in synchronization with the N clock. At the same time, the local oscillator 24 is inputted with a signal having a phase difference θ from the IF flaw signal from the arithmetic circuit 39 and the local signal of the local oscillator 24, and the frequency (W) of the quasi-synchronous detection signal is set to −Δwt.
is controlled so that t1 is equal to the IF flaw signal frequency Wi t.
It is done. This quasi-synchronous detection enables baseband signal processing, and eventually synchronous detection will be performed using the IP multiplied signal carrier wave. Therefore, the IF flaw signal high frequency component is not included after the despreading demodulation section N, and the signal processing in the carrier domain is reduced, making it easy to integrate the circuit into an LSI. Fourth
can be obtained by simply adding the multipliers 26 and 29.

Problems to be Solved by the Invention However, in the conventional configuration described above, due to interference between other stations and multipath, the phase comparison characteristic of C(φ) deviates from the ideal solid curve as shown in FIG. The curve tends to deviate as shown by the broken line, and even if the PN phase comparison correlation value C(φ) is controlled to 0, the position of the received PN signal and the local PN signal output from the local PN generator will vary. There was a problem in that the phase difference φ did not become 0, making it difficult to maintain synchronization of the PN clock for synchronizing the received PN signal and the local PN signal.

The present invention solves the above-mentioned conventional problems, and makes it possible to maintain stable PN clock synchronization after acquiring PN synchronization.
The object of the present invention is to provide an N-clock synchronization holding device.

Means for Solving the Problems In order to solve the above problems, the PN clock synchronization holding device includes a sampling circuit that samples the received baseband signal of the direct spread spectrum communication method using a sampling pulse, and a local clock output from the local PN generator. It includes a differentiating circuit that differentiates a PN signal, and a sampling pulse generator that generates the sampling pulse by applying a differential pulse of the differentiating circuit to demodulated data. It is configured to control the clock phase of a clock oscillator.

Effect With the above configuration, the sampling pulse generated by the differential pulse obtained by differentiating the local PN signal changes its polarity in response to ten modulation or one modulation of the received data of the received baseband signal, and this sampling pulse generates a differential pulse that is obtained by differentiating the local PN signal. Since the transmitted PN signal of the baseband signal is sampled, the phase of the transmitted PN signal can be detected in the same way even during + modulation or 1 modulation. Moreover, P.N.
After synchronization is acquired, a PN clock synchronization system is constructed using sampling pulses, so after -1 PN synchronization, a PN clock using the correlation output characteristics of leading phase and lagging phase is configured.
There is no need to perform clock phase control, and therefore there is no shift in phase comparison characteristics due to interference between other stations, multipath, etc., and stable synchronization of the PN clock can be maintained.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a direct spread spectrum communication receiving device including a PN clock synchronization maintaining device according to an embodiment of the present invention, and parts having the same functions and effects as the conventional example are given the same reference numerals. Therefore, the explanation will be omitted.

In FIG. 1, 51 is a differential circuit, and the local PN
The local PN signal S output from the generator 32 is differentiated to output a differentiated pulse U indicating a changing point of the local PN signal S. 52 is a sampling pulse generator consisting of a multiplier, which generates a differential pulse U output from the differential circuit 51.
By multiplying by the demodulated data outputted from the adder 43, a sampling pulse ■ is obtained. 53 is a sampling circuit consisting of a multiplier, which samples the received baseband signal Z by multiplying the received baseband signal Z output from the frequency converter 22 and the sampling pulse V;
A sample signal W is output. 54 is a sampling circuit 5
3, which integrates the sample signal W output from the sampling circuit 53 and outputs the phase detection signal X.
Output. Reference numeral 55 denotes a changeover switch that switches between the arithmetic circuit 39 and the LPF 54 and connects it to the VCO 40, and when the local PN signal S output from the local PN generator 32 is synchronized with the received PN signal and within the synchronization range,
It can be switched to the PF54 side. Due to the above,
A PN clock synchronization holding section 56 is configured.

Next, the operation of the above configuration will be explained. Frequency converter 2
The received baseband signal Z output from 2 includes the transmission data and the PN signal on the transmission side, and when the transmission data is modulated by 10, the reception baseband signal Z is Z+ as shown in Fig. 2(a).
When the waveform is -modulated, the waveform is as shown in Figure 2 (b).
This results in a Z- waveform as shown in . In addition, the local PN generator 32 generates a local PN as shown in FIG. 2(C).
A signal S is output, and this local PN signal S is differentiated by a differentiating circuit 51 to generate a differentiated pulse U having a polarity as shown in FIG. 2(d) indicating a change point of the local PN signal S. This differential pulse U and the demodulated data output from the adder 43 are multiplied by the sampling pulse generator 52, and the demodulated data corresponding to the received baseband signals Z4 and 2- are used to generate the demodulated data in FIGS. ) Sampling pulses ◆ and V- are output as shown in . This is because the polarity of the differential pulse U must be controlled depending on whether the transmission data is modulated by + or - modulated.

Next, the sampling circuit 53 uses the sample signal W obtained by multiplying the received baseband signal 24'' or Z- by the sampling pulse ■4 or V- as shown in FIG. 2 (aHb) to acquire PN synchronization. When the changeover switch is later switched to the LPF54 side, the operation of controlling V C040 to maintain PN clock synchronization is shown in Figure 3 for the case of the received baseband signal Z+ when the transmitted data is modulated by 10. Refer to and explain.

When the phase of the received baseband signal 2 in FIG. 3(a) fluctuates and the sampling pulse V advances in phase with respect to the received PN signal as shown in FIG. 3(b), the sampling circuit 53 outputs The sample signal W becomes a negative output signal as shown in FIG. 3(C).

Furthermore, when the sampling pulse ■ is delayed in phase with respect to the received PN signal as shown in FIG. 3(f), the sandal signal W output from the sampling circuit 53 is
), it becomes a positive output signal.

Furthermore, as shown in FIG. 3(d), when the sampling pulse ■ is in positive phase and synchronized with the received PN signal of the received baseband signal Z, the sample signal W output from the sampling circuit 53 is As shown in FIG. 3(e), it becomes a cycle signal with positive and negative outputs.

Next, the sample signal W output from the sampling circuit 53 is integrated by the LPF 54, and is applied as the phase detection signal X to the VCO 40 through the changeover switch 55.
When controlling the phase of the PN clock Y output from the CO40, if the sample signal W is a negative output as shown in Figure 3(C), the phase detection signal As can be seen from the phase detection characteristic diagram in Figure 4,
Control is performed in the direction of delaying the phase of the sampling pulse ■, that is, in the direction of setting the phase detection signal The signal is controlled in the direction of advancing the phase of the sampling pulse V. Also, the sample signal W
When is a positive and negative cycle signal as shown in Figure 3(e),
The phase detection signal X obtained by integrating it becomes O, and since it has a positive phase, that state is maintained. In this way, the phase of the PN clock Y remains stable even if the phase comparison characteristic shown in Figure 10 deviates from the ideal one as shown by the broken line due to interference between other stations or multipath. It is something that is kept synchronous.

In addition, if the received baseband signal Z is a signal Z- when the transmission data is modulated as shown in FIG. 2(a), the sampling pulse ■- as shown in FIG. 2(f) is used as the sampling pulse ■. As a result, the sample signal W has the same polarity as in the case of ten modulation, and is phase-controlled in the same manner using the phase detection characteristics shown in FIG.

In this way, by configuring a PN clock synchronization system using the sampling pulse V, even if an interference signal is input, the phase relationship of this interference signal is not constant, so the phase detection signal X, which is an integral value, is 0. If the frequency difference between the PN clocks of other stations is Δf, the IPN
Since the phase is shifted by a clock amount and there is a high probability of inversion in units of IPN clocks, the inversion results in a reverse output, and the phase detection signal X is averaged and becomes a 0 output, and is not affected.

Effects of the Invention As described above, according to the present invention, after PN synchronization is acquired, the received baseband signal is generated from a differential pulse obtained by differentiating the local PN signal, and the received baseband signal is sampled by a narrow sampling pulse, and the obtained sample is using a signal,
PN of PN clock generator for driving local PN generator
Since the clock phase is controlled, the received PN signal and the local PN signal can be stably synchronized without being affected by interference between other stations or multipath, and high-precision PN clock synchronization can be maintained. It becomes possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a direct spread spectrum communication receiving device including a PN clock synchronization maintaining device according to an embodiment of the present invention, FIGS. 2(a) to (f), and FIGS. 3(a) to (g).
) are signal waveform diagrams at each main part to explain the operation of FIG. 1, and FIGS. 2
Figure (C) is a local PN signal waveform diagram, Figure 2 (d) is a differential pulse waveform diagram of the local PN signal, Figure 2 (e) (f
) is a sampling pulse waveform diagram when the data signal is + modulated and 1 modulated, Figure 3 (a) is a received baseband signal waveform diagram, and Figure 3 (b), (d), and (f) are leading phase and positive phase diagrams. Sampling pulse waveform diagram at time and delay phase, 3rd
Figure (C) (13) (!I+) is a sample signal waveform diagram at leading phase, positive phase, and lagging phase. Figure 4 is a phase detection characteristic diagram for PN clock phase control. Figure 5 is A block diagram showing the basic configuration of a conventional spread spectrum communication system. Figures 6 and 7 are signal waveform diagrams for each main part of Figure 5, Figure 8 is a correlation output characteristic diagram, and Figure 9 is an improved version. A block diagram of a receiving device in the direct spread spectrum communication system, FIG. 10 is a phase comparison characteristic diagram of C(φ),
FIG. 11 is a vector diagram of C(φ). 32... Local PN generator, 40... VCO (P
N tarokku oscillator), 51... Differential circuit, 52...
sample pulse generator, 53... sampling circuit,
54... LPF, 55... Selector switch, 56...
・PN clock synchronization holding unit, S...local PN signal, U...differential pulse, ■...sampling pulse,
W...sample signal, X...phase detection signal, Y...
・PN clock, Z... Reception baseband signal.

Claims (1)

[Claims] 1. A sampling circuit that samples the received baseband signal of the direct spread spectrum communication system using a sampling pulse, a differentiation circuit that differentiates the local PN signal output from the local PN generator, and a differentiation pulse of the differentiation circuit that is used as demodulated data. and a sampling pulse generator that generates the sampling pulse by applying the sampling pulse, and the PN clock synchronization holding device is configured to control a clock phase of a PN clock oscillator for driving the local PN generator by an output signal of the sampling circuit.