JPH0292552U

JPH0292552U -

Info

Publication number: JPH0292552U
Application number: JP17126888U
Authority: JP
Priority date: 1988-12-28
Filing date: 1988-12-28
Publication date: 1990-07-23

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例に係る受信機を示す
外観図、第２図は本実施例の受信機内部の回路構
成を示すブロツク図、第３図は本実施例で採用し
た送信信号フオーマツトを示す図、第４図はデー
タの種類と識別コードとの関係を示す図、第５図
は第２図中のＲＡＭ１３の主要内容を示す模式構
成図、第６図は本実施例の全体的な処理動作を示
すフローチヤート、第７図は第６図中の受信デー
タ取り込み処理（ステツプａ_１３）を具体的に示
すフローチヤート、第８図は第６図中のキー処理
（ステツプａ_５）を具体的に示すフローチヤート
、第９図はキー操作による表示部２の表示の切り
換わりを示す図、第１０図は本考案の他の実施例
に係る受信機内部の回路構成の一部を示すブロツ
ク図、第１１図は上記他の実施例で採用した送信
信号フオーマツトを示す図である。２……表示部、４……受信回路、５……入力同
期回路、６……ＢＣＨ誤り訂正回路、７……プリ
アンブル検出回路、８……同期コード検出回路、
９……Ｓ−Ｐ変換回路、１０……受信タイミング
制御回路、１１……ＣＰＵ、１３……ＲＡＭ、１
４……演算回路、１５……表示バツフア、１６…
…表示ドライバ、２１……ＩＤ−ＲＯＭ、２２…
…アドレス一致検出回路、Ｋ……識別コードレジ
スタ、Ｓ……タイマレジスタ、Ｌ……受信可否フ
ラグ、Ｘ……連勝複式用のレース結果レジスタ、
Ｙ……単勝用のレース結果レジスタ、Ｚ……単勝
複式用のレース結果レジスタ、Ｒ……選択データ
レジスタ、Ｓ_１……サーチキー、Ｓ_２〜Ｓ_４……
レース結果の選択キー、Ｓ_５……レース結果以外
の選択キー。 Fig. 1 is an external view showing a receiver according to an embodiment of the present invention, Fig. 2 is a block diagram showing the internal circuit configuration of the receiver of this embodiment, and Fig. 3 is a transmission signal adopted in this embodiment. FIG. 4 is a diagram showing the relationship between data types and identification codes. FIG. 5 is a schematic configuration diagram showing the main contents of the RAM 13 in FIG. 2. FIG. 6 is an overall diagram of this embodiment. 7 is a flowchart specifically showing the received data importing process (step _a13 ) in FIG. 6, and FIG. 8 is a flowchart specifically showing the key processing (step _a5) in FIG. ), FIG. 9 is a diagram showing the switching of the display on the display unit 2 by key operation, and FIG. 10 is a part of the circuit configuration inside the receiver according to another embodiment of the present invention. FIG. 11 is a block diagram showing the transmission signal format adopted in the other embodiment described above. 2... Display unit, 4... Receiving circuit, 5... Input synchronization circuit, 6... BCH error correction circuit, 7... Preamble detection circuit, 8... Synchronization code detection circuit,
9...S-P conversion circuit, 10...Reception timing control circuit, 11...CPU, 13...RAM, 1
4... Arithmetic circuit, 15... Display buffer, 16...
...Display driver, 21...ID-ROM, 22...
...Address match detection circuit, K...Identification code register, S...Timer register, L...Reception availability flag, X...Race result register for consecutive wins and combinations,
Y...Race result register for single win, Z...Race result register for single win and double win, R...Selection data register, _S1 ...Search key, _S2 to _S4 ...
Selection key for race results, _S5 ... Selection key for items other than race results.

Claims

[Scope of Claim for Utility Model Registration] (1) Selection switch means for selecting a desired type of data from among multiple types of data regarding races, and storing type data indicating the type selected by the selection switch means. type data storage means; receiving means for receiving data related to the race; determining means for determining the type of data received by the receiving means; a first received data storage means for storing; a second received data storage means for storing only received data for which the determination means has determined that the type data matches the type data stored in the type data storage means; A receiver comprising display means for displaying data stored in the first and second received data storage means. (2) The display means normally displays the data stored in the second received data storage means, and displays the data stored in the first received data storage means only when a predetermined switch operation is performed. 2. The receiver according to claim 1, wherein the receiver displays data.