JPH0290382A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To improve an operation efficiency as a whole by operating asynchronously plural function modules whose maximum operation frequencies are different, and also, executing a synchronized control for a data transfer between the function modules. CONSTITUTION:A single chip microcomputer 1 incorporates a CPU module 2, a RAM module 3, a timer counter module 4, a serial input/output circuit module 5, a DMAC module 6 and a DMAC module 7. In this state, to the modules 2, 3, 4, 6 and 7, different operation clock signals phi0, phi3, phii, phi1 and phi2 are supplied through a frequency dividing circuit 11 from the output of a clock pulse generator 10 to which an external clock signal CLK1 and the modules execute an asynchronous operation. To the input/output circuit module 5, an independent clock signal CLK2 is applied and a data transfer which passes through a silicon pack plane bus 8 being an asynchronous bus is brought to synchronized control. In such a manner, the operation efficiency as a whole can be improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit in which a plurality of functional modules having different maximum operating frequencies are formed on one semiconductor substrate, and furthermore, to a semiconductor integrated circuit included in such a semiconductor integrated circuit. The present invention relates to a technique for increasing the overall operating frequency of a functional module, and relates to a technique that is effective when applied to, for example, a semiconductor integrated circuit configured in an ASIC (Application Specific Integrated Circuit) format.

[Prior art]

For ASICs, which are semiconductor integrated circuits for specific applications, function modules designed in the past are registered in a library as standard cells from the perspective of reusing design assets, and the registered information can be used later as needed. It is possible to adopt a standard cell method, which can be used to construct semiconductor integrated circuits for specific applications. For example, when a single-chip microcomputer is constructed on one semiconductor substrate using such a method, peripheral circuits such as serial input/output circuits, timers/counters, and various controllers are installed as standard in addition to the central processing unit, depending on the required specifications. Select from cells. Conventionally, various functional modules adopted in this manner are combined with a synchronous bus on one semiconductor substrate and integrated into one chip.

In addition, AS consists of various functional modules connected via a synchronous bus.
An example of a document describing an IC-type semiconductor integrated circuit is Nikkei Electronics J (July 13, 1987 issue), pages 90 and 91, published by Nikkei McGraw-Hill.

[Problem to be solved by the invention]

Incidentally, the maximum operating frequency of various functional modules prepared in advance as standard cells for ASICs often differs depending on differences in their circuit configurations, functions, layout rules, and the like. Therefore, when a semiconductor integrated circuit for a specific application is constructed using an ASIC method such as a standard cell, the maximum operating frequencies of various functional modules included in the semiconductor integrated circuit may differ from each other.

At this time, if multiple functional modules with different maximum operating frequencies are combined using a synchronous bus and integrated into a single chip as in the past, the maximum operating frequency of this semiconductor integrated circuit will be the maximum operating frequency of the functional modules mounted on it. The inventor has discovered that there is a problem in that the operating speed of the functional module that is originally capable of high-speed operation is sacrificed, and the operating efficiency of the entire semiconductor integrated circuit is reduced. discovered.

An object of the present invention is to set the operating frequency of a semiconductor integrated circuit formed on one semiconductor substrate including a plurality of functional modules having different maximum operating frequencies to the maximum operating frequency of the various functional modules included in the semiconductor integrated circuit. It is an object of the present invention to provide a semiconductor integrated circuit that can prevent the situation of being limited by the lowest functional module and improve the overall operating efficiency.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a plurality of functional modules with different maximum operating frequencies are connected to an asynchronous bus and are operated asynchronously based on operating clock signals with different frequencies, and the functional modules operated asynchronously are used for data transfer via the asynchronous bus. A semiconductor integrated circuit made of a single chip is constructed by performing synchronization control of two chips.The above synchronization control is a control for exchanging data while checking the status of the other party using handshake signals. or a control operation that allows the bus access cycle to be extended based on the sampling result of the wait request.

At this time, in order to increase data transfer efficiency between a plurality of functional modules having the same operating clock frequency, it is preferable to connect these functional modules by a synchronous bus.

In addition, operating clock signals for functional modules that operate at different operating clock frequencies are formed by a clock pulse generator that uses the same clock source and a frequency dividing circuit that divides the output of this clock pulse generator at a required division ratio. However, in this case, it is desirable to include the frequency dividing circuit in each functional module in order to reduce the number of clock signal lines. Further, it is also possible to provide an operating clock signal to a specific functional module among the functional modules operated at different operating clock frequencies via a clock source different from the clock source of the clock pulse generator.

[For production]

According to the above means, a plurality of functional modules having different maximum operating frequencies included in a semiconductor integrated circuit formed on one chip can operate asynchronously based on operating clock signals having mutually different frequencies. Data transfer timing and access timing between operated functional modules are adjusted by synchronization control such as handshake control and wait cycle insertion. As a result, the maximum operating frequency of a semiconductor integrated circuit that includes a plurality of functional modules and is integrated into one chip is not limited by the functional module with the lowest maximum operating frequency among the functional modules built into it. This results in improved overall operating efficiency in the circuit.

[Embodiment] FIG. 1 shows a single-chip microcomputer that is an embodiment of the present invention. The single-chip microcomputer 1 shown in the figure uses, as necessary, standard cells for configuring functional modules that have been designed in the past and is registered as a library, although this is not particularly limited, to configure a semiconductor integrated circuit for a specific application. It is an ASIC type semiconductor integrated circuit constructed using a standard cell method using the building block method or the polycell method, and is formed on a single semiconductor substrate such as silicon using known semiconductor integrated circuit manufacturing technology. .

The single-chip microcomputer 1 shown in FIG.
(Central Processing Unit) module 2, RAM (Random Access Memory) module 3 used as the work area of this CPtJ module 2, timer/counter module 4, serial input/output circuit module 5, and the above-mentioned CPU. module 2
DMAC for high-speed data transfer by reducing the burden on
It incorporates functional modules such as a (direct memory access controller) module 6 and a DMAC module 7. These functional modules are coupled to an address bus ABUS, a data bus DBUS, and a control bus CBUS, which constitute a silicon backplane bus 8 as an internal asynchronous bus.

Although not shown, the single-chip microcomputer 1 of this embodiment includes a memory management unit that converts the logical address given to the address bus ABUS into a physical address for the external memory space, and this memory management unit. An address output buffer for giving the physical address output from the unit to the outside of the single-chip microcomputer 1, and a data bus DBUS to the single-chip microcomputer 1.
A data input/output buffer for interfacing with the outside of the single-chip microcomputer 1, and a control bus buffer for interfacing a predetermined signal line included in the control bus CBUS with the outside of the single-chip microcomputer 1 are provided.

In this embodiment, the CPU module 2, RAM module 3, timer/counter module 4, serial input/output circuit module 5, DMAC module 6, and DM
It is assumed that the AC modules 7 each have a circuit configuration that operates in synchronization with a clock signal, and the maximum operating frequencies at which they can operate normally are different. CPU module 2
, DMAC module 6, I) MAC module 7, R
The AM module 3 and the timer/counter module 4 receive an operating clock signal φ of a necessary frequency within a range below their respective maximum operating frequencies. , φ1. φ2. φ3. φj is supplied individually. These operating clock signals φ. , φ1. φ2
．． φ3. Although not particularly limited, φi have different frequencies, and an external clock signal CLKI such as a system clock signal is connected to an external crystal terminal EXTA.
The signal is output from a frequency dividing circuit 11 that sequentially divides the output of the clock pulse generator 10 received at L in accordance with a predetermined frequency division ratio. This frequency dividing circuit 11 is constituted by a counter having a predetermined number of bits and a selector for selecting the output of this counter, although it is not particularly limited, and obtains a frequency that is a fractional multiple smaller than the output frequency of the clock pulse generator 1o. The serial input/output circuit module 5 receives bit-serial data RXD synchronized with transfer lock RXC, and transmits data TXD bit-serial in synchronization with transfer lock TxC, although this is not particularly limited. The data transfer rate at this time is transfer lock RxC,
Since it is specified by TXC, the serial input/output circuit module 5 is equipped with the above-mentioned clock pulse generator so that only the operating clock frequency of the serial input/output circuit module 5 can be arbitrarily determined independently in relation to this transfer rate. A clock signal CLK2 independent of the ten clock sources is provided.

A CPU module 2, a RAM module 3, a timer/counter module 4, a serial input/output circuit module 5, and a DMAC module 6 and D that operate asynchronously with each other.
The MAC module 7 performs synchronization control (asynchronous bus control) when transferring data via the silicon backplane bus 8 as the asynchronous bus. In this embodiment, the delay control is a control operation that allows data to be exchanged while checking the status of the other party using a handshake signal. For example, the CPU module 2, DMAC module 6, and DMAC module 7, which are examples of bus master modules included in the single-chip microcomputer 1 of this embodiment, acquire bus rights to the silicon backplane bus 8 and operate the bus. When starting a cycle, handshake signals for synchronization control include, but are not limited to, a read/write signal R/W, an address strobe signal As, and a data/write signal.
A strobe signal DS is output, and a data access signal DTA is sent from the accessed module to be accessed.
Uke takes the CK. This data accrual signal DTAC
Although not particularly limited, K is output by the RAM module 3, timer/counter module 4, and serial input/output circuit module 5, which are examples of bus slave modules, and in addition, the CPU module 2 transfers data to the DMAC module 6.7. The DMAC module 6 and the DMAC module 7 can also output when exchanging data to set a destination address, a data transfer source address, or to provide low-level control information.

Although the address strobe signal AS is not particularly limited, its low level indicates that a valid address signal is being supplied on the address bus ABUS. The read/write signal R/W is regarded as a signal that indicates the direction of data transfer, and for example, its high level indicates a read cycle, and its low level indicates a write cycle. Although the data strobe signal DS is not particularly limited, in a read cycle, its low level instructs the other functional module that valid data can be output to the data bus DBUS, and in a write cycle, it instructs the other functional module that valid data can be output to the data bus DBUS. The low level indicates to the other functional module that data has been output. The data acknowledge signal DTACK is, although not particularly limited, an input signal that signifies the completion of data transfer for the module that starts the bus cycle, and the bus cycle start module detects the low level of the data acknowledge signal DTACK during the read cycle. By doing so, data is taken in and the bus cycle is ended, and when the bus cycle activation module detects the low level of the data acknowledge signal DTACK during the write cycle, the bus cycle is ended.

Figure 2 shows that CPU module 2 is connected to RA by synchronization control.
An example of the operation of read accessing the M module 3 is shown.

When the CPU module 2 performs read access to the RAM module 3, the CPU module 2 receives its operation clock signal φ. State S synchronized with (read/read synchronized with l)
The write signal R/W is set to high level, and the address signal A is generated in synchronization with the subsequent state S1. -An to the address bus ABUS, and asserts the address strobe signal AS and data strobe signal DS to low level in synchronization with the next state S2. The CPU module 2 is at least in state S3. In S4, no new signal is output.

When the address strobe signal AS is asserted to a low level, a functional module such as the RAM module 3 uses the address signals A0 to An determined on the address bus ABUS at that time to determine whether or not it has been selected. As a result, the RAM module 3, which is the selected module in the explanation according to FIG. Using the read/write signal R/W at high level and the data strobe DS at low level, the data D0 to Di to be read are output to the data bus DBUS, and furthermore, the data acknowledge signal DTACK is asserted at low level.

Data in the read cycle of CPU module 2
The sampling timing of the acknowledgment signal DTACK is set to state S5, and if the data acknowledgment signal DTACK is sampled at this timing and is at a low level, the CPU module 2 moves onto the data bus DBUS in synchronization with state S6. -Di is fetched and latched, and the address strobe signal AS and data strobe signal DS are input during state S7.
are negated to high level, respectively, and the read cycle ends. Although not particularly limited, address signals A0 to
An and read/write signal R/W are maintained until the end of state S7.

RAM module 3 receives address strobe signal AS
and data D until either or both of the data strobe signal DS and data strobe signal DS are negated. - Maintain the output of Di and the data acknowledgment signal DTACK in the asserted state.

If the access speed of the RAM module 3 is slow and the data acknowledgment signal DTACK is still negated to a high level at the start of state S5 of the CPU module 2, the CPU module 2 A wait state is inserted until the data acknowledgment signal DTACK is asserted to a low level, and the data acknowledgment signal DTACK is
After detecting the asserted state at a predetermined timing, the read cycle is completed as described above.

Figure 3 shows that CPU module 2 is connected to RA by synchronization control.
An example of the operation of write accessing the M module 3 is shown.

When the CPU module 2 performs write access to the RAM module 3, the operation clock signal φ is used. CPU synchronized to
Module 2 state S. address bus AB
tTS is placed in a high impedance state and CP
The U module 2 outputs address signals A, ~An to the address bus ABUS in synchronization with the start of state S, and asserts the address strobe signal As to a low level in synchronization with the next state S2, and , sets the read/write signal R/W to low level.

When the address strobe signal AS is asserted to a low level, a functional module such as the RAM module 3 outputs the address signal A established on the address bus ABUS at that time. -An is used to determine whether or not it has been selected, and as a result, the RAM module 3, which is the selected module in the explanation according to FIG. 3, receives its address signal A.

A memory cell column specified by a predetermined plurality of bits included in ~An is addressed.

The CPU module 2 outputs the data DI, -Di to be written to the data bus DBUS in synchronization with state S3, and asserts the data strobe signal DS to a low level in synchronization with state S4. When the data strobe signal DS is asserted, the RAM module 3 as the selected module uses the low level read/write signal R/W and the low level data strobe signal DS to read data on the data bus DBUS. Data D+
+”Di is read, and after the read data is safely stored internally, the data accrual signal DTA (,
Assert K to low level.

Note that the CPU module 2 does not generate a new signal during state S5.

Data in the write cycle of CPU module 2
The sampling timing of the acknowledgment signal D'I'ACK is set to state SG, and if the data acknowledgment signal 1) TACK is sampled at this timing and is at a low level, the CPU module 2 outputs the address signal during state S7. The strobe signal As and data strobe signal DS are each negated to a high level to complete the write cycle. Address signal A, although not particularly limited. -An and data D. ~Di is maintained until the end of state S7. RAM module 3
maintains the asserted state of the data acknowledge signal DTACK until both or one of the address strobe signal AS and the data strobe signal DS is negated.

If the access speed of the RAM module 3 is low and the data acknowledgment signal DTACK is still negated to a high level at the start of state SG of the CPU module 2, the CPU module 2 A wait state is inserted until the data acknowledgment signal DTACK is asserted to a low level, and the data acknowledgment signal DTACK is
After detecting the asserted state of , the write cycle is completed as described above.

CPU module 2 and RA shown in FIGS. 2 and 3
The contents of the synchronization control of the asynchronous bus with the M module 3 are basically applied to the synchronization control between other functional modules.

In the above description of synchronization control, address signal A is used to determine whether or not the module itself is the selected module.

It was decided that this would be done inside each functional module using a predetermined bit of ~An, but when accessing, the CPU module 2
The bus master module may output a module selection signal for directly specifying the module to be accessed. In this case, the module selection signal is the address signal A. It can be asserted at approximately the same timing as the output timing of ~An.

In the single-chip microcomputer shown in FIG. 1, a CPU module 2, a DMAC module 6,
Although not particularly limited, bus arbitration between the DMAC modules 7 and 7 is performed in a daisy-chain manner, and the CPU 2 has a bus arbiter 13. The bus request signal BR1 output from the DMAC module 6 and the bus request signal BR2 output from the other DMAC module 7 are passed through the AND gate 14. Although the bus request signals BR1, BR2, and BR are not particularly limited, their low level is set as the bus request level. The bus arbiter 13 provides a pass acknowledgment signal BAKo to the DMAC module 6, and this DMAC module 6 provides a pass acknowledgment signal BAK1 to the DMAC module 7. Pass acceptance signal BAKo, B
Although AK1 is not particularly limited, a low level is the bus use approval level. Bus arbiter 13 is CPU2
When the module 2 has not acquired the bus right, the pass acknowledge signal BAKo is asserted to a low level in response to the bus request signal BR being asserted to a low level. The DMAC module 6 that receives this pass acknowledge signal BAKo keeps the pass acknowledge signal BAK1 in the negated state when it is requesting to acquire the bus right, and outputs the pass acknowledge signal BAK when it is not requesting to acquire the bus right. Assert low level. The DMAC module 6.7 provides the bus busy signal BBSY, which indicates that the bus is in use due to its low level, to the bus arbiter 13, whereby the bus arbiter 13 knows the bus occupancy state.

FIG. 4 shows the DMAC: module 6 in a state where the silicon backplane bus 8 is not occupied.
An example of bus arbitration operation when the EDMAC module 7 requests the bus right is shown.

Time t. When the bus request signal BR□ is asserted to low level and in response, the bus request signal BR is set to low level (time 11), the bus arbiter 13
recognizes requests to use the bus.

At this time, if the CPU module 2 does not request bus ownership, the bus arbiter 13 sends a pass acknowledgment signal BAK0.
is asserted to a low level at a predetermined timing (time t□). The DMAC module 6 that receives this recognizes that its request has been accepted and keeps the pass acknowledge signal BAK□ in the negated state. As a result, the DMAC module 6 which has acquired the right to use the bus asserts the bus busy signal BBSY to a low level to declare that the bus is in use.At time t4), the DMAC module 6 enters a data transfer cycle. Note that the bus arbiter 13 receives the bus busy signal B.
When detecting that BSY is changed to low level, pass acknowledge signal BAK0 is negated to high level (time ts).

When the DMAC module 6 completes its own data transfer cycle, it negates the bus busy signal BBSY to a high level and relinquishes the bus right (time t6). At this time, since the other DMAC module 7 is still asserting the bus request signal BR and requesting the bus right since time t2, the bus arbiter 13 asserts the pass acknowledge signal BAK to low level again at time 1T. At this time D
Since the MAC module 6 does not request the bus right, the MAC module 6 directly uses the low-level pass acknowledge signal BAK as it is.
(time ts). As a result, the DMAC module 7 acquires the bus right. D
The MAC module 7 asserts the bus busy signal BBSY to low level to declare that the bus is in use, and enters a data transfer cycle at time t9). When the bus arbiter 13 detects that the bus busy signal BBSY is changed to low level, the bus arbiter 13 outputs a pass acknowledge signal BA.
K is negated to a high level (time t) - In conjunction with this, the pass acknowledge signal BAK□ is also negated to a high level (time t,). When the DMAC module 7 completes its own data transfer cycle, it negates the bus busy signal BBSY to a high level and relinquishes the bus right (time t1□).

Bus arbitration is not limited to the daisy-chain method; if the bus arbiter is provided as an independent functional module, each bus master module gives a bus request signal to the bus arbiter, and each bus master module individually receives a pass acknowledge signal from the bus arbiter. It is also possible to adopt a centralized arbitration method such as Furthermore, the bus arbiter can also perform bus arbitration with an external bus master module on a system bus (not shown) to which the single-chip microcomputer 1 is externally coupled.

FIG. 5 shows a single-chip microcomputer which is another embodiment of the present invention. Like the single-chip microcomputer 1 shown in FIG. 1, the single-chip microcomputer 21 shown in FIG. Synchronization control for data transfer via the silicon backplane bus 28, which is an example of an asynchronous bus, is based on the sampling results of way I requests. This embodiment differs from the above embodiment in that it is based on a control operation that allows the cycle to be extended.

The single-chip microcomputer 21 shown in FIG.
It incorporates functional modules such as a U module 22, a RAM module 23 used as a work area for the CPU module 22, and a parallel input/output circuit module 25. These functional modules are coupled to an address bus ABUS, a data bus DBUS, and a control bus CBUS, which constitute a silicon backplane bus 28 as an asynchronous bus.

Although not shown, the single-chip microcomputer 21 of this embodiment includes a memory management unit that converts the logical address given to the address bus ABUS into a physical address for the external memory space,
The physical address output from this memory management unit is transferred to the single-chip microcomputer 2.
an address output buffer for interfacing the data bus DBUS with the outside of the single-chip microcomputer 21; and a data output buffer for interfacing the data bus DBUS with the outside of the single-chip microcomputer 21; A control bus buffer and the like are provided for interfacing with the outside.

In this embodiment, the CPU module 22, RAM module 23, and parallel input/output circuit module 25
It is assumed that these have circuit configurations that operate in synchronization with a clock signal, and the maximum operating frequencies at which they can operate normally are different. The CPU module 22, RAM module 23, and parallel input/output circuit module 25 are provided with operating clock signals φxor φ□1. φ12 is supplied individually.

These operation clock signals φ101 φ□0. φ1□ is
A frequency dividing circuit 31 which sequentially divides the output of a clock pulse generator 30 having different frequencies and receiving an external clock signal CLK3 such as a system clock signal at an external crystal terminal EXTAL according to a predetermined frequency division ratio, although this is not particularly limited. is output from. This frequency dividing circuit 31 is constituted by a counter having a predetermined number of bits and a selector for selecting the output of this counter, although it is not particularly limited, and obtains a frequency that is a fractional multiple smaller than the output frequency of the clock pulse generator 30.

In this embodiment, synchronization control for data transfer via the silicon backplane bus 28 as an asynchronous bus is performed by the accessed module outputting a wait request to the bus access module. For example, the CPU module 22, which is an example of a bus master module included in the single-chip microcomputer 21 of the present embodiment, uses a read signal RD that instructs a read cycle at a low level and a write signal RD at a low level as bus cycle control signals. A write signal WR instructs a cycle, memory enable signals M and E whose low level indicates a read/write operation of the memory, and I10 whose low level indicates a read/write operation of the input/output circuit. Output enable signal IOE to control bus CBUS. The CPU module 22 receives from the outside a wait signal WAIT for determining whether to insert a wait state into a bus cycle. This wait signal WA
IT includes, but is not particularly limited to, the wait signal WAI T1 output from the RAM module 23 and the wait signal w output from the parallel input/output circuit module 25.
It is supplied from an AND gate 26 that performs a logical product such as A I T .

Here, as shown in FIG. 6, the access cycle of the CPU module 22 is basically based on states T, T2 and T3, and a wait state Tw is inserted as required by the accessed module. The CPU module 22 receives an operation clock signal φ□ in state T2 and wait state Tw. The wait signal W is synchronized with the falling edge of
A I T is sampled, and as a result, the weight signal W
When A I T is at a low level, a wait state Tw is inserted between state T2 and state T3 to prolong the access cycle.

In this embodiment, the read/write cycle time of the RAM module 23 and the parallel input/output circuit module 25 is not particularly limited, but is set to be longer than the read/write cycle time of the CPU module 22. R.A.
When the M module 23 is a module to be accessed by the CPU module 22, this RAM module 2
3 asserts a wait signal WAIT to a low level for a predetermined period of time in order to insert a number of wait states Tw that can prolong the read/write cycle of the CPU module 22 for the period necessary for its own read/write operation. . Similarly, when the parallel input/output circuit module 25 is a module to be accessed by the CPU module 22, this module 25 can extend the read/write cycle of the CPU module 22 by a number of times necessary for its own read/write operation. weight state T
Wait signal WA I T2 to enable insertion of W
is asserted low for a predetermined period. The RAM module 23 and the parallel input/output circuit module 25 use the memory enable signal ME and the I10 enable signal as the assert timing of the wait signals WAIT□ and WAIT2 with respect to the sampling timing of the wait signal WAIT by the CPU module 22, although it is not particularly limited. The assertion timing of IOE can be used as a reference. The assertion period of the wait signal WAIT is not particularly limited, but
The operating clock signal φ□. The wait signal WAIT is determined by taking into consideration the division ratio between the clock signal φ1□ and the operation clock signal φ1□ of the RAM module 23, and the wait signal WAIT.

The operation clock signal φ□ is asserted during the assertion period. The operating clock signal φ12 of the parallel input/output circuit module 25 is determined by considering the division ratio, and these wait signals WA
IT1. WAIT is generated by a wait signal generation circuit (not shown) included in each functional module.

FIG. 6 shows R of the CPU module 22 under synchronization control.
An example of a read/write access operation for the AM module 23 is shown.

When the CPU module 22 performs read access to the RAM module 23, the CPU module 22 enters state T.
The operating clock signal φ□ at 1.

The address signal A is synchronized with the rising edge of the address signal A. ~An to the address bus ABUS, and also asserts the memory enable signal ME and the read signal RD to low level in synchronization with the falling transition of the operating clock signal φ1° in the state T1.

When the memory enable signal ME is asserted to a low level, a memory module such as the RAM module 23 outputs the address signal A that is currently established on the address bus ABUS. -An is used to determine whether or not it has been selected, and as a result, the RAM module 23, which is the selected module in the explanation according to FIG. Data D to be read by addressing a specified word, ie, a memory cell column, and using a read signal RD asserted to a low level. ~ D1 as data bus D
Output to BUS. This data D. -The output timing of Di is determined by the operation of the RAM module 23,
In this embodiment, the RAM module 23 asserts the wait signals WA and IT1 at predetermined timings synchronized with the change of the memory enable signal ME to low level, and synchronizes with the falling timing of the operating clock signal φ1° in state T2. This enables the CPU module 22 to sample the low-level wait signal WAIT. As a result, the CPU module 22 inserts the wait state Tw after the state T2 to extend the read cycle by one cycle of the operating clock signal φ1°.

According to this embodiment, the wait signal WAIT has already been negated to a high level at the sampling timing of the next wait signal WAIT, that is, the falling timing of the operation clock signal φ1o in the wait state Tw, so that the wait signal WAIT is already negated to a high level. After that, the state is set to T3, and the CPU module 22 moves to the state T3.
The read data D is determined on the data bus DBUS in synchronization with the falling timing of the operation clock signal φ1o at No. 3. -Di, and negates the memory enable signal ME and read signal RD to complete the read cycle. This allows R.A.
A CP with a different operating clock frequency from the M module 23.
The U module 22 receives read data D output from the RAM module 23. - Dl can be reliably read.

When the CPU module 22 performs write access to the RAM module 23, the CPU module 22 transfers the address signals A to An to the address bus AB in synchronization with the rising edge of the operating clock signal φ1o in state T1.
Output to US. And the operation clock signal φ□ in the state T1. Write data D, -Dj are output to the data bus DBUS in synchronization with the falling transition of , the memory enable signal ME is asserted to low level, and the operation clock signal φ
1. The signal WR to the line 1 is asserted to low level in synchronization with the rising edge of the signal.

When the memory enable signal ME is asserted to a low level, a memory module such as the RAM module 23 outputs the address signal A that is currently established on the address bus ABUS. -An is used to determine whether or not it has been selected, and as a result, the RAM module 23, which is the selected module in the explanation according to FIG. While addressing the specified memory cell column, using the write signal WR asserted to low level,
Write data D. -Take Di into the interior. The write data D by the RAM module 23. The timing of taking in -Di is determined by the operation of the RAM module 23, and in this embodiment, the RAM module 23 asserts the wait signals WAIT1 to -1 to and the operating clock signal φ1 in state T.
The CPU module 22 is enabled to sample the low level way 1 to signal WAIT in synchronization with the falling timing of signal WAIT. As a result, the CPU module 22 inserts a wait state t-Tw after state T2 and generates the operation clock signal φ□. The write cycle is extended by one cycle. According to this embodiment, the sampling timing of the next wait signal WAIT, that is, the operation clock signal φ□ in way 1-state Tw. Since the wait signal WAIT has already been negated to a high level at the falling timing of Tw, the state T3 follows the wait state Tw, and the CPU module 22 writes the write data D until the end of the state T3.
. While maintaining the output of ~Di, the memory enable signal ME and the write signal W are synchronized with the falling timing of the operation clock signal φ1° in state T3.
R is negated and the write cycle ends. In this way, the write cycle of the CPU module 22 is the operating clock signal φ□. As a result, the RAM module 23, which has an operating clock frequency different from that of the CPU module 22, receives the output data D of the CPU module 22. - The write operation to Dj can be performed reliably.

The contents of the synchronization control for the asynchronous bus between the CPU module 22 and the RAM module 23 shown in FIG. 6 are basically applied to the synchronization control between other functional modules.

In the above description of synchronization control, address signal A is used to determine whether or not the module itself is the selected module.

It was decided that this would be done inside each functional module using a predetermined bit of ~An, but when accessing, the CPU module 2
A path master module such as 2 may output a module selection signal for directly specifying a module to be accessed. In this case, the module selection signal is the address signal A.

It can be asserted at approximately the same timing as the output timing of ~An.

Furthermore, it goes without saying that the number of wait states Tw to be inserted is not limited to one cycle of the operating clock signal, and can be increased or decreased as appropriate depending on the difference in operating speed or operating capability between functional modules that transfer data.

FIG. 7 shows a single-chip microcomputer which is another embodiment of the present invention. The single-chip microcomputer 40 shown in this figure is different from the single-chip microcomputers shown in FIGS. 1 and 5 in the configuration for supplying operating clock signals to each functional module. That is, the functional modules 41 to 43 typically shown in FIG. The clock signal φ is sent to frequency dividing circuits 41A to 43 built in each functional module 41 to 43.
The frequency is divided at a predetermined division ratio at A to obtain individual operating clock signals. With this configuration, the number of clock signal lines to each functional module can be reduced compared to the above embodiments. In this case, the division ratio of the frequency divider circuit included in each functional module may be programmably selectable in the manufacturing process of the single-chip microcomputer 4o by methods such as selective connection of wiring using a master slice or selection of program links. can.

Note that the handshake signal, wait signal, etc. explained in each of the above embodiments can be used for synchronization control for data transfer via the asynchronous bus 45 to which each of the functional modules 41 to 43 is coupled.

FIG. 8 shows a single-chip microcomputer which is still another embodiment of the present invention.

Single-chip microcomputer 5 shown in the same figure
0 includes, for example, three functional modules 51, 52, and 53 with the same operating clock frequency, and a functional module 54 with a different operating clock signal. The functional modules 51 to 53 are commonly supplied with an operating clock signal φ3o having a necessary frequency within the range below their maximum operating frequency, and the functional module 54 is supplied with an operating clock signal φ3□ having a different frequency. . Although these operation clock signals φant φ3□ are not particularly limited,
External clock signal CLK such as system clock signal
5 is outputted from a frequency dividing circuit 58 which sequentially divides the output of the clock pulse generator 57 according to a predetermined frequency division ratio.

Functional modules 51, 52, 53 that can operate synchronously with each other
are coupled together with other asynchronously operated functional modules 54 to an asynchronous bus 55 and also individually by a synchronous bus 56. For example, function module 5
1 is a DMAC module, and a functional module 52
is a RAM module and the functional module 53 is a parallel input/output circuit module.
When an M module or a parallel input/output circuit module is selected as the accessed module, data is transferred between the functional modules 51, 52, and 53 using the synchronous bus 56.
It is now done through. Data transfer by the synchronous bus 56 is performed in units of a common fixed period determined by a plurality of cycles of the operating clock signal φ3°.

For synchronization control for data transfer via the asynchronous bus 55, the handshake signal or wait signal described in each of the above embodiments can be used.

By coupling the functional modules 51 to 53 capable of synchronous operation by the synchronous bus 56 in this way, the exchange of signals for synchronization control required when transferring data via the asynchronous bus 55 is unnecessary. Thereby, data transfer efficiency between the functional modules 51, 52, and 53 can be improved.

Incidentally, even in the single-chip microcomputer 50 shown in FIG. 8, the same configuration as shown in FIG. 7 can be applied to form the operating clock signal of each functional module.

Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited thereto, and various changes can be made without departing from the gist thereof.

For example, although the single-chip microcomputer in the above embodiment is configured in an ASIC format based on a standard cell method,
It can also be an IC.

Further, the types and number of functional modules included in the single-chip microcomputer are not limited to the above embodiments, and can be changed as appropriate.

Furthermore, the clock source is not limited to an external clock, but may also be a vibrator connected to a clock pulse generator. In this way, when a semiconductor integrated circuit has a built-in clock source, a clock signal obtained based on the built-in clock source can be provided externally.

In the above explanation, the invention made by the present inventor was mainly applied to an ASIC type single-chip microcomputer, which is the background field of application, but the present invention is not limited thereto. Regardless of the design method, it can be widely applied to data processing LSIs such as single-chip microcomputers and various semiconductor integrated circuits. The present invention can be applied to a semiconductor integrated circuit in which a plurality of functional modules having at least different maximum operating frequencies are formed on one semiconductor substrate.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, a plurality of functional modules included in one semiconductor substrate with different maximum operating frequencies are operated asynchronously based on operating clock signals with different frequencies, and data is transmitted between the functional modules operated asynchronously via an asynchronous internal bus. Since synchronization control for transfer is performed, the maximum operating frequency of a semiconductor integrated circuit that includes multiple functional modules on a single chip is the lowest maximum operating frequency among the functional modules built into it. This has the effect that the overall operating efficiency of such a semiconductor integrated circuit can be improved without being limited by the functional module.

This is especially true for ASICs, where design assets are reused to construct semiconductor integrated circuits for specific applications.

From the above effects, even if the maximum operating frequency of the functional modules adopted according to the required specifications varies, the operating efficiency of the entire semiconductor integrated circuit will not drop significantly for specific applications configured using these modules. This reduces the need to newly develop or change the design of specific functional modules, and this has the effect that design assets for various functional modules can be reused efficiently or without waste.

In addition, if multiple functional modules with the same operating clock frequency are included, data transfer efficiency between the functional modules can be improved by connecting the functional modules using a synchronous bus. This makes it possible to improve the throughput of the entire semiconductor integrated circuit compared to the case where all functional modules are connected only by an asynchronous bus.

In addition, operating clock signals for functional modules operated at different operating clock frequencies are generated by a clock pulse generator that uses the same clock source and a frequency dividing circuit that divides the output of this clock pulse generator by a required frequency division ratio. However, if the frequency dividing circuit is included in each functional module, the number of clock signal lines to each functional module can be reduced.

Then, the clock is applied to a specific functional module among the functional modules operated at different operating clock frequencies, for example, an input/output circuit whose data transfer rate is defined by a transfer lock frequency independent of the operating clock frequency. By supplying the operating clock signal through a tarok source different from the clock source of the pulse generator, it is possible to arbitrarily determine only the operating clock frequency of the input/output circuit in relation to the transfer relay 1~. This makes it possible to flexibly adapt the semiconductor integrated circuit to the required specifications of a system including a semiconductor integrated circuit, such as a single-chip microcomputer.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a single-chip microcomputer that is an embodiment of the present invention, and FIG. 2 shows an example of synchronization control for read access via an asynchronous bus in the single-chip microcomputer of FIG. 1. Timing chart I ~, FIG. 3 is a timing chart showing an example of synchronization control for write access via an asynchronous bus in the single-chip microcomputer shown in FIG. 5 is a timing chart showing an example of bus arbitration operation for an asynchronous bus in FIG. FIG. 5 is a block diagram of a single-chip microcomputer that is another embodiment of the present invention, and FIG. 6 is a block diagram of synchronization control for read/write access via an asynchronous bus in the single-chip microcomputer of FIG. A timing chart showing an example; FIG. 7 is a block diagram of a single-chip microcomputer that is another embodiment of the present invention; FIG. 8 is a block diagram of a single-chip microcomputer that is still another embodiment of the present invention. . 1. Single-chip microcomputer, 2 CPUs
Module, 3... RAM module, 4... Timer/counter module, 5... Serial input/output circuit module, 6, 7... DMAC module, 8...
Silicon back plane bus, 1O clock pulse generator, 11 frequency divider circuit, 13 bus arbiter, CLKI, CLK2 external clock signal, A
S...address strobe signal, DS/data strobe signal, DTACK...data acknowledge signal, R/W...read/write signal, φ. , φ1. φ2
．． φ3. φi - Operating clock signal, 21... Single chip microcomputer, 22... CPU module, 23... RAM module, 25... Parallel input/output circuit module, 28 Silicon back plane bus, 30... Tarokku pulse generator, 31
・Frequency divider circuit, CLK3...external clock signal, RD
...Read signal, WR...Write signal, ME...Memory input 54...Function module, 55...Asynchronous bus, 56...Synchronized bus, 57...Clock pulse generator, 58...Branch station Circuit, CLK5...external clock signal, φ3fil φ31...operation clock signal. A work T, WA work T□, WAIT2/wait signal, φ1
01 φ40. φ,2...operation clock signal, 41,
42.43...Function module, 41A, 42A, 43
A... Frequency divider circuit, 44... Clock pulse generator, 45... Asynchronous bus, CLK4... External clock signal, φ clock signal, 51, 52, 53° Figure So S+ S2 S3 S455 S6 S? oxDi

Claims (1)

[Scope of Claims] 1. A semiconductor integrated circuit formed on one semiconductor substrate by commonly connecting a plurality of functional modules having different maximum operating frequencies to an asynchronous bus, wherein all or one of the plurality of functional modules is connected in common to an asynchronous bus. A semiconductor integrated circuit in which the functional modules are operated asynchronously based on operating clock signals having different frequencies, and the functional modules operated asynchronously are configured to perform synchronization control for data transfer via an asynchronous bus. 2. The semiconductor integrated circuit according to claim 1, wherein the functional modules operated asynchronously perform synchronization control by mutually exchanging handshake signals. 3. The functional module operated asynchronously gives a wait request to another functional module, and the other functional module performs synchronization control by inserting a wait cycle according to the sampling result of the wait request. The semiconductor integrated circuit described. 4. The semiconductor integrated circuit according to claim 2 or 3, wherein the plurality of functional modules having the same operating clock frequency are also coupled to each other by a synchronous bus. 5. Operating clock signals for functional modules operated at different operating clock frequencies are generated by a clock pulse generator using the same clock source and a frequency dividing circuit that divides the output of this clock pulse generator by a required frequency division ratio. 4. The semiconductor integrated circuit according to claim 2, wherein the frequency dividing circuit is formed and included in each functional module. 6. The operating clock signal for a group of functional modules of the functional modules operated at different operating clock frequencies is obtained by using a clock pulse generator with the same clock source and the output of this clock pulse generator at a required frequency division ratio. The operating clock signal for other specific functional modules is formed by a frequency divider circuit that divides the frequency.
4. The semiconductor integrated circuit according to claim 2, wherein the clock pulse generator is provided through a clock source different from the clock source of the clock pulse generator.