JPH0284808A - Fm carrier detection circuit - Google Patents

Abstract

PURPOSE:To obtain a detecting signal to detect whether or not a reception carrier is a carrier having the absolute value of a recep tion carrier electric field level exceeding a reference value even in a weak electric field by counting the number of signal change of a synchronous detecting signal outputted from a PLL, and detecting whether or not a count value is less than a regulation value. CONSTITUTION:An FM wave received by an antenna 1, after being frequency- converted at a tuner part 2, is inputted to an IF amplifier part 4, and is outputted to a detecting part as an amplified output IF signal, and also, it is inputted to the PLL 5. Phase comparison between the IF signal and oscillation output from a VCO is performed at the PLL 5, then, the synchronous detecting signal LD is outputted. An H level is outputted as the detecting signal LD in a synchronous state, and an L level is outputted in an asynchronous state. The detecting signal LD is inputted to a counter part 6, and a reference clock CLK from a reference clock generating part 7 is frequency-divided to be supplied as a gate signal, and the detecting signal LD in a gate period is counted. A decoder 8 which inputs the count value outputs a carrier detecting signal when the change of count output is less than the regulation value.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an FM receiving circuit in a radio device such as a cellular radio device that switches channels according to the received carrier electric field level, and in particular, the present invention relates to an FM receiving circuit in a radio device such as a cellular radio device that switches channels depending on the received carrier electric field level. The present invention relates to an FM carrier detection circuit that can detect the absolute value of a level.

[Conventional technology]

Conventionally, the absolute value of the received carrier electric field level of FM can be detected using the rectification level of the intermediate frequency signal amplified by the intermediate frequency amplification section, or because the intermediate frequency amplification section consists of a limiter amplifier, its AGC (Automatic
Generally, this was done by adjusting the voltage level (Ga1n Control).

However, when the receiving channel is exposed to a weak electric field, the S/N of the intermediate frequency signal deteriorates, the level (i.e., rectification level or AGC voltage level) decreases, or the temperature of the component circuits decreases. Since the instability of the signal cannot be ignored and the level varies depending on the temperature, it has been difficult to accurately determine the absolute value of the received carrier electric field level at that point from the level.

In particular, the AGC voltage level has large temperature variations during this weak electric field, which poses a problem in detecting the absolute value of the received carrier electric field level.

Incidentally, the signal level detection circuit using the rectified level and the device using this type of signal level detection circuit are related to, for example, Japanese Patent Application Laid-Open No. 13717/1982 and Japanese Patent Application Laid-Open No. 18229/1982. Publication, JP-A-60-13
Publication No. 901 and the like can be mentioned.

[Problem to be solved by the invention]

The above conventional technology does not take into consideration the detection accuracy of the absolute value of the received carrier electric field level in a weak electric field or the variation of the detected value due to temperature. There are cases where a function is required to detect a value of about -2 dBμv as the absolute value of the level, but the above-mentioned conventional technology has caused difficulties in performing such detection.

The purpose of the present invention is to solve the problems of the prior art described above,
An object of the present invention is to provide an FM carrier detection circuit that makes it possible to easily detect the absolute value of a received carrier electric field level in a weak electric field.

[Means to solve the problem]

In order to achieve the above object, the present invention inputs an intermediate frequency signal amplified by an intermediate frequency amplification section to an FM carrier detection circuit, compares the phases of the intermediate frequency signal and a reference signal, and compares the phases of the intermediate frequency signal and a reference signal. As a result of the comparison, a synchronization detection signal indicating in binary form whether the intermediate frequency signal and the reference signal are in a synchronous state or an asynchronous state is outputted, and the reference signal and the reference signal are synchronized with the intermediate frequency signal. A phase-locked loop that controls the frequency of the reference signal based on a synchronization detection signal; and a phase-locked loop that inputs a reference clock, divides the frequency of the reference clock to obtain a gate signal, and detects the synchronization during one gate period of the gate signal. It consists of a counting section that counts the number of changes in the signal, and a detecting section that detects whether the counted value counted by the counting section is below a certain specified value and outputs the detection result. As a detection output of the detection unit, a carrier detection signal indicating whether the received carrier is a carrier having an absolute value of the received carrier electric field level equal to or higher than a certain reference value is obtained.

[Effect]

The PLL is composed of, for example, a voltage controlled oscillator, a quadrature phase comparator, etc., and the input intermediate frequency signal and the reference signal, which is an oscillation output from the voltage controlled oscillator, are connected to the quadrature phase comparator. The phases are compared and the synchronization detection signal is obtained as the comparison output.

Further, the oscillation frequency of the voltage controlled oscillator is controlled based on the synchronization detection signal so that the reference signal is synchronized with the intermediate frequency signal.

Further, when the intermediate frequency signal and the reference signal are in a synchronous state, the synchronization detection signal is, for example, at the II H11 level, in an asynchronous state (a state in which synchronization has occurred).
It is a binary signal that is at the 11 L II level when the signal is at the 11 L II level.

In P and LL, lock range, following speed, etc.
Below a certain level determined by the performance of the PLL,
A carrier having the absolute value of the received carrier electric field level is defined as F
When the M receiving circuit is receiving, the reference signal is synchronized with the intermediate frequency signal, but as the electric field gradually becomes weaker, synchronization occurs, and the reference signal becomes synchronized with the intermediate frequency signal. I'm starting to stop doing it. Therefore,
Looking at the number of signal changes within a certain period of time of the synchronization detection signal, which is the output of the PLL, it is found that when the absolute value of the received carrier electric field level is below the specified level, the electric field becomes weak and the received carrier deteriorates. As the absolute value of the received carrier electric field level decreases, it increases monotonically.

Therefore, within this monotonically increasing range, the absolute value of the received carrier electric field level has a unique correspondence with the number of signal changes in the synchronization detection signal within a certain period of time.

The present invention focuses on the above phenomenon.

Therefore, the counting section inputs a reference clock in order to count the number of signal changes in the synchronization detection signal within a certain period of time,
The reference clock is frequency-divided to obtain a gate signal, and the number of changes in the synchronization detection signal is counted during one gate period of the gate signal.

Further, the detection section detects whether or not the count value counted by the counting section is less than or equal to a specified value, and outputs the detection result.

Therefore, in the present invention, when a certain value is to be detected as the absolute value of the received carrier electric field level, the above-mentioned The performance of the PLL is determined, and a specified value in the detection section is set to the number of signal changes within one gate period of the synchronization detection signal corresponding to the detection level.

By doing so, the carrier detection signal obtained as the detection output of the detection unit determines whether the absolute value of the received carrier electric field level is equal to or higher than the detection level, in other words, the detection level (i.e., the reference value). ) indicates whether a carrier having an absolute value of the received carrier electric field level is being received or not.

In the present invention, the relationship between the above-mentioned absolute value of the received carrier electric field level and the number of signal changes within a certain period of time of the synchronization detection signal is as follows:
The present invention makes it possible to detect the absolute value of the received carrier electric field level in a weak electric field, which has been difficult in the past, because it is not affected by the S/N deterioration of the intermediate frequency signal or the temperature instability of the constituent circuits. It can be done easily.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

In the figure, 1 is an antenna, 2 is a tuner section, 3 is a filter, 4 is an intermediate frequency amplification section, 5 is a PLL, 6 is a counting section, 7 is a reference clock generation section, 8 is a decoder, IF is an intermediate frequency signal, LD is a synchronization detection signal, CLK is a reference clock, and CD is a carrier detection signal.

Now, the configuration and operation will be explained.

FM waves received by the antenna 1 are frequency-mixed in the tuner section 2 and input to the intermediate frequency amplification section 4 via the filter 3. The amplified output of the intermediate frequency amplification section 4 is supplied to the next detection stage (not shown) as an intermediate frequency signal IF, and is also input to the PLL 5.

The PLL 5 is composed of a voltage controlled oscillator, a quadrature phase comparator, etc. (not shown), and receives an input intermediate frequency signal! F and the oscillation output from the voltage controlled oscillator are phase-compared by a quadrature phase comparator, and a synchronization detection signal LD is obtained as the comparison output. Further, the oscillation frequency of the voltage controlled oscillator is controlled based on the synchronization detection signal LD so that the oscillation output is synchronized with the intermediate frequency signal IF.

When the intermediate frequency signal IF and the oscillation output are in a synchronous state, the synchronization detection signal LD is at the "H" level, for example, and when they are in an asynchronous state (out of synchronization), it is at the -"L11 level. This is a binary signal.

The counting section 6 divides the reference clock CLK from the reference clock generating section 7 to obtain a gate signal, receives the synchronization detection signal LD, and counts the number of changes in the gate signal during one gate period.

The decoder 8 inputs the count output, and outputs a signal when the count output is less than a specified value.

The output from this decoder 8 becomes the carrier detection signal CD.

Here, the relationship between the absolute value of the received carrier electric field level of the carrier received by the antenna 1 and the synchronization detection signal LD will be explained.

When the PLL 5 is receiving a carrier having an absolute value of the received carrier electric field level below a certain specific level (details will be discussed later), the oscillation output is the intermediate frequency signal I.
However, as the electric field gradually becomes weaker and the received carrier deteriorates, that is, the absolute value of the received carrier electric field level decreases, synchronization occurs and the oscillation output becomes an intermediate frequency signal. It becomes out of sync with IF. Then, the intermediate frequency signal IF and the oscillation output alternately repeat a synchronous state and an asynchronous state.

Therefore, the number of signal changes in the synchronization detection signal LD changes as shown in FIG. 2 as the absolute value of the received carrier electric field level changes.

FIG. 2 is a characteristic diagram showing the relationship between the absolute value of the received carrier electric field level and the number of changes in the synchronization detection signal in the embodiment of FIG.

In FIG. 2, the horizontal axis indicates the absolute value of the received carrier electric field level, and the value increases as it goes to the left and decreases as it goes to the right. Further, the vertical axis indicates the number of signal changes (average value) of the synchronization detection signal, and the value increases as it goes up and decreases as it goes down.

As shown in FIG. 2, the average value of the number of signal changes in the synchronization detection signal monotonically increases from a certain level of 0 as the absolute value of the received carrier electric field level decreases. The 0 point on this specific level is associated with the performance of the PLL 5. For example, in a cellular radio, 6 dBu
It is conceivable that it is about v.

As described above, within this monotonically increasing range, the absolute value of the received carrier electric field level can uniquely correspond to the number of signal changes within a certain period of time of the synchronization detection signal LD. Therefore, when trying to detect a certain value as the absolute value of the received carrier electric field level, the performance of the PLL 5 is determined so that that value (hereinafter referred to as the detection level) falls within the monotonically increasing range described above. If the number of signal changes within one gate period of the synchronization detection signal LD corresponding to the detection level is the specified value of the decoder 8, then the carrier detection signal CD
This indicates that the absolute value of the received carrier electric field level is greater than or equal to the detection level, or in other words, that a carrier having the absolute value of the received carrier electric field level that is greater than or equal to the detection level is being received.

In this embodiment, the counting output of the counting unit 6 is initialized at the start of counting (at the rising or falling edge of the gate signal), and thereafter, within one gate period, the counting results at each point in time are shown. shall be taken as a thing.

According to this embodiment, when the count value exceeds the specified value within one gate period, the carrier detection signal CD changes immediately, so there is an effect that the disappearance of the carrier electric field can be quickly dealt with.

Next, a second embodiment of the present invention will be described.

FIG. 3 is a block diagram showing a second embodiment of the invention.

In the figure, 9 is a comparator, 10 is a rewritable register, and other parts equivalent to those in the first embodiment described above are given the same reference numerals.

In this embodiment, the configuration and operation up to obtaining a count output in the counting section 6 are the same as those in the first embodiment.

Therefore, the operation after that will be explained.

The count output of the counting section 6 is input to the comparator 9.
is constantly compared with the value stored in register 10. Here, the comparator 9 outputs a signal when the relationship of counted value≦stored value holds.If the stored value is the specified value, the comparison output of the comparator 9 is used to generate the carrier detection signal CD.
get.

This embodiment has the same effect as the first embodiment, and since the register 10 is rewritable, the specified value can be rewritten to any value, and therefore the detection level can be changed. This has the effect that it can be done.

Next, a third embodiment of the present invention will be described.

FIG. 4 is a block diagram showing a third embodiment of the present invention.

In the figure, 11 is a counting section, 12 is a detection section, 13.1
6 is a gate circuit, 14 is a counter, 15 is a variable frequency divider,
17 is a microprocessor (hereinafter referred to as MPU), 1
8 is a memory, S is a counting start signal, R is a gate signal, and other parts equivalent to those in the first embodiment described above are given the same reference numerals.

In this embodiment, the configuration and operation up to obtaining the synchronization detection signal LD as the output of the PLL 5 are the same as in the first embodiment. Therefore, the configuration and operation after that will be explained.

The counting section 11 is composed of a gate circuit 13.16, a counter 14, and a variable frequency dividing circuit 15, and the detecting section 12 is composed of an MPU 17.
and a memory 18.

The counting section 11 operates to count the number of signal changes in the synchronization detection signal LD during one gate period determined by the control of the MPU 17 of the detection section 12, and its operation will be described below.

The synchronization detection signal LD is input to the gate circuit 13 of the counting section 11. On the other hand, the reference clock CLK from the reference clock generating section 7 is inputted to the gate circuit 16 . Gate circuit 1
6 permits input of the reference clock CLK to the variable frequency divider 15 by the counting start signal S output from the MPU 7 of the detection unit 12. Further, the variable frequency divider 15 is connected to the MPU 7 of the detection unit 12.
The input reference clock C with the frequency division ratio determined by
Divide the frequency of LK to obtain a gate signal R. The gate circuit 13 allows the synchronization detection signal LD to be input to the counter 14 for one gate period using the gate signal R. The counter 14 counts the number of signal changes in the input synchronization detection signal LD. Then, the output of the counter 14 is inputted to the MPU 17 of the detection section 12 as the count output of the counting section 11.

Furthermore, the gate signal R is also input to the MPU 17 of the detection unit 12 to notify the end of the counting operation.

The main parts of the above operation will be explained in more detail using FIG. 5.

FIG. 5 is a timing chart showing the timing of the main signals in FIG. 4.

In the figure, A indicates one gate period, and H indicates a hold period of the output of the counter 14.

As shown in FIG. 5, when the MPU 17 of the detection unit 12 sets the counting start signal S to "H+ level", the gate circuit 16 allows input of the reference clock CLK to the variable frequency divider 15, and , the counter 14 and the variable frequency divider 15 are each initialized. When the variable frequency divider 15 is initialized, the gate signal R becomes "L" level, and the gate circuit 13 sends the synchronization detection signal LD to the counter 14. Allow input.

Thereafter, when the variable frequency divider 15 sets the gate signal R to "H" level and the gate period A ends, the gate circuit 13 prohibits input of the synchronization detection signal LD to the counter 14, and As a result, the output of the counter 14 is held, and the MPU 17 of the detection unit 12
Set the counting start signal S to "L" level. Counting start signal S is °“L”.

When the level is reached, the gate circuit 16 outputs the reference clock CLK.
input to the variable frequency divider 15 is prohibited, and the gate signal R, which is the output of the variable frequency divider 15, is held at the "H" level.

Next, the operation of the detection section 12 will be explained in more detail.

The MPU 17 detects whether the counting output of the counting section 11 is within a specified value, calculates the average value and the absolute value of the received carrier electric field level from the counting output, and performs counting operations of the counting section 11. Control processing and setting of the frequency division ratio of the variable frequency divider 15 that determines the length of one gate period are executed respectively. For this reason, MPU
17 is an input port for inputting the counting output from the counting section 15; an interrupt terminal for inputting the gate signal R;
It includes an output port that outputs a start signal S and a frequency division ratio control output of the variable frequency divider 15.

The memory 18 also stores prescribed values for counting outputs, data necessary for calculating the absolute value of the received carrier electric field level, and the like.

Next, the control processing and calculation processing of the MPU 17 will be explained.

FIG. 6 and FIG. 7 are flowcharts each showing an outline of the process 2-) among the processes performed by the MPU 17.

First, the process shown in FIG. 6 is for starting detection of the absolute value of the received carrier electric field level at fixed time intervals or as needed by an internal interrupt of the MPU 17.

To explain according to the flow of the figure, first, after other interrupts are prohibited, it is determined whether the frequency division ratio of the variable frequency divider 15 is to be changed from the current setting.

This is to determine whether to increase detection accuracy or perform high-speed detection, and determine the length of the l-gate period, as necessary. When the setting of the frequency division ratio of the variable frequency divider 15 is completed, next, the counting start signal S is changed from the "L" level to the "H" level to start the counting operation. Thereafter, after enabling other interrupts, the process returns from this interrupt processing.

Second, when the counting operation for one gate period is completed in the counting section 11, the rising edge of the gate signal R causes the MPU1 to
7 and executes the process shown in FIG. First, after disabling other interrupts, the counting start signal S is set to “H”.
” level to “L” level and hold the counting output of the counting unit 11.Next, the counting output is read and it is determined whether it is below the specified value, and the carrier which is the detection output of the detection unit 12 is read. A detection flag (that is, equivalent to a carrier detection signal) is set or reset.

If the count output is less than the specified value, the count output is stored in the memory 18, and the average count value is determined from the count output values of the past several times. For example, the absolute value of the received carrier electric field level and the synchronization detection signal L shown in FIG.
By preparing in the memory 18 and referring to a data table of absolute value data of the received carrier electric field level corresponding to the average counted value data obtained from the characteristic of the number of changes in the signal of D, the received carrier is determined from the average counted value. The absolute value of the electric field level is determined and stored in the memory 18. After the above processing, other interrupts are enabled and the process returns from this interrupt processing.

According to this embodiment, the absolute value of the received carrier electric field level that is higher than the detection level in a weak electric field can be determined by calculation. Therefore, there is an effect that processing can be performed according to the absolute value of the received electric field level obtained. Furthermore, since the frequency division ratio of the variable frequency divider 15 is variable, the counting section 1
There is an advantage that the counting precision of 1 and the counting time (that is, 1 gate period) can be selected according to each process that requires detection of the absolute value of the received carrier electric field level.

Next, a fourth embodiment of the present invention will be described.

FIG. 8 is a block diagram showing a fourth embodiment of the present invention.

In the figure, 19 is a level detection section, 20 is a level identification section, 21 is an FM carrier detection circuit, and other parts equivalent to those in the first embodiment described above are given the same reference numerals.

In this embodiment, the configuration and operation up to outputting the intermediate frequency signal IF to the intermediate frequency amplification section 4 are the same as those in the first embodiment. Therefore, the configuration and operation of the characteristic parts of this embodiment will be explained.

The intermediate frequency signal IF is supplied from the intermediate frequency amplifying section 4 to the next detection stage (not shown) and the PLL 5 as in the first embodiment, and is also input to the level detecting section 19. The level detecting section 19 extracts the rectified level of the intermediate frequency signal IF and inputs it to the level identifying section 20 . The level identification unit 20 converts the rectified level into a binary signal using a specific threshold and outputs the signal.

Here, the value of the threshold is set to the value of the rectification level when a carrier electric field of a level slightly stronger than the specific level zero point shown in FIG. 2 is received.

In this embodiment, the PLL5. Counting part 6. Reference clock generator 7. This switch turns on/off the power of the FM carrier detection circuit 21 composed of the decoder IO, and when the received carrier deteriorates, that is, the absolute value of the received carrier electric field level decreases, the rectified level from the level detection unit 19 decreases. is the level identification part 2
When the threshold of 0 is no longer satisfied, the binary signal becomes "L" level, and the power of the FM carrier detection circuit 21 is turned on.

Note that the operation of each component constituting the FM carrier detection circuit 21 when the power is turned on is the same as in the first embodiment.

According to this embodiment, there are effects similar to those of the first embodiment,
Furthermore, since power is supplied to the FM carrier detection circuit 21 only when the electric field is weak, the power consumption of the circuit can be reduced.

〔Effect of the invention〕

According to the present invention, the number of signal changes in the synchronization detection signal output from the PLL is counted for a certain period of time, and by detecting whether or not the counted value is less than a certain specified value, in a weak electric field. Also, it is possible to obtain a carrier detection signal indicating whether or not the received carrier has an absolute value of the received carrier electric field level equal to or higher than a certain reference value.

Therefore, in the past, it has been difficult to perform
According to the present invention, the absolute value of the received carrier electric field level in a weak electric field can be easily detected.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
FIG. 3 is a characteristic diagram showing the relationship between the absolute value of the received carrier electric field level and the number of changes in the synchronization detection signal in the embodiment of FIG. 1, and FIG. 3 is a block diagram showing the second embodiment of the present invention.
FIG. 4 is a block diagram showing a third embodiment of the present invention, and FIG.
4 is a timing chart showing the timing of the main signals in FIG. 4, FIGS. 6 and 7 are flowcharts showing an outline of the MPU control process and counting process in FIG. 4, and FIG. FIG. 2 is a block diagram showing an embodiment of the invention. Explanation of symbols 1... Antenna, 2... Tuner section, 3... Filter, 4... Intermediate frequency amplification section, 5... PLL, 6,
11... Counting section, 7... Reference clock generation section, 8.
...Decoder, 9...Comparator, 10...Register,
12...Detection section, 13.16...Gate circuit, 14
...Counter, 15...Variable frequency divider, 17...M
PU, 1B...Memory, 19...Level detection section, 2
0... Level identification L21... FM carrier detection circuit. Agent Patent Attorney Akio Namiki A; Thea Figure 1 - Sorrow Island Carrier Dengan, Shibel's Fart Length (I Nao @ Figure 3 Figure @ 7)

Claims (1)

[Claims] 1. In an FM receiving circuit using a superheterodyne system, an intermediate frequency signal amplified by an intermediate frequency amplification section is input, the intermediate frequency signal and a reference signal are compared in phase, and the As a result of the comparison, a synchronization detection signal indicating in binary form whether the intermediate frequency signal and the reference signal are in a synchronous state or an asynchronous state is outputted, and the reference signal and the reference signal are synchronized with the intermediate frequency signal. A phase-locked loop that controls the frequency of the reference signal based on a synchronization detection signal; and a phase-locked loop that inputs a reference clock, divides the frequency of the reference clock to obtain a gate signal, and detects the synchronization during one gate period of the gate signal. It consists of a counting section that counts the number of changes in the signal, and a detection section that detects whether the count value counted by the counting section is below a certain specified value and outputs the detection result, The detection output of the detection unit is used as a carrier detection signal indicating whether or not the carrier being received by the FM receiving circuit is a carrier having an absolute value of a received carrier electric field level equal to or higher than a certain reference value. FM
Carrier detection circuit. 2. In the FM carrier detection circuit according to claim 1,
The detection unit inputs the count value counted by the counting unit, and only when the count value is equal to or less than the specified value,
An FM carrier detection circuit comprising a decoder that outputs a certain signal, and the output of the decoder is used as the detection output of the detection section. 3. In the FM carrier detection circuit according to claim 1,
The detection unit compares the specified value stored in the register with the counted value counted by the counting unit, and determines that the counted value is less than or equal to the specified value. a comparator that outputs a certain signal only when
FM carrier detection circuit, characterized in that the output of the comparator is used as the detection output of the detection section, and the specified value stored in the register can be rewritten to any value. . 4. The FM carrier detection circuit according to claim 1,
The detection unit detects whether the count value counted by the counting unit is less than or equal to the specified value, and outputs the detection result, and also detects the average value and the count value counted by the counting unit. comprising a calculation means for calculating the absolute value of the received carrier electric field level, and a memory for storing the calculation result obtained by the calculation means and data necessary for the calculation, and using the detection output of the calculation means. , the detection output of the detection section. 5. The FM carrier detection circuit according to claim 1,
The counting section includes a variable frequency divider capable of dividing the reference clock by several different frequency division ratios, and the detection section includes a control means for setting the frequency division ratio of the variable frequency divider. An FM carrier detection circuit characterized by the following. 6. The FM carrier detection circuit according to claim 1,
A reference clock that generates the reference clock, further comprising: a level detection unit that extracts the rectification level of the intermediate frequency signal; and a level identification unit that converts the extracted rectification level into a binary signal using a predetermined threshold; An FM carrier detection circuit, characterized in that power supply to the generation section, the phase-locked loop, the counting section, and the detection section is controlled by a binary signal from the level discrimination section.