JPH0283886A - Lifo device - Google Patents

Abstract

PURPOSE:To reset all data in respective memory cells within the time of one machine cycle by providing a resetting means in respective memory cells to constitute a LIFO device. CONSTITUTION:When a normal action is executed and the input of a Reset terminal 43 is 1, since the input of 2-input NAND 13, 23 and 33 becomes 1, when data are pushed in from a Push in terminal, a transfer gate 51 is opened, data are inputted to a NAND 13, simultaneously, gates 21 and 31 of memory cells 20 and 30 are opened and the data in a memory cell 50 are inputted to a NAND 23 in a cell 60 and the data in a cell 60 are inputted to a NAND 33 in a cell 30. Simultaneously, when gates 11, 21 and 31 are closed, gates 15, 25 and 35 are opened, the inverted data are inputted to inverters 14, 24 and 34 and the push-in of the data is completed. On the other hand, when the input of the terminal 43 is 0, the input of the NAND 13, 23 and 33 becomes 0, and outputs theta1, theta2 and theta3 become 1. When a control pulse phi3 becomes 1, the gates 15, 25 and 35 are opened and the output of the inverters 14, 24 and 34 becomes 0.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a last-in first-out memory device (La5t-in first-out memory device), which is a type of memory device.
(hereinafter abbreviated as LIFO device).

(Prior Art) FIG. 2 shows an example of the configuration of a conventional 1-pin, 3-word LIFO device (for example, Ne1l H, E, Weste, K
amranEghraghian, PRINCIPL
ES OF 0MO8VLSI DESIGN (198
5),ADDISON-WESIJY,P,364
-366). In FIG. 2, 50, 60.70 are memory cells for 1 bit each, and memory cell 5
Memory cells 0 and 60 have the same circuit configuration, and memory cell 0 has one less transfer gate than memory cells 50 and 60.

The memory cell 50 has a transfer gate 51°52.55
．． 56 and Inno-Ni-Yu 53 and 54. The input end of the transfer gate 5 is connected to the Pu5h in terminal 81, and the output end is connected to the input end of the inverter 53 and the output end of the transfer gate 52.

The output terminal of the inverter 53 is connected to the Pop out terminal 82 and the input terminal of the transfer dart 55, the output terminal of the transfer gate 55 is connected to the input terminal of the inverter 540 and the output terminal of the transfer dart 56, and the output terminal of the inverter 54 is connected to the input terminal of the inverter 540 and the output terminal of the transfer dart 56. The input terminal of the transfer gate 52 is connected to the input terminal of the transfer gate 6 of the memory cell 6θ, and the input terminal of the transfer gate 56 is connected to the input terminal of the transfer gate 6 of the memory cell 6θ.
The output terminal of the inverter 63 is connected to the output terminal of the inverter 63. Transfer gates 51, 52, 55 and 56 receive control pulses φ1, φ2, φ8, . The opening/closing operation is performed based on φ4.

The operation of the 1-bit, 3-word IJFO device shown in FIG. 2 is as follows.

First, when data is pushed in from the push in terminal 81, the data is input to the inverter 53 by opening the transfer gate 51, and at the same time, the transfer gate 61.71 of the memory cell 60.70 is opened to input the data to the inverter 53. The data in the memory cell 6θ is input to the inverter 63 in the memory cell 60, and the data in the memory cell 6θ is input to the inverter 73 in the memory cell o. Next, by closing the transfer gates 51, 61.71 and simultaneously opening the transfer gates 55, 65, 75, the data inverted by the inverters 53, 63, 73 are inputted to the inverters 54, 64°74, respectively. Complete the push-in action.

The data inputted into the memory cells 50, 60, and 70 are transferred to the transfer ports 52, 55, 62, and 6, respectively.
It can be held in the memory cells 50, 60.70 by alternately opening and closing 5.72 and 75.

Next, in a data read operation, that is, when outputting the held data to the Popout terminal 82, the held data is input to the inverters 53, 63, and 73 by opening the transfer gates 52, 62, and 72, respectively. Then, the output of the inverter 53 is output to the pop out terminal 82, which becomes the data to be read. Thereafter, transfer gates 52, 62, and 72 are closed and transfer gates 56 and 66 are opened to shift the data held in memory cells 60 and 70 to the left into memory cells 50 and 60, respectively.

(Problem to be Solved by the Invention) However, in the LIFO device with the above configuration, if you want to reset all the internal data, such as when the internal data changes due to external noise, etc., it is necessary to write 0'' data for the number of words. There is a LIFO consisting of N words.
There is a problem in that in order to reset all data in the device, a time of N machine cycles is required, assuming that the cycle time for reading and writing is one machine cycle.

The present invention eliminates the above-mentioned problem that it takes N machine cycles to reset data in the LIFO device, and provides an excellent LIFO device that can reset all data in one machine cycle. The purpose is to provide.

(Means for Solving the Problems) The present invention provides a first transfer dart whose input end is connected to a first input terminal, a second transfer dart whose input end is connected to a first output terminal, a third transfer gate whose input terminal is connected to the second input terminal; and a fourth transfer gate whose input terminal is connected to the second output terminal.
), and a two-input NAND, one of which is connected to the output terminals of the first and fourth transfer darts, the other is connected to the reset terminal, and the output terminal is connected to the first output terminal. , an inverter whose input terminals are connected to the output terminals of the second and third transfer gates, and an inverter whose output terminals are connected to the second output terminal.

(Function) By setting the input value of the reset terminal to 1n, L
The IFO device operates as a normal IJFO device. That is, by controlling the opening and closing of the first to fourth transfer gates, data is forced into the first input terminal and data held from the second output terminal is output to the next stage memory cell. Furthermore, it is possible to push out and output the held data from the first output terminal and input data from the next stage from the second input terminal.

When the input value of the reset terminal is set to “0”, 2 inputs N
Since one input terminal of the AND becomes "0", the output value of the two-input NAND becomes "1" regardless of the input value of the other input terminal.Therefore, when the second transfer gate is opened, , the output "1°" of the two-input NAND is input to the inverter. As a result, the output value of the inverter becomes "0'" and the data is set.

(Embodiment) FIG. 1 shows a 1-bit, 3-word LI that is an embodiment of the present invention.
It is a circuit diagram of the FO device, and the memory cell is 10°20.30
It consists of

The memory cell 10 is a transfer adder) III 2゜15.16, a 2-input NAND 13, and an inverter 1.
The input terminal of the transfer gate 11 is connected to the Pu5h in terminal 41, and the output terminal is connected to the 2-input NA
Input terminal 101 of ND I 3 and transfer gate 1
2 output terminals, respectively. 2 input NAND
The output terminal of the transfer gate 13 is connected to the pop out terminal 42 and the input terminal of the transfer gate 15, and the output terminal of the transfer gate 15 is connected to the input terminal of the inverter 14 and the output terminal of the transfer gate 16. is connected to the input terminal of the transfer gate 12 and the input terminal of the transfer gate 21 in the memory cell 2o, and the input terminal of the transfer gate 16 is connected to the output terminal of the 2-input NAND in the memory cell 2o, and
1.9 input terminal 102 is connected to Re5et terminal 43.

Memory cell 2θ has the same configuration as memory cell 10, and memory cell 3θ differs from memory cells 10 and 20 only in that it does not have a transfer gate corresponding to transfer gate 16 or 26.

As explained above, the circuit shown in FIG. 1 is different from the circuit shown in FIG. It is replaced with input NAND.

Note that the LIFO device shown in FIG.
d transfer gates 11, 12, 15, 16 . ..., 35 is,
For example, with the CMOS transformer 7 adapter shown in Fig. 3(a) or the MOS inverter shown in Fig. 3(b), 2 input NA
The NDs 23.23 and 33 can be configured with, for example, MOS FETs, and the inverters 14 and 24.34 can be configured with, for example, CMOS inverters.

Next, the circuit operation of the embodiment shown in FIG. 1 will be explained with reference to the operation timing chart shown in FIG. 4. In addition, the third
In the figure, T1 to T indicate machine cycles.

First, when operating normally, connect Res e to terminal 43.
When the input value (Re5et) is 1'', the inputs of the input terminals 102, 202, and 302 of the 2-input NAND 13, 23, and 33 are N, respectively.
III, so the two input NAND 13, 23
.

33 are inverters 53°63.7 shown in FIG. 2, respectively.
3, the operation of the circuit shown in FIG. 1 is the same as that of the circuit shown in FIG. 2 described above. During the period T1T2 shown in FIG. 4, the memory cells 10,
20.30 transfer gates 12 and 15.22 and 2
Control pulses φ2 and φ3 are applied alternately to cells 5.32 and 35, and data 1 and 2.3 are held in memory cells 10 and 20.30, respectively. Note that θ1 to θ3 in FIG. 4 are memory cells 10, 20, and 3, respectively.
2 input NAN within 0, D 13,2 ;? .

The output values θ1a, θ2a, and θ3a of 33 represent the output values of the inverters 14, 24, and 34, respectively.

Next, a case will be described in which data in the memory cells 10, 20, and 30 is reset. Re5 to reset
The input value of the et terminal 43 is set to "0".

As shown in FIG. 4, when the input value Re5et of the Re5et terminal 43 is set to "0" at time t, the two-input NAND I3 in the memory cells 10, 20, and 30
.

Since the inputs of the input terminals 102, 202, and 302 of 23.33 are +101+, the two input NAND l &,
The output values θ1, θ2, and θ3 of 23 and 33 become 1'' as shown in FIG. 15, 25.35, the control force φ, becomes 1", and the transfer l"
- When gates 15 and 25.35 open, 2 input NAND 13
,2,? , 33 are input to the inverters 14, 24.34, respectively, and the inverter 14
, 24.34, the output values θ1, θ2a, and θ6a are respectively "0" as shown in FIG. That is, by keeping the input value of the Re5et terminal 43 at "0" for at least one machine cycle until the output values of the inverters 14, 24, and 34 of the memory cells 10, 20, and 30 are determined, All data in each memory cell of the LIFO device can be set to 0'' (reset) within one machine cycle.

Although this embodiment is a case of a 1-bit/3-word LIFQ device, it can also be applied to an n-bit/m-word LIFO device, and similar effects can be obtained.

FIG. 5 shows an example of a 2-bit, 4-word LIFO device.

(Effects of the Invention) As described above in detail, according to the present invention, LIFO
Since a reset means is provided in each memory cell constituting the device, it is possible to reset all data in each memory cell within one machine cycle.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional L
The circuit diagram of the IFO device, Figure 3 is the circuit diagram of the transfer gate, Figure 4 is the operation timing diagram, and Figure 5 is the 2-bit 4
Circuit diagram of word LIFO device 0 10.20.30...memory cell, 11,12゜15
．． 16, 21, 22, 25, 26, 31, 32゜35・
...Transfer gate, 13,23.33...2 input NAND, 14,24.34...Inverter, 41
-Pu5h in terminal, 42-Pop out terminal, 43---Reset terminal, 201, 102-2
Input terminal of input NAND 13, 201.202...
2 input NAND 23 input terminals, 301.302...
・2-input NAND ss input terminal. Patent applicant Oki Electric Industry Co., Ltd.

Claims (1)

[Claims] A first transfer gate whose input terminal is connected to the first input terminal; a second transfer gate whose input terminal is connected to the first output terminal; and a second transfer gate whose input terminal is connected to the first output terminal. a third transfer gate connected to the input terminal; a fourth transfer gate whose input terminal is connected to the second output terminal; and one of the two input terminals is the output terminal of the first and fourth transfer gates. a two-input NAND, the other of which is connected to the reset terminal, and whose output terminal is connected to the first output terminal; and whose input terminals are connected to the output terminals of the second and third transfer gates. A LIFO device comprising a memory cell having an inverter whose output terminal is connected to the second output terminal.