JPH0282814A - Programmable logic device - Google Patents
Programmable logic deviceInfo
- Publication number
- JPH0282814A JPH0282814A JP63235293A JP23529388A JPH0282814A JP H0282814 A JPH0282814 A JP H0282814A JP 63235293 A JP63235293 A JP 63235293A JP 23529388 A JP23529388 A JP 23529388A JP H0282814 A JPH0282814 A JP H0282814A
- Authority
- JP
- Japan
- Prior art keywords
- input
- wiring
- switch
- adjacent
- output terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 9
- 238000004549 pulsed laser deposition Methods 0.000 description 6
- 238000000899 pressurised-fluid extraction Methods 0.000 description 4
- 239000011159 matrix material Substances 0.000 description 2
- 101000972349 Phytolacca americana Lectin-A Proteins 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Logic Circuits (AREA)
Abstract
Description
【産業上の利用分野Ｊ
本発明は、ユーザが手元において任意の論理回路を電気
的にプログラム可能なプログラマブル・ロジック・デバ
イスに係り、特に、高機能で且つ省面積を実現するプロ
グラム可能な配線を備えた、プログラム可能な論理要素
を複数個含み、該論理要素をプログラム可能な配線で接
続したプログラマブル・ロジック・デバイスの改良に関
するものである。
（従来の技術］
従来より、ユーザが手元において任意の論理回路を実現
可能に構成された集積回路であるプログラマブル・ロジ
ック・デバイス（以下、ＰＬＤと称する）が知られてい
る。
このＰＬＯは、主に、ユーザ独自の論理を構築するため
のコンフィグラブルなプログラマブル論理要素（以下、
ＰＬＥと称する）と、該ＰＬＥの論理機能及び内部配線
の接続を決定するための回路機能定義用のメモリ・セル
と、装置の外部パッケージ・ビンと内部論理回路（ＰＬ
Ｅ）との間のインターフェイスを行うためのプログラマ
ブル入出カブロック（以下、ＩＯＢと称する）と、該Ｉ
ＯＢ及びＰＬＥの入出力を希望のネットワークに接続す
る配線バスを与えるためのプログラマブルな配線と、か
ら構成されている。
前記プログラマブルな配線は、従来、例えば第９図に示
す如く、各ＰＬＥ１０（及びｌ０Ｂ）の行と行の間にあ
る水平方向の配線１２と、各ＰＬＥ１０（及びｌ０Ｂ）
の列と列の間にある垂直方向の配線１４と、各配線１２
と１４の行と列の交点に配置された、隣接する列と行か
らの配線を交差させるための配線間スイッチ１６Ａを含
むスイッチング・マトリックス１６と、各配線１２．１
４のＰＬＥＩＯと対応する位置に配設された、各ＰＬＥ
ＩＯの入出力を前記配線１２又は１４に接続するための
入出力スイッチ（以下、ＩＯＢと称する）１８から構成
されていた。
前記配線間スイッチ１６Ａ及び１０８１８は、それぞれ
、回路機能定義データの各ビットで制御可能とされてお
り、これによって、任意の配線を実現するようにされて
いる。
しかしながら、従来は、各ＰＬＥＩＯの■○Ｓ１８と、
配線間スイッチ１６Ａが独立して設けられていたため、
ＰＬＥＩＯ間の遠近に拘わらず、必ず２個のｌ０８１８
と最低１個のスイッチング・マトリックス１６を通す必
要があり、スイッチ数が多く、配線が大変であると共に
、ＰＬＤの面積が太き（なってしまっていた。又、信号
が通過するゲート（又はスイッチ）が多くなるため、信
号の減衰や信頼性低下という問題もあった。
【発明が達成しようとする課題】
本発明は、前記従来の問題点を解消するべくなされたも
ので、プログラム可能な配線の最適化を図って、高機能
、省面積を実現可能なＰＬＤを提供することを目的とす
る。[Industrial Application Field J] The present invention relates to a programmable logic device that allows a user to electrically program any logic circuit at hand, and in particular, to a programmable logic device that allows a user to electrically program any logic circuit at hand. The present invention relates to an improvement in a programmable logic device that includes a plurality of programmable logic elements and connects the logic elements with programmable wiring. (Prior Art) Programmable logic devices (hereinafter referred to as PLDs), which are integrated circuits configured to enable users to realize arbitrary logic circuits at hand, have been known. Configurable programmable logic elements (hereinafter referred to as
PLE), memory cells for circuit function definition to determine logic functions and internal wiring connections of the PLE, external package bins of the device and internal logic circuits (PL
A programmable input/output block (hereinafter referred to as IOB) for interfacing with
It consists of programmable wiring for providing a wiring bus that connects the input/output of OB and PLE to a desired network. Conventionally, as shown in FIG. 9, the programmable wiring includes a horizontal wiring 12 between the rows of each PLE 10 (and 10B), and a horizontal wiring 12 between the rows of each PLE 10 (and 10B).
The vertical wiring 14 between the columns and each wiring 12
a switching matrix 16 including inter-wire switches 16A arranged at the intersections of rows and columns of and 14 for crossing wires from adjacent columns and rows; and each wire 12.1.
Each PLE arranged at a position corresponding to PLEIO of 4
It consisted of an input/output switch (hereinafter referred to as IOB) 18 for connecting the input/output of IO to the wiring 12 or 14. The inter-wiring switches 16A and 10818 can each be controlled by each bit of the circuit function definition data, thereby realizing arbitrary wiring. However, conventionally, ■○S18 of each PLEIO,
Since the inter-wiring switch 16A was provided independently,
Regardless of the distance between PLEIO, there are always two l0818
and at least one switching matrix 16, the number of switches is large, wiring is difficult, and the area of the PLD is large.In addition, the gate (or switch) through which the signal passes ), resulting in problems such as signal attenuation and decreased reliability. [Problems to be achieved by the invention] The present invention has been made to solve the above-mentioned conventional problems. The objective is to provide a PLD that is highly functional and space-saving by optimizing the PLD.
本発明は、プログラム可能な論理要素を複数個含み、該
論理要素をプログラム可能な配線で接続したプログラマ
ブル・ロジック・デバイスにおいて、前記プログラム可
能な配線が、複数の入出力端・子を有し、該入出力端子
を相互に接続するためのスイッチが内蔵された、複数の
スイッチ・ステーションと、該スイッチ・ステーション
の入出力端子の一部を、隣接する論理要素の入出力端子
に直接接続する配線と、前記スイッチ・ステーションの
入出力端子の一部を、隣接するスイッチ・ステーション
の入出力端子に直接接続する配線とを少なくとも含むこ
とにより、前記課題を達成したものである。The present invention provides a programmable logic device that includes a plurality of programmable logic elements and connects the logic elements with programmable wiring, wherein the programmable wiring has a plurality of input/output terminals/children, A plurality of switch stations with built-in switches for interconnecting the input/output terminals, and wiring that directly connects some of the input/output terminals of the switch stations to the input/output terminals of adjacent logic elements. The above object has been achieved by including at least wiring that directly connects a part of the input/output terminals of the switch station to the input/output terminals of the adjacent switch station.
発明者等が多数の設計例を調査したところ、ＰＬＥ間の
配線の大半（６割以上）が、隣接するＰＬＥ同士を結ぶ
ものであることが判明した。本発明は、このような調査
結果に基づいてなされたもので、特に隣接するＰＬＥ間
の接続を容易とすることによって、高機能及び省面積を
実現したものである。
即ち、本発明においては、プログラム可能な配線を、第
１図に示す如く、複数のスイッチ・ステーション（以下
、ＳＳと称する）２０と、該５Ｓ２０の入出力端子の一
部を、隣接するＰＬＥＩＯに直接接続する、図の斜め方
向の配線２２と、前記５Ｓ２０の入出力端子の一部を、
隣接するＳＳに直接接続する、図の上下又は左右方向の
配線２４とを含むものとしている。ここで、前記ＰＬＥ
１０の入出力°端子は、例えば第２図に示す如く、Ａ、
Ｄｉｎ、Ｂ、Ｃ，ＲＤ、Ｗ、Ｙ、に、ＤＳＺ、。
ＣＥ、Ｘを含む構成とすることができる。又、前記５Ｓ
２０の入出力端子は、例えば第３図に示す如く、Ｙｌに
１ＤＳＷ１〜Ｗ４、Ｚ、ＧＥ、Ｘ。
Ｓｌ 〜８４、Ａ、Ｄｉｎ、Ｂ、Ｅｌ 〜Ｅ４、Ｗ、Ｒ
Ｄ、Ｃ，Ｎ１〜Ｎ４を含む構成とすることができる。
従って、第４図に例示する如く、通過するスイッチ数が
、従来のＩＯＢの分だけ少なくてすむ。
特に、隣接するＰＬＥＩＯ間の接続は、５８２０を１つ
経由するだけですむ。
又、５８２０に接続される配線の信号方向が明確化し、
入出力関係がはっきりするため、従来のように例えば出
力同士を無用にスイッチする必要がない。従って、接続
不要なバスが明らかになり、回路の最適化が行われ、こ
の点でもスイッチ数を減少できる。
更に、ＰＬＥ入出力で等価なものがあれば、それらを明
確に考慮できるため、少ないスイッチ数で制約の多い構
成にした場合でも配線自由度の低下が少ない。
以上のように、本発明によれば、１０８を通す必要がな
く、スイッチ数が減少するので、配線がし易く、高機能
である。特に隣接するＰＬＥの配線は圧倒的に有利であ
る。又、スイッチ数が減少するので、省面積を実現する
ことができる。When the inventors investigated a large number of design examples, it was found that the majority (60% or more) of the wiring between PLEs connects adjacent PLEs. The present invention was made based on the results of such research, and achieves high functionality and space saving by particularly facilitating the connection between adjacent PLEs. That is, in the present invention, as shown in FIG. Directly connect the diagonal wiring 22 in the figure and a part of the input/output terminal of the 5S20,
It includes wiring 24 in the vertical or horizontal direction in the figure, which is directly connected to the adjacent SS. Here, the PLE
For example, as shown in FIG. 2, the 10 input/output terminals are A,
Din, B, C, RD, W, Y, ni, DSZ,. The configuration may include CE and X. Also, the above 5S
The 20 input/output terminals are, for example, Yl, 1DSW1 to W4, Z, GE, and X, as shown in FIG. Sl ~84, A, Din, B, El ~E4, W, R
It can be configured to include D, C, and N1 to N4. Therefore, as illustrated in FIG. 4, the number of switches to pass through can be reduced by the number of conventional IOBs. In particular, the connection between adjacent PLEIOs only needs to go through one 5820. Also, the signal direction of the wiring connected to 5820 is clarified,
Since the input/output relationship is clear, there is no need to unnecessarily switch between outputs as in the past. Therefore, buses that do not need to be connected are identified, the circuit is optimized, and the number of switches can be reduced in this respect as well. Furthermore, if there are equivalent PLE inputs and outputs, they can be clearly taken into consideration, so even if the configuration is configured with a small number of switches and many restrictions, the degree of freedom in wiring is less reduced. As described above, according to the present invention, there is no need to pass through 108 and the number of switches is reduced, so wiring is easy and highly functional. In particular, wiring of adjacent PLEs is overwhelmingly advantageous. Furthermore, since the number of switches is reduced, space can be saved.
以下、図面を参照して、本発明の実施例を詳細に説明す
る。
本実施例は、第５図に示す如く、ＰＬＥｌｏを複数個含
み、該ＰＬＥＩＯをプログラム可能な配線で接続したＰ
ＬＤにおいて、前記プログラム可能な配線が、複数の入
出力端子Ｘ、Ｗ、Ｑ、８１、Ｎ２、ＢＳＡ、Ｅ、ＣＫＳ
Ｃ，Ｎｌ、Ｎ２を有し、該入出力端子を相互に接続する
ためのスイッチ２０Ａ（第８図参照）が内蔵された複数
の５Ｓ２０と、該５Ｓ２０１７）入出力端子ノ一部Ｘ、
Ｑ、Ｂ、Ａ、ＣＫｌＣを、隣接するＰＬＥｌｏに直接接
続する、図の斜め方向の配線２２と、前記５８２０の入
出力端子の残部Ｗ、Ｓ１、Ｎ２、Ｅ、Ｎｌ、Ｎ２を、隣
接する５Ｓ２０に直接接続する、図の左右又は上下方向
の配線２４とを含むようにしたものである。
前記ＰＬＥＩＯは、例えば第６図に示す如く、汎用入力
Ａ、Ｂ、Ｃが入力される組合わせ論理回路（例えばＡＮ
Ｄ回路＞１０Ａと、該組合わせ論理回路１０Ａの組合わ
せ論理出力ＸをクロックＣＫに応じて遅延して出力Ｑを
発生するフリップフロップＩＯＢと、から構成される順
序回路とすることができる。
前記５Ｓ２０は、例えば第７図に示すようなスイッチ・
テーブルを実現するものとすることができる。第７図の
スイッチ・テーブルを実現する５８２０は、例えばＭ８
図に示す如く、多数のスイッチ２ＯＡを用いて構成する
ことができる。
本実施例においては、順序回路とされた各ＰＬＥ１０内
の機能及び５Ｓ２０内の配線を適切にプログラムするこ
とによって、任意の順序回路を実現できる。
なお、前記実施例においては、ＰＬＥｌｏが、組合わせ
論理回路１０Ａとフリップ７０ツブ１０Ｂを含む順序回
路とされていたが、ＰＬＥＩＯの種類はこれに限定され
ない。
又、５Ｓ２０が実現するスイッチ・テーブル及びその具
体的回路構成も実施例に限定されない。Embodiments of the present invention will be described in detail below with reference to the drawings. As shown in FIG.
In the LD, the programmable wiring connects multiple input/output terminals X, W, Q, 81, N2, BSA, E, CKS.
A plurality of 5S20 having built-in switches 20A (see FIG. 8) for connecting the input/output terminals to each other, and a part of the input/output terminals (X,
The diagonal wiring 22 in the figure directly connects Q, B, A, CKlC to the adjacent PLElo, and the remaining input/output terminals W, S1, N2, E, Nl, N2 of the 5820 are connected to the adjacent 5S20. This includes wiring 24 in the horizontal or vertical direction in the figure, which is directly connected to the wiring. The PLEIO is a combinational logic circuit (for example, AN
The sequential circuit can be made up of a D circuit>10A and a flip-flop IOB that generates an output Q by delaying the combinational logic output X of the combinational logic circuit 10A according to the clock CK. The 5S20 is, for example, a switch as shown in FIG.
A table can be realized. The 5820 that implements the switch table in FIG. 7 is, for example, an M8
As shown in the figure, it can be configured using a large number of switches 2OA. In this embodiment, any sequential circuit can be realized by appropriately programming the functions in each PLE 10 and the wiring in 5S20, which are formed into a sequential circuit. In the above embodiment, PLElo is a sequential circuit including the combinational logic circuit 10A and the flip 70 block 10B, but the type of PLEIO is not limited to this. Further, the switch table realized by the 5S20 and its specific circuit configuration are not limited to the embodiments.
第１図は、本発明に係るプログラマブル・ロジック・デ
バイス（ＰＬＯ）の基本的な構成を示すブロック線図、
第２図は、第１図で用いられるプログラマブル論理要素
（ＰＬＥ）の入出力端子の例を示すブロック線図、
第３図は、同じくスイッチ・ステーション（ＳＳ）の入
出力端子の例を示すブロック線図、第４図は、本発明の
詳細な説明するためのブロック線図、
第５図は、本発明に係るＰＬＤの実施例の構成を示すブ
ロック線図、
第６図は、実施例で用いられているＰＬＥの構成を示す
ブロック線図、
第７図は、実施例で用いられているスイッチ・ステーシ
ョンのスイッチ・テーブルの例を示す線図、
第８図は、前記スイッチ・テーブルに基づいたスイッチ
・ステーションの回路の例を示す回路図、第９図は、従
来のプログラム可能な配線を−含むＰＬＤの一例を示す
ブロック線図である。
１０・・・プログラマブル論理要素（ＰＬＥ）、２ｏ・
・・スイッチ・ステーション（ＳＳ）、Ｙ１ＫＳＤ１Ｗ
１〜Ｗ４、Ｚ％ＣＥ１Ｘ、Ｓ１〜Ｓ４、Ａ、ＤｉｎＳ８
．Ｅｌ 〜Ｅ４、Ｗ、ＲＤＳＣ，Ｎｌ〜Ｎ４ ・
・・入出力端子、２ＯＡ・・・スイッチ、
２２．
２４・・・配線。FIG. 1 is a block diagram showing the basic configuration of the programmable logic device (PLO) according to the present invention, and FIG. 2 shows the input/output terminals of the programmable logic element (PLE) used in FIG. FIG. 3 is a block diagram showing an example of the input/output terminals of the switch station (SS); FIG. 4 is a block diagram for explaining the present invention in detail; FIG. 5 is a block diagram showing the configuration of an embodiment of a PLD according to the present invention, FIG. 6 is a block diagram showing the configuration of a PLE used in the embodiment, and FIG. 7 is a block diagram showing the configuration of a PLE used in the embodiment. 8 is a diagram illustrating an example of a switch table of a switch station based on the switch table; FIG. 9 is a circuit diagram illustrating an example of a switch station circuit based on said switch table; FIG. FIG. 2 is a block diagram showing an example of a PLD including wiring. 10...Programmable logic element (PLE), 2o.
...Switch Station (SS), Y1KSD1W
1~W4, Z%CE1X, S1~S4, A, DinS8
．． El ~ E4, W, RDSC, Nl ~ N4 ・
...Input/output terminal, 2OA...switch, 22. 24...Wiring.
Claims (1)
要素をプログラム可能な配線で接続したプログラマブル
・ロジック・デバイスにおいて、前記プログラム可能な
配線が、 複数の入出力端子を有し、該入出力端子を相互に接続す
るためのスイッチが内蔵された、複数のスイッチ・ステ
ーションと、 該スイッチ・ステーションの入出力端子の一部を、隣接
する論理要素の入出力端子に直接接続する配線と、 前記スイッチ・ステーションの入出力端子の一部を、隣
接するスイッチ・ステーションの入出力端子に直接接続
する配線と、 を少なくとも含むことを特徴とするプログラマブル・ロ
ジック・デバイス。(1) In a programmable logic device that includes a plurality of programmable logic elements and connects the logic elements with programmable wiring, the programmable wiring has a plurality of input/output terminals, and the input/output a plurality of switch stations each having a built-in switch for interconnecting terminals; wiring for directly connecting a portion of the input/output terminals of the switch stations to the input/output terminals of adjacent logic elements; A programmable logic device comprising at least the following: wiring that directly connects a portion of the input/output terminals of a switch station to the input/output terminals of an adjacent switch station.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63235293A JP2723926B2 (en) | 1988-09-20 | 1988-09-20 | Programmable logic device |
| US07/408,523 US5003200A (en) | 1988-09-20 | 1989-09-18 | Programmable logic device having programmable wiring for connecting adjacent programmable logic elements through a single switch station |
| EP89309471A EP0360540B1 (en) | 1988-09-20 | 1989-09-19 | Programmable logic device |
| CA000611857A CA1313234C (en) | 1988-09-20 | 1989-09-19 | Programmable logic device |
| DE68917235T DE68917235T2 (en) | 1988-09-20 | 1989-09-19 | Programmable logic circuit. |
| KR1019890013545A KR940007002B1 (en) | 1988-09-20 | 1989-09-20 | Programmable logic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63235293A JP2723926B2 (en) | 1988-09-20 | 1988-09-20 | Programmable logic device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0282814A true JPH0282814A (en) | 1990-03-23 |
| JP2723926B2 JP2723926B2 (en) | 1998-03-09 |
Family
ID=16983967
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63235293A Expired - Lifetime JP2723926B2 (en) | 1988-09-20 | 1988-09-20 | Programmable logic device |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US5003200A (en) |
| EP (1) | EP0360540B1 (en) |
| JP (1) | JP2723926B2 (en) |
| KR (1) | KR940007002B1 (en) |
| CA (1) | CA1313234C (en) |
| DE (1) | DE68917235T2 (en) |
Families Citing this family (39)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5172014A (en) * | 1986-09-19 | 1992-12-15 | Actel Corporation | Programmable interconnect architecture |
| US5477165A (en) * | 1986-09-19 | 1995-12-19 | Actel Corporation | Programmable logic module and architecture for field programmable gate array device |
| US5451887A (en) * | 1986-09-19 | 1995-09-19 | Actel Corporation | Programmable logic module and architecture for field programmable gate array device |
| GB8906145D0 (en) * | 1989-03-17 | 1989-05-04 | Algotronix Ltd | Configurable cellular array |
| US5153463A (en) * | 1990-04-11 | 1992-10-06 | Kawasaki Steel Corporation | Programmable logic device having a reduced switching matrix |
| US5198705A (en) * | 1990-05-11 | 1993-03-30 | Actel Corporation | Logic module with configurable combinational and sequential blocks |
| US5073729A (en) * | 1990-06-22 | 1991-12-17 | Actel Corporation | Segmented routing architecture |
| US5191241A (en) * | 1990-08-01 | 1993-03-02 | Actel Corporation | Programmable interconnect architecture |
| US5144166A (en) * | 1990-11-02 | 1992-09-01 | Concurrent Logic, Inc. | Programmable logic cell and array |
| US5079451A (en) * | 1990-12-13 | 1992-01-07 | Atmel Corporation | Programmable logic device with global and local product terms |
| US5298805A (en) * | 1991-08-29 | 1994-03-29 | National Semiconductor Corporation | Versatile and efficient cell-to-local bus interface in a configurable logic array |
| US5338984A (en) * | 1991-08-29 | 1994-08-16 | National Semiconductor Corp. | Local and express diagonal busses in a configurable logic array |
| US5436575A (en) * | 1991-09-03 | 1995-07-25 | Altera Corporation | Programmable logic array integrated circuits |
| US5883850A (en) * | 1991-09-03 | 1999-03-16 | Altera Corporation | Programmable logic array integrated circuits |
| JPH05252025A (en) * | 1991-10-28 | 1993-09-28 | Texas Instr Inc <Ti> | Logic module and integrated circuit |
| US5254886A (en) * | 1992-06-19 | 1993-10-19 | Actel Corporation | Clock distribution scheme for user-programmable logic array architecture |
| US5294846A (en) * | 1992-08-17 | 1994-03-15 | Paivinen John O | Method and apparatus for programming anti-fuse devices |
| US5535342A (en) * | 1992-11-05 | 1996-07-09 | Giga Operations Corporation | Pld connector for module having configuration of either first PLD or second PLD and reconfigurable bus for communication of two different bus protocols |
| GB9223226D0 (en) * | 1992-11-05 | 1992-12-16 | Algotronix Ltd | Improved configurable cellular array (cal ii) |
| US5424655A (en) * | 1994-05-20 | 1995-06-13 | Quicklogic Corporation | Programmable application specific integrated circuit employing antifuses and methods therefor |
| US5495181A (en) * | 1994-12-01 | 1996-02-27 | Quicklogic Corporation | Integrated circuit facilitating simultaneous programming of multiple antifuses |
| US5552720A (en) * | 1994-12-01 | 1996-09-03 | Quicklogic Corporation | Method for simultaneous programming of multiple antifuses |
| US5646546A (en) * | 1995-06-02 | 1997-07-08 | International Business Machines Corporation | Programmable logic cell having configurable gates and multiplexers |
| US5970255A (en) | 1995-10-16 | 1999-10-19 | Altera Corporation | System for coupling programmable logic device to external circuitry which selects a logic standard and uses buffers to modify output and input signals accordingly |
| JP3486725B2 (en) * | 1995-11-28 | 2004-01-13 | 株式会社ルネサステクノロジ | Variable logic integrated circuit |
| US5744980A (en) * | 1996-02-16 | 1998-04-28 | Actel Corporation | Flexible, high-performance static RAM architecture for field-programmable gate arrays |
| US5715197A (en) | 1996-07-29 | 1998-02-03 | Xilinx, Inc. | Multiport RAM with programmable data port configuration |
| US5781032A (en) * | 1996-09-09 | 1998-07-14 | International Business Machines Corporation | Programmable inverter circuit used in a programmable logic cell |
| EP0956646B1 (en) * | 1997-01-29 | 2003-04-02 | Elixent Limited | Field programmable processor arrays |
| US5999104A (en) * | 1997-12-03 | 1999-12-07 | Ford Motor Company | Method of producing customizable automotive electronic systems |
| US6005488A (en) * | 1997-12-03 | 1999-12-21 | Ford Motor Company | User control interface architecture for automotive electronic systems |
| EP1005162A3 (en) * | 1998-11-26 | 2003-04-02 | International Business Machines Corporation | Circuit and method for implementing combinatorial logic functions |
| GB2374242B (en) * | 2001-04-07 | 2005-03-16 | Univ Dundee | Integrated circuit and related improvements |
| US7276934B1 (en) * | 2005-06-14 | 2007-10-02 | Xilinx, Inc. | Integrated circuit with programmable routing structure including diagonal interconnect lines |
| US7279929B1 (en) | 2005-06-14 | 2007-10-09 | Xilinx, Inc. | Integrated circuit with programmable routing structure including straight and diagonal interconnect lines |
| US7895560B2 (en) * | 2006-10-02 | 2011-02-22 | William Stuart Lovell | Continuous flow instant logic binary circuitry actively structured by code-generated pass transistor interconnects |
| US7710148B2 (en) * | 2008-06-02 | 2010-05-04 | Suvolta, Inc. | Programmable switch circuit and method, method of manufacture, and devices and systems including the same |
| US10719079B2 (en) | 2017-06-22 | 2020-07-21 | Nokomis, Inc. | Asynchronous clock-less digital logic path planning apparatus and method |
| KR102415012B1 (en) * | 2020-06-02 | 2022-06-29 | 강민지 | Flame reaction color comparative experiment device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61280120A (en) * | 1985-06-04 | 1986-12-10 | ジリンクス・インコ−ポレイテツド | Configurable logic array |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2430152A1 (en) * | 1978-06-29 | 1980-01-25 | Duret Christian | MODULAR NODAL NETWORK FOR SWITCHING ELECTRIC SIGNALS, ESPECIALLY TELECOMMUNICATION SIGNALS |
| US4670749A (en) * | 1984-04-13 | 1987-06-02 | Zilog, Inc. | Integrated circuit programmable cross-point connection technique |
| US4642487A (en) * | 1984-09-26 | 1987-02-10 | Xilinx, Inc. | Special interconnect for configurable logic array |
| DE3587944T2 (en) * | 1985-04-17 | 1995-04-20 | Xilinx Inc | Configurable logical matrix. |
| US4857774A (en) * | 1986-09-19 | 1989-08-15 | Actel Corporation | Testing apparatus and diagnostic method for use with programmable interconnect architecture |
| US4758745B1 (en) * | 1986-09-19 | 1994-11-15 | Actel Corp | User programmable integrated circuit interconnect architecture and test method |
| US4786904A (en) * | 1986-12-15 | 1988-11-22 | Zoran Corporation | Electronically programmable gate array having programmable interconnect lines |
-
1988
- 1988-09-20 JP JP63235293A patent/JP2723926B2/en not_active Expired - Lifetime
-
1989
- 1989-09-18 US US07/408,523 patent/US5003200A/en not_active Expired - Lifetime
- 1989-09-19 EP EP89309471A patent/EP0360540B1/en not_active Expired - Lifetime
- 1989-09-19 DE DE68917235T patent/DE68917235T2/en not_active Expired - Fee Related
- 1989-09-19 CA CA000611857A patent/CA1313234C/en not_active Expired - Fee Related
- 1989-09-20 KR KR1019890013545A patent/KR940007002B1/en not_active IP Right Cessation
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61280120A (en) * | 1985-06-04 | 1986-12-10 | ジリンクス・インコ−ポレイテツド | Configurable logic array |
Also Published As
| Publication number | Publication date |
|---|---|
| US5003200A (en) | 1991-03-26 |
| CA1313234C (en) | 1993-01-26 |
| KR900005288A (en) | 1990-04-13 |
| EP0360540A2 (en) | 1990-03-28 |
| DE68917235T2 (en) | 1994-11-17 |
| EP0360540B1 (en) | 1994-08-03 |
| KR940007002B1 (en) | 1994-08-03 |
| JP2723926B2 (en) | 1998-03-09 |
| EP0360540A3 (en) | 1990-09-12 |
| DE68917235D1 (en) | 1994-09-08 |
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