JPH0281585A - Liquid crystal display device - Google Patents

Liquid crystal display device

Info

Publication number
JPH0281585A
JPH0281585A JP23220588A JP23220588A JPH0281585A JP H0281585 A JPH0281585 A JP H0281585A JP 23220588 A JP23220588 A JP 23220588A JP 23220588 A JP23220588 A JP 23220588A JP H0281585 A JPH0281585 A JP H0281585A
Authority
JP
Japan
Prior art keywords
liquid crystal
gate signal
crystal display
display device
picture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23220588A
Other languages
Japanese (ja)
Inventor
Kazuya Fujita
和也 藤田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP23220588A priority Critical patent/JPH0281585A/en
Publication of JPH0281585A publication Critical patent/JPH0281585A/en
Pending legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Transforming Electric Information Into Light Information (AREA)

Abstract

PURPOSE:To obtain a high-quality picture with few flickers by providing a switching means to discharge charges accumulated in parastic capacity. CONSTITUTION:The charges accumulated in parasitic capacity CGS between the gate sources of a switching transistor(TR) Q1 for liquid crystal driving to be the main factor of DELTAV generation are discharged so as to made zero the difference DELTAV generated between a common electrode voltage VC and a mean value VPC of a picture element electrode voltage, and the flickers are decreased. That is, a switching means Q2 is provided between a picture element electrode 1 and a common electrode 2, a gate signal at timing different from that of the picture scanning gate signal to be supplied to a switching TR Q1 for the liquid cristal driving is added to the switching means Q2, the means Q2 is turned on, and the charges accumulated in the parastic capacity is discharged. Thus, the flickers can be decreased, and the liquid crystal display device with improved picture quality can be obtained.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は液晶テレビジョン受像機等の液晶表示装置に係
り、特にアクティブマトリクス方式の液晶表示装置の改
良に関する。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a liquid crystal display device such as a liquid crystal television receiver, and particularly relates to an improvement of an active matrix type liquid crystal display device.

(従来の技術) 従来、液晶テレビジョン受像機、液晶デイスプレィ等の
液晶表示装置に使用する液晶パネルは第4図に示すよう
に構成されている。即ら、画素電極1とこれに対向Jる
共通電極2間に液晶3を配置し、画素電極側にはガラス
基板4.偏光板5を配置し、共通電極側にはカラーフィ
ルタ6、ガラス基板7.偏光板8を配置している。
(Prior Art) Conventionally, a liquid crystal panel used in a liquid crystal display device such as a liquid crystal television receiver or a liquid crystal display is constructed as shown in FIG. That is, a liquid crystal 3 is arranged between a pixel electrode 1 and a common electrode 2 facing thereto, and a glass substrate 4 is placed on the pixel electrode side. A polarizing plate 5 is arranged, and a color filter 6 and a glass substrate 7 are arranged on the common electrode side. A polarizing plate 8 is arranged.

また、液晶の駆動回路は第5図に示すように構成されて
いる。1は画素電極、2は共通電極、3は液晶であり、
液晶3は液晶容徂CLCと液晶抵抗RLCで等価的に表
され、画素電極1に対しては映像信号vSC±VS  
(但し、■SCは信号電圧平均値。
Further, the liquid crystal drive circuit is constructed as shown in FIG. 1 is a pixel electrode, 2 is a common electrode, 3 is a liquid crystal,
The liquid crystal 3 is equivalently represented by a liquid crystal content CLC and a liquid crystal resistance RLC, and a video signal vSC±VS is applied to the pixel electrode 1.
(However, ■SC is the average signal voltage value.

VSは信号電圧である)を信号ライン9からスイッチ用
トランジスタ(例えばFET)Qlのドレイン・ソース
を通して加えるようにし、そのゲートに対しては画面走
査用ゲート信号VGIを走査ライン10を通して加える
ようにしている。更に、液晶3に対して並列的に映像信
号保持用」ンデンザCSを配置しである。
VS is a signal voltage) is applied from the signal line 9 through the drain and source of a switching transistor (for example, FET) Ql, and a screen scanning gate signal VGI is applied to its gate through the scanning line 10. There is. Further, a video signal holding sensor CS is arranged in parallel with the liquid crystal 3.

ところで、液晶表示装置では、液晶を保護するため、交
流電圧駆動が用いられる。即ち、信号ライン9に対して
は信号電圧VSの極性を順次に切り換えて印加づる。従
来、極性反転可能な最小中位である1フイールド毎に極
性反転を行っている。
Incidentally, in a liquid crystal display device, AC voltage driving is used to protect the liquid crystal. That is, the polarity of the signal voltage VS is sequentially switched and applied to the signal line 9. Conventionally, the polarity is inverted for each field, which is the smallest medium level in which the polarity can be inverted.

第6図(a) kよ交流電圧駆動における画素電極電圧
vPの変化を示したものであり、第6図(b)は交流電
圧駆動における輝度変化(ノリツカ)を丞したものであ
る。
FIG. 6(a) shows the change in the pixel electrode voltage vP in AC voltage driving, and FIG. 6(b) shows the luminance change (Noritsuka) in AC voltage driving.

第6図(a)に示すように共通電極電圧VCと画素電極
電圧の平均値vPCには差ΔVが生じるために、共通電
極電圧VCと画素電極電圧VP  (=VPC−)VS
)との差は極性反転の前後でvl又はVPとなり異なっ
てしまう。そのために、第6図(b)に示すように画面
fIli度が時間的に変化し、301」Zのフリッカと
して感じられることになる。
As shown in FIG. 6(a), since there is a difference ΔV between the common electrode voltage VC and the average value vPC of the pixel electrode voltage, the common electrode voltage VC and the pixel electrode voltage VP (=VPC-)VS
) is vl or VP before and after polarity reversal. Therefore, as shown in FIG. 6(b), the screen fIli degree changes over time, which is perceived as a 301''Z flicker.

これは、第7図に示すように液晶の光透過率が液晶両端
に印加される電圧の絶対値V (= l VP −Vc
l)だけで決定されるために、バックライトによる光の
透過伝が1フイールド毎に異なってしまうためである。
As shown in FIG. 7, the light transmittance of the liquid crystal is determined by the absolute value V (= l VP −Vc
This is because the transmission of light by the backlight differs from field to field since it is determined only by 1).

(発明が解決しようとする課題) 上記の如く、従来の液晶表示装置では、交流電圧駆動を
行うと画面輝度が時間的に変化し、フリッカとして感じ
られるという問題があった。
(Problems to be Solved by the Invention) As described above, conventional liquid crystal display devices have a problem in that when driven with an AC voltage, the screen brightness changes over time, which is perceived as flicker.

本発明は上記の問題を除去するためのもので、ノリツカ
を低減し、画面品位を向上した液晶表示装置を提供する
ことを目的とするものである。
The present invention is intended to eliminate the above-mentioned problems, and an object of the present invention is to provide a liquid crystal display device that reduces flickers and improves screen quality.

[発明の構成] (課題を解決するための手段) このため、本発明は、共通電極電圧VCと画糸電ViA
電圧の平均値vPCとの間に生じる差△Vを零にすべく
、Δ■の発生する主な要因である液晶駆動用のスイッチ
トランジスタQ1のゲート・ソース間の奇生容量CGS
に蓄積される電荷を放電させて、フリッカを低減するも
のCある。然かるに、画素電極と共通電極間にスイッチ
手段を設け、このスイッチ手段には前記液晶駆動用のス
イッチトランジスタに供給する画面走査用ゲート信号と
は異なったタイミングのゲート信号を加えてオンするこ
とにより、奇生容量に蓄積した電荷を放電させるように
構成したことを特徴としている。
[Structure of the Invention] (Means for Solving the Problems) Therefore, the present invention provides a common electrode voltage VC and a thread voltage ViA.
In order to make the difference △V between the voltage and the average voltage vPC zero, the parasitic capacitance CGS between the gate and source of the liquid crystal driving switch transistor Q1, which is the main cause of Δ■, is reduced to zero.
There is a method C that reduces flicker by discharging the charges accumulated in the screen. However, a switch means is provided between the pixel electrode and the common electrode, and this switch means is turned on by applying a gate signal having a timing different from that of the screen scanning gate signal supplied to the liquid crystal driving switch transistor. The device is characterized in that it is configured to discharge the charge accumulated in the parasitic capacitance.

(作用) 上記のΔVの発生する要因としては、主に液晶駆呻用の
スイッチトランジスタQ1のゲート・ソース間寄生容I
CGS(第5図参照)が挙げられる。即ち、CGSに電
荷が?5槓されるとすれば、CGS(VGS−ΔV) 
−ΔV (O3+CLC)但し、VGSはスイッチ用ト
ランジスタQ1のゲート・ソース闇電圧である。上式か
ら、Δ V=CGS−VGS/  (O3+CI−C+
CGS)となり、CGS及びこれに蓄積される電圧VG
Sに基づいてΔ■が生じ、フリッカの原因となる。本発
明によれば、CGSに蓄積された電荷が放電されてΔ■
が減少し、フリッカを低減づることができる。
(Function) The cause of the above ΔV is mainly the parasitic capacitance I between the gate and source of the switch transistor Q1 for driving the liquid crystal.
One example is CGS (see Figure 5). In other words, is there a charge on CGS? 5 If it is hit, CGS (VGS - ΔV)
-ΔV (O3+CLC) However, VGS is the gate-source dark voltage of the switching transistor Q1. From the above formula, ΔV=CGS-VGS/ (O3+CI-C+
CGS), and the voltage VG stored in CGS and this
Δ■ occurs based on S, causing flicker. According to the present invention, the charges accumulated in the CGS are discharged and Δ■
and flicker can be reduced.

また、同時に他の寄生容量に路積された電荷も取り除か
れるので、CGS以外の寄生容1iの影響も1刃除でき
る。
Furthermore, since charges accumulated in other parasitic capacitances are also removed at the same time, the influence of parasitic capacitances 1i other than CGS can be eliminated by one.

(実施例) 以下、図面に示した実施例に基づいて本発明を説明する
(Example) The present invention will be described below based on the example shown in the drawings.

第1図は本発明の一実施例の液晶表示装置の要部を示づ
回路図である。
FIG. 1 is a circuit diagram showing essential parts of a liquid crystal display device according to an embodiment of the present invention.

この図におい−(、第5図と同一部分には同符号をイ」
シである。第5図と異なる点は両系゛市極1と共通電極
2との間に、放電を行うためのスイッチ用トランジスタ
(例えばFET)O2を設けた魚である。そして、トラ
ンジスタQ2のグーi〜にスイッチ用トランジスタQ1
に供給する両面走査用ゲート信号とはタイミングの異な
るゲート化54 Vclを加えてオンすることにより、
CGSk:蓄積された電荷を放電するように構成しでい
る。
In this figure, the same parts as in Figure 5 are indicated by the same symbols.
It is shi. The difference from FIG. 5 is that a switching transistor (for example, FET) O2 for performing discharge is provided between the city electrode 1 and the common electrode 2 in both systems. Then, the switching transistor Q1 is connected to the goo i~ of the transistor Q2.
By adding and turning on the gate 54 Vcl, which has a different timing from the gate signal for double-sided scanning supplied to the
CGSk: Configured to discharge accumulated charges.

第2図は上記のゲート信号VG2のタイミングの一例を
示づもので、ゲート信号VG2としては画面走査用ゲー
ト信号VGIよりも速いタイミングの信号を用いている
。これは、トランジスタQ1をオンにして映像信号を画
素に古き込む直前にトランジスタQ2をオンにさせるこ
とにより、映像信号保持用コンデンサC8の電荷まで放
電させてしまうことのないようにりるためである。この
グー1〜信号VG2は、時間的に1つ前の画素の画面走
査用グー1−信号VGIを遅延回路C遅延したり或いは
1つ前のVGIをワンショット−ンルチバイブレータを
組み合わせた回路に供給するなどしC作成される。
FIG. 2 shows an example of the timing of the above-mentioned gate signal VG2, and a signal having a faster timing than the screen scanning gate signal VGI is used as the gate signal VG2. This is to avoid discharging the charge in the video signal holding capacitor C8 by turning on the transistor Q2 just before the transistor Q1 is turned on and the video signal is stored in the pixel. . These Goo 1 to signals VG2 are generated by delaying the Goo 1 signal VGI for screen scanning of the previous pixel by a delay circuit C, or by using a circuit that combines a one-shot multivibrator with the previous VGI. C is created by supplying, etc.

第3図は本発明による△V及びノリツカの改色効宋を承
りグラフである。第3図(a)(ま共通電殉電月VCと
画木電極ih圧の平均値■PCとの間にI4じるXΔV
の時間的変化を示している。従来のようにトランジスタ
Q2が無ければ、奇生容量に蓄積される電イIjにより
、Δ■(よ時間と共に次第に増加りる〕〕−ブとなり、
本発明のようにトランジスタQ2による放電を行うと、
Q2がオン覆る毎にΔは零に低減される。第3図(b)
はフリッカ値(ちらつき度合い)の時間的変化を承りも
のぐ、トランジスタQ2の有無によっU(a)と同様な
変化が得られ、本発明によつC顕汎なフリッカ低減幼果
を得ることができる。
FIG. 3 is a graph showing the effect of color modification of ΔV and Noritsuka according to the present invention. Figure 3 (a) (Average value of common electric power discharge month VC and drawing electrode ih pressure ■ PC
It shows the change over time. If there were no transistor Q2 as in the conventional case, the electric current Ij accumulated in the parasitic capacitance would result in Δ■ (which gradually increases with time) -b,
When discharging is performed by transistor Q2 as in the present invention,
Each time Q2 turns on, Δ is reduced to zero. Figure 3(b)
The change in the flicker value (degree of flicker) over time can be obtained depending on the presence or absence of the transistor Q2, and the present invention can obtain a significant flicker reduction result. Can be done.

[発明の効果1 以上述べたように本発明によれば、奇生容量に蓄積され
た電荷を取り除くことができるので、寄生容量の影7り
を軽減することができ、フリッカの少ない品位の高い画
面を提供できる。また、液晶材料の不均一性や液晶駆動
用トランジスタ以外の寄生容量による影響も排除できる
利点がある。
[Effect of the Invention 1] As described above, according to the present invention, the charge accumulated in the parasitic capacitance can be removed, so that the shadow of the parasitic capacitance can be reduced, and a high-quality product with less flicker can be produced. Screens can be provided. Further, there is an advantage that the influence of non-uniformity of the liquid crystal material and parasitic capacitance of transistors other than the liquid crystal driving transistor can be eliminated.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の液晶駆動装置の要部を示1
回路図、第2図は第1図の放電用スイッチl−ランラス
タをオンさせるゲート信号のタイミングを説明づる説明
図、第3図11本発明によるΔV及びフリッカの改善効
果を説明する説明図、第4図は液晶パネルの構造を概略
的に承り断面図、第5図は従来の液晶駆動回路の回路図
、第6図は従来の交流電圧駆動によるフリッカ発生の原
理を説明する説明図、第7図は印加電圧に対する液晶の
光透過率を示すグラフである。 1・・・画素電極、2・・・共通電極、3・・・液晶、
9・・・信号ライン、10・・・走査ライン、Ql・・
・液晶駆動用スイッチトランジスタ、Q2・・・放電用
スイッチ1〜ランジスタ、VGI・・・画面走査用ゲー
ト信号、 VO2・・・Q2のゲート信号。
FIG. 1 shows the main parts of a liquid crystal driving device according to an embodiment of the present invention.
2 is an explanatory diagram illustrating the timing of the gate signal that turns on the discharge switch l-run raster shown in FIG. 1; FIG. Figure 4 is a cross-sectional view schematically showing the structure of a liquid crystal panel, Figure 5 is a circuit diagram of a conventional liquid crystal drive circuit, Figure 6 is an explanatory diagram illustrating the principle of flicker generation by conventional AC voltage drive, and Figure 7. The figure is a graph showing the light transmittance of liquid crystal versus applied voltage. 1... Pixel electrode, 2... Common electrode, 3... Liquid crystal,
9...Signal line, 10...Scanning line, Ql...
- Switch transistor for liquid crystal drive, Q2...discharge switch 1 to transistor, VGI...gate signal for screen scanning, VO2...gate signal for Q2.

Claims (1)

【特許請求の範囲】 画素電極とこれに対向する共通電極間に液晶層を挟み、
画素電極に対しては映像信号を信号ラインからスイッチ
用トランジスタのドレイン・ソースを通して加え、その
ゲートに対して走査ラインから画面走査用ゲート信号を
加えるようにした液晶表示装置において、 前記画素電極と共通電極間に設けて、オン動作によって
寄生容量に蓄積した電荷を放電させるスイッチ手段と、
前記画面走査用ゲート信号とは異なつたタイミングのゲ
ート信号を発生し、前記スイッチ手段をオンさせるゲー
ト信号発生手段とを具備したことを特徴とする液晶表示
装置。
[Claims] A liquid crystal layer is sandwiched between a pixel electrode and a common electrode opposite thereto,
In a liquid crystal display device in which a video signal is applied from a signal line to a pixel electrode through the drain and source of a switching transistor, and a screen scanning gate signal is applied from a scanning line to the gate thereof, the pixel electrode is common to the pixel electrode. A switch means provided between the electrodes and discharging the charge accumulated in the parasitic capacitance by turning on the switch means;
A liquid crystal display device comprising gate signal generating means for generating a gate signal having a timing different from the screen scanning gate signal and turning on the switch means.
JP23220588A 1988-09-19 1988-09-19 Liquid crystal display device Pending JPH0281585A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23220588A JPH0281585A (en) 1988-09-19 1988-09-19 Liquid crystal display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23220588A JPH0281585A (en) 1988-09-19 1988-09-19 Liquid crystal display device

Publications (1)

Publication Number Publication Date
JPH0281585A true JPH0281585A (en) 1990-03-22

Family

ID=16935634

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23220588A Pending JPH0281585A (en) 1988-09-19 1988-09-19 Liquid crystal display device

Country Status (1)

Country Link
JP (1) JPH0281585A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05150270A (en) * 1991-05-21 1993-06-18 Semiconductor Energy Lab Co Ltd Digital image display method of electrooptic device using thin film transistor
EP0605846A1 (en) * 1992-12-25 1994-07-13 Sony Corporation Active matrix liquid crystal display device
EP0614167A1 (en) * 1993-03-04 1994-09-07 Tektronix, Inc. Electrode shunt in plasma channel
JP2012133046A (en) * 2010-12-20 2012-07-12 Samsung Mobile Display Co Ltd Display device and driving method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05150270A (en) * 1991-05-21 1993-06-18 Semiconductor Energy Lab Co Ltd Digital image display method of electrooptic device using thin film transistor
EP0605846A1 (en) * 1992-12-25 1994-07-13 Sony Corporation Active matrix liquid crystal display device
US5448384A (en) * 1992-12-25 1995-09-05 Sony Corporation Active matrix liquid crystal display device having discharge elements connected between input terminals and common terminal
KR100276615B1 (en) * 1992-12-25 2001-01-15 이데이 노부유끼 Active matrix liquid crystal display and its driving method
EP0614167A1 (en) * 1993-03-04 1994-09-07 Tektronix, Inc. Electrode shunt in plasma channel
JP2012133046A (en) * 2010-12-20 2012-07-12 Samsung Mobile Display Co Ltd Display device and driving method

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