JPH0281228A - Address determining system for branch instruction in assembler - Google Patents

Abstract

PURPOSE:To shorten a processing time by eliminating a no-operation instruction and updating a downward branch instruction text linked with a label text which is updated together with a downward text, when a downward branch instruction outputted temporarily by a first machine language is changed to a second machine language. CONSTITUTION:An address determining part 3 sets successively a branch destination address of a branch instruction which is brought to downward branch to the label concerned, and when a downward branch instruction which is changed to a second machine language 6 from a first machine language (as for word length, a first machine language > a second machine language) exists therein, a no-operation instruction NOP is eliminated and a downward text 2 is all updated from its downward branch instruction. Subsequently, from its downward branch instruction, a label text 13 is detected successively and a branch address of the downward branch instruction is set. In such a way, since it is unnecessary to verify a text having no relation to an elimination of the no-operation instruction NOP, a machine language from which the no- operation instruction is eliminated can be outputted quickly.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to an address determination method for a branch instruction in an assembler. A text creation section that translates a program and creates text with the purpose of removing non-operational instructions inserted when the program is changed to a small machine language, and an address determination section that resolves undetermined addresses based on the text. The text of the downward branch instruction, which branches one step downward, is translated into the first and second machine language, which have different machine language lengths depending on the address width with the branch destination label. Temporarily output the large first machine language,
In an address determination method for a branch instruction in an assembler that allocates a non-action instruction to the area that remains when changing to the second machine language when determining an address, a linkage information storage area is provided for each downward branch instruction text and label text, and the program A text creation unit that creates text corresponding to a step, stores linkage information in the linkage information storage N area, and links downward branch instruction text to the same label sequentially from the label text; is detected, the branch destination address of the downward branch instruction is determined based on the linkage information, and if there is a downward branch instruction that has been changed to the second machine language, the no-operation instruction is deleted and the text below the branch instruction is updated. and an address determination unit that updates the set downward branch instruction text linked to the updated label text, and the downward branch instruction tentatively output in the first machine language is changed to the second machine language. When the no-action instruction is deleted, the downward branch instruction text linked to the updated label text is updated together with the text below.

[Industrial application field]

The present invention relates to an assembler that translates processor instructions, and more particularly to a downward branch address determination method.

The address of the downward branch in the assembler is 2PASS
This problem is solved using the (pass) method.

That is, the machine language and the label address of the branch destination are determined in the first pass, and the branch destination address of the undetermined downward branch instruction is resolved in the second bus.

However, for example, Intel microprocessor 808
6 <, the JMP instruction is short J? due to the address width (hereinafter referred to as offset) from the branch destination. IP instruction (2-byte instruction) or long J? When one of the IP instructions (3-byte instructions) is translated into machine language, setting the downward branch JMP instruction in the second pass changes the machine language length and affects the determined address of the other instruction. .

For this reason, conventionally, a long instruction is provisionally output in the lth pass, and a short J? If you change to IP instruction, 1 will remain.
Bytes are allocated to NOP instructions (no operation), which results in longer programs, increased memory capacity, and longer operating times.

Therefore, there is a need for a branch instruction address determination method that deletes this NOP instruction.

[Conventional technology]

The conventional example will be explained using the following source program example (assembler language for Intel processor 8086).

A: JMPB MOV^χ, BX MP A B: The operation of the assembler based on this input source is as follows.

(1st pass) 11) Register label A.

(21J?IPB does not appear on the source because label B does not appear on the source, so the long JMP instruction (E9X
XXX) is temporarily output.

(3) Output NOV machine language.

(4) Since the address of JMPA has been resolved, the offset is calculated and a short JMP instruction (EBXX) is output.

(5) Register label B.

As a result of the above, 0000 A 0000 t’9XXXX 0003 89t3 0005 E[IF9 0007 B becomes.

(2nd pass) Resolve the unresolved address of JMP B (E9XXXX). Since the offset is 1 byte or less, (Short JMP instruction EBO5) + (NOP
90). As a result, 0000 A 0000 EBO590 000389C3 0005HBF9 0007 B.

[Problem to be solved by the invention]

When the offset is calculated in the second pass and the command is changed to a short JMP command, the remaining 1 byte is conventionally assigned to the N-go command, but this has no operation and is a useless command.

For this reason, it may be possible to delete this NOP, but
By deleting a certain NOP, a long P instruction may become a short JMP instruction, and this change may cause other long JMP instructions to become short JMP instructions, so the final address is determined. The problem is that the address must be reset by repeatedly searching for the relevant instruction from the beginning to the end of the program until it is executed, which increases the processing time of the assembler.

In view of the above problems, it is an object of the present invention to provide a simple address determination method for a branch instruction in an assembler that determines an address by deleting NOPs.

[Means to solve the problem]

In order to achieve the above object, the branch instruction address determination method in the assembler of the present invention is as shown in the assembler block diagram of the embodiment in FIG.
11) and label text I-(13), respectively, are provided with a link information storage area (14), and the text (2) corresponding to each program step is provided.
a text creation unit (1) that creates a linkage information storage area (14), stores linkage information in the linkage information storage area (14), and links downward branch instruction text (11) to the same label sequentially from the label text (13); The label text (1
3) and determines the branch destination address of the downward branch instruction based on the linkage information, and if there is a downward branch instruction changed to the second machine language (6), delete the no-operation instruction and execute the branch instruction. An address determination unit (3) is provided which updates the lower text (2) and also updates the set downward branch instruction text (11) linked to the updated label text (13).

[For production]

When the machine word length is changed, the only instruction that affects address determination among the instructions above that instruction is the downward branch instruction to the label below the changed instruction. Then, only this downward branch instruction is subject to update.

For this reason, a downward branch instruction text 11 having a link information storage area 14 and a label text 13 are provided, and when text 2 is created, the text creation unit 1 selects the downward branch instruction text 11 that branches to the same label from the label text 13. Link sequentially.

According to this linkage information, the address determination unit 3 sequentially sets the branch destination address of the branch instruction to branch downward to the corresponding label, and in the address determination unit 3, the first machine language 5 (the word length is the first machine language) is set.
If there is a downward branch instruction (in the case of multiple instructions, an upper downward branch instruction) changed from the second machine language) to the second machine language 6,
The no-action instruction NOP is deleted and all text 2 below the downward branch instruction is updated, and label texts 13 are sequentially detected from the downward branch instruction to set the branch destination address of the downward branch instruction.

By deleting the no-operation instruction NOP, the upward branch instruction becomes the first
The machine language 5 may be changed to the second machine language 6, but this is reset during the text update process.

As a result of the above, since there is no need to verify text unrelated to the deletion of the no-action command NOP, machine language with the no-action command deleted can be quickly output.

〔Example〕

Embodiments of the present invention will be described in detail with reference to the drawings.

Fig. 1 is an assembler block diagram of the embodiment, Fig. 2 is a text example, Fig. 3 is a processing flowchart, and Fig. 4 is an assembler block diagram of the embodiment.
The figure is an explanatory diagram of the text creation process, Figure 5 is an explanatory diagram of the address determination process (part 1), Figure 6 is an explanatory diagram of the address determination process (part 2), and Figure 7 is an explanatory diagram of the address determination process (part 3).
).

The JMP instruction (branch instruction) of the microprocessor 8086 will be explained below as an example. Note that in this JMP instruction, the first machine language 5 is a long JMP instruction (3-byte instruction).
The second machine language 6 corresponds to a short JMP instruction (2-byte instruction).

In FIG. 1, 1 is a text creation unit that reads an assembler source program, creates text for each step according to the text format described later, and links downward branch instruction text H1 to the same label; 2 is a text that will be described later. , 3 is an address determination unit that determines unresolved addresses while deleting no-operation instructions (NOP') based on the created text 2.

Figure 2 shows text examples of various commands, and the unconditional command text 10 is MOV, ADD, PLI.
In the text of an instruction such as the SI+ instruction that can be output fixedly regardless of the address, the next machine language address is obtained by adding (text length - 2) to the machine language address of the instruction.

The downward branch instruction text 11 is obtained by adding a linkage information storage area 14 and an invalid product storage area 15 to the conventional branch instruction text. A text address is written, and two 3-byte instructions are written in the invalid storage area 15.
When changed to a byte instruction, "0bi" is written as if one byte was deleted.

Note that the invalid length area is provided so that the text address does not change even if the NOP is deleted. The next machine language address of this instruction is obtained by adding (text length - 8 - invalid length).

The upward branch instruction text 12 is the text of the JMP instruction that branches upward, the text address of the corresponding label text is entered, and, like the downward branch instruction text 11, an invalid product storage area 15 is added. The next machine language address of this instruction is obtained by adding (text length - 0 - invalid length).

Note that the machine language address is entered in the upper and lower branch instruction texts 11.12, and the branch destination address is set with the machine language address of the IP (instruction pointer, next step machine language address) label as an offset. be done.

The label text 13 is for setting the machine language address of the label, and is provided with a linkage information storage area 14.

Others, CALL instruction 1 conditional J? Instructions such as IP instructions whose machine language length does not change are not shown, but are the upper branch instruction text 12 with the invalid storage area deleted.

The operation of the assembler will be explained below with reference to FIG.

[Text creation]

Create text 2 for each step while calculating machine language addresses.

At this time, the association information storage area 14 of the downward branch instruction text 11 stores association information of the downward branch instruction text 11 to the same label upward from the label text 13, that is, the text address.

Figure 4 shows an example of the text created by the above processing.Since JMP L3 is a downward JMP instruction, a 3-byte instruction is temporarily output as machine language, and
The text address of JMP L3 sequentially above label L3 is entered and linked.

Note that a terminal symbol (FFFFFF) is written at the end of the linkage.

[Address determination]

(Search for label text 13 from the upper address of 11.

(2) Search for the downward branch instruction text l corresponding to the detected label text 13 based on the association information, and set the branch destination address.

Figure 5 corresponds to the text in Figure 4.
Since L3 is a 2-byte instruction, NOP ('90
' is applied, and "01" is written in the invalid product storage area 15.

(3) If there is a 2-byte instruction, update the machine language address of the text below this text and the branch destination address of other instructions.

In FIG. 6, since the text address 0OOOOOB is an upper short JMP instruction, the text address 000016 is calculated while calculating the machine language addresses below this instruction.
Update the text below.

As a result, in FIG. 6, the upward branch instruction (text address 0O003C) is changed from EBF2 to EBF4.

At this time, if the upper JMP instruction is changed from a 3-byte instruction to a 2-byte instruction, the subsequent text 2 is updated without inserting a NOP.

(4) Search for the label text from the text after the lower JMP instruction whose machine language length has been changed, and search for the label text (2L (31
Process.

As a result, even if it is a downward branch instruction that has already been set, the label text 13 has been updated, so the setting is performed again.

(5) If there is no change in the machine word length, determine the downward branch address for the next label.

Figure 7 shows an example where multiple JMP instructions intersect.As a result of determining the address of JMP 8■ to ■ following the label, if JMP A■ is a 2-byte instruction, JMP
Update text 2 after MP command ■ and search for label text 3 from JMP C.

Therefore, JMP B■ will be reconfigured for label 8■ that has already been set, and if JMP B■ is changed to a 2-byte instruction, text 2 will be updated based on this JMP B■. .

Normally, it is relatively rare for a 3-byte instruction to be changed to a 2-byte instruction, so the above operation causes addresses to be determined sequentially downward.

In the above embodiment, the resetting process for upward P instructions, etc. was performed in the text update process, but after updating the machine language address, the address resetting process for other instructions is performed sequentially from the text whose machine language length has been changed. When the machine language length is changed by an upper JMP instruction, the machine language is reset based on the upper JMP instruction, and when label text 1-13 is detected, the above process is performed. Furthermore, processing time can be shortened.

As described above, when a 3-byte instruction is changed to a 2-byte instruction, the verification of whether or not it is necessary to reset the address of the instructions above the instruction is performed using the text 1 of the downward branch instruction linked to the label text 13 below. Since it is only necessary to perform a search on linkage information and it can be easily searched using linkage information, addresses can be determined in a short time by eliminating non-operating instructions.

〔Effect of the invention〕

The present invention provides a fast processing method for determining addresses while deleting the area conventionally occupied by non-operating instructions when the machine word length is changed in determining the address of a downward branch. By deleting non-operational instructions, the effect of reducing the amount of memory and improving the processing speed of the program is significant.

[Brief explanation of the drawing]

Figure 1 is an assembler block diagram of the embodiment, Figure 2 is a diagram representing a text example, Figure 3 is a processing flowchart, Figure 4 is an illustration of text creation processing, and Figure 5 is an illustration of address determination processing (its 1), FIG. 6 is an explanatory diagram of the address determination process (part 2), and FIG. 7 is an explanatory diagram of the address determination process (part 3). In the figure, 1 is a text creation section, 2 is a text, 3 is an address determination section, 5 is a first machine language, a 3-byte instruction, a long JMP instruction, and 6 is a second machine language, a 2-byte instruction. Short JMP command, 10 is unconditional command text, 11
1 is a downward branch instruction text, 12 is an upward branch instruction text, 13 is a label text, 14 is a linkage information storage area, 1
5 is an invalid length storage area. Figure 3: Assembler block diagram of the embodiment Figure 1: Text example Figure 2: Text creation process illustration Figure 4: Address determination process (part 1) Figure 5: Address determination processing explanation BIE (part 1) 2) Figure 6 Address determination process explanatory diagram (Part 3) Figure 7

Claims (1)

[Scope of Claims] A text creation unit that translates a program and creates text, and an address determination unit that resolves undetermined addresses based on the text, and the machine language length is determined according to the address width with the branch destination label. Among the branch instructions to be translated into first and second machine languages that are different in length, the text of the downward branch instruction that branches downward is temporarily outputted with the first machine language (5) having a large machine language length. , in an address determination method for a branch instruction in an assembler that allocates a no-action instruction to the area remaining when changing to the second machine language (6) when determining the address, the downward branch instruction text (11) and label text (13) are respectively In addition to providing a linkage information storage area (14), the text (2) corresponding to each program step is provided.
a text creation unit (1) that creates a linkage information storage area (14), stores linkage information in the linkage information storage area (14), and links downward branch instruction text (11) to the same label sequentially from the label text (13); The label text (1
3) and determines the branch destination address of the downward branch instruction based on the linkage information, and if there is a downward branch instruction changed to the second machine language (6), delete the no-operation instruction and execute the branch instruction. an address determination unit (2) that updates the lower text (2) and also updates the set downward branch instruction text (11) linked to the updated label text (13);
3) is provided, and when the downward branch instruction provisionally output in the first machine language (5) is changed to the second machine language (6) with a smaller machine word length, the no-action instruction is deleted. A branch instruction address determination method in an assembler, characterized in that a downward branch instruction text linked to the updated label text is updated together with the downward text.