JPH0267673U - - Google Patents
Info
- Publication number
- JPH0267673U JPH0267673U JP14706788U JP14706788U JPH0267673U JP H0267673 U JPH0267673 U JP H0267673U JP 14706788 U JP14706788 U JP 14706788U JP 14706788 U JP14706788 U JP 14706788U JP H0267673 U JPH0267673 U JP H0267673U
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- wiring board
- integrated circuit
- hybrid integrated
- thick film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 5
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
第１図は本考案の一実施例の回路ブロツク図、
第２図は該一実施例の基板の縦断面図、第３図は
本考案の他の実施例の回路ブロツク図、第４図は
該他の実施例の基板の縦断面図である。
１……厚膜配線基板、２……外部端子、３……
スルーホールランド、４……電気的測定用ピン、
５……厚膜配線に搭載された能動素子、６……厚
膜配線基板内導電体層、７……厚膜集積回路の外
装樹脂。
FIG. 1 is a circuit block diagram of an embodiment of the present invention.
FIG. 2 is a longitudinal sectional view of the substrate of this embodiment, FIG. 3 is a circuit block diagram of another embodiment of the present invention, and FIG. 4 is a longitudinal sectional view of the substrate of this other embodiment. 1... Thick film wiring board, 2... External terminal, 3...
Through-hole land, 4...pin for electrical measurement,
5... Active element mounted on thick film wiring, 6... Conductive layer in thick film wiring board, 7... Exterior resin of thick film integrated circuit.
Claims (1)
素子が樹脂で封止される混成集積回路用配線基板
において、基板内の所望の位置に前記基板の他の
面に露出するスルーホール電極を有することを特
徴とする混成集積回路用厚膜配線基板。 In a wiring board for a hybrid integrated circuit in which an element is mounted on only one surface of an insulating substrate and the element is sealed with resin, a through-hole electrode exposed on the other surface of the substrate is provided at a desired position within the substrate. 1. A thick film wiring board for a hybrid integrated circuit, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14706788U JPH0267673U (en) | 1988-11-10 | 1988-11-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14706788U JPH0267673U (en) | 1988-11-10 | 1988-11-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0267673U true JPH0267673U (en) | 1990-05-22 |
Family
ID=31417136
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14706788U Pending JPH0267673U (en) | 1988-11-10 | 1988-11-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0267673U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006071292A (en) * | 2004-08-31 | 2006-03-16 | Sanyo Electric Co Ltd | Manufacturing method of circuit device |
-
1988
- 1988-11-10 JP JP14706788U patent/JPH0267673U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006071292A (en) * | 2004-08-31 | 2006-03-16 | Sanyo Electric Co Ltd | Manufacturing method of circuit device |