JPH0262981A - Delay time analyzing device - Google Patents

Abstract

PURPOSE:To improve the efficiency of designing by calculating the distribution of the delay time of each signal propagation path of a circuit and indicating timing adjustment at the initial stage of a timing test of the circuit. CONSTITUTION:Delay times of respective signal propagation paths in a network are calculated by a delay time calculation part 3 and classified by delay time zones and a delay class determination part 5 calculates the number of signal propagation paths corresponding to the classified delay times. Then a specific signal propagation path is specified and a signal propagation path 25 which has a partially common signal propagation path to the specific signal propagation path is retrieved 25. Thus, the distribution of the delay times of the respective signal propagation paths is made clear, the signal propagation path which has the common partial path to the specific signal propagation path is grasped, and the influence of the specific path upon other paths can be grasped. Therefore, which part of the circuit needs to be redesigned so as to satisfy timing restrictions can accurately by predicted and the circuit is designed with efficiency.

Description

Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) The present invention relates to a delay time analysis device that analyzes the delay time of each No. 43 propagation path in a circuit network such as a logic circuit.

(Prior Art) When designing a logic circuit, it is necessary to satisfy not only logical functions but also design constraints regarding delay time (referred to as timing constraints).

For this reason, in addition to functional verification of the circuit that has been created, an evaluation of the timing crossbar is also performed.

Conventionally, in timing verification, two terminals on a logic circuit are specified, and a delay time in a signal propagation path between these two terminals is calculated. Then, it is determined whether the calculated delay time satisfies the timing constraints, and if it does not (the signal propagation path that does not satisfy the timing constraints is called a critical path), the signal between the specified two terminals is Modify the logic circuit so that the propagation path satisfies the timing constraints. Conventionally, a method has been used to correct the timing of a logic circuit by repeating such operations for all combinations of terminals in the logic circuit.

<Problems to be Solved by the Invention> In the conventional method described above, for example, even if most of the paths in a logic circuit become critical paths and it is necessary to reconsider the design or circuit, Since the logic circuit is corrected each time a path is discovered, there is a problem in that timing correction processing that is not originally necessary is repeated, resulting in wasted processing time and processing ω.

In addition, if the critical path passes through a common subcircuit and the delay time of this common subcircuit is large and the timing constraints cannot be satisfied, only the common subcircuit should be modified to shorten the delay time. Although it is possible to satisfy the timing constraints using the common subcircuit, in the conventional method, processing is performed without knowing whether or not the critical path passes through the common subcircuit. There is a problem in that a circuit is modified and an already modified signal propagation path is re-used as a critical bus.

The present invention has been made in view of the above, and has the following objectives and
6. The purpose of the present invention is to provide a delay time analysis device that calculates the distribution of delay times of each signal propagation path in a circuit and provides timing adjustment guidelines at the initial stage of circuit timing verification to improve design efficiency. .

[Structure of the Invention] (Means for Solving the Problem) In order to achieve the above object, the delay time analysis device of the present invention searches for each signal propagation path in a circuit network, and calculates the delay time of each signal propagation path. a delay time calculation means that calculates the delay time; and a delay time calculation means that classifies each delay time calculated by the delay time calculation means into a plurality of delay time zones according to the delay time, and corresponds to each delay time classified into each delay time zone. a delay time classification means for calculating the number of each signal propagation path, a routing means for specifying a specific signal propagation path among the signal propagation paths, and a specific signal propagation path specified by the routing means. and a common route search means for searching for the ri propagation route.

(Function) The delay time analysis device of the present invention calculates the delay time of each signal propagation path in the circuit network, classifies each delay time into a plurality of delay time bands, and calculates the delay time of each signal propagation path in the circuit network. The number of signal propagation paths corresponding to each delay time is calculated, a specific signal propagation path is specified, and a signal propagation path has a partial signal propagation path that is partially common to the specified specific signal propagation path. Searching for.

(Example) Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a circuit block diagram showing the configuration of a delay time analysis device according to an embodiment of the present invention. The delay time analysis device shown in the figure includes a logic circuit data storage section 1 that stores data on the circuit configuration of a logic circuit, such as the one shown in FIG. 2, whose delay time is to be analyzed; a delay time calculation section 3 that calculates the delay time of each signal propagation path of the logic circuit stored in the section 1; and the delay time calculation section 3.
The delay time of each signal propagation path calculated by A delay class determining unit 5 calculates the delay of each signal propagation path, and the delay class determining unit 5 calculates each delay time classified into a plurality of delay time periods and each signal corresponding to each delay time. a delay time display section 7 that controls to display the number of propagation paths; a display device 9 that displays each of the classified delay times and the number of each signal propagation path via the delay time display section 7; an element delay data storage section 11 that stores delay data of each element of the circuit stored in the logic circuit data storage section 1 and supplies delay data of the multiple elements to the delay time calculation section 3; and a logic circuit data storage section The number of signal propagation paths calculated by the start point and end point data storage section 13 that stores the start point and end point data of the circuit stored in the section 1 and the delay class determining section 5 is calculated for each delay time period. A delay class data storage unit 17 stores the delay time step size and the number of delay classes when dividing the delay time into a plurality of delay time slots as described above. , the delay time calculation section 3
A delay route data storage unit 19 stores each signal propagation route calculated in , that is, delay route data together with the delay time of the route, and a delay route data storage unit 19 that stores each signal propagation route data calculated in a specific bus designation unit 23 that designates a specific signal propagation route in the specific bus designation unit 23; a specific route data storage unit 21 that stores the specific signal propagation route designated by the specific bus designation unit 23; It has a common bus search unit 25 that searches for a No. 12 propagation route that has a signal propagation route that is partially common to the specified signal propagation route that is designated and stored in the specific route data storage unit 21.

Next, as an example, the delay time of each signal propagation path of the logic circuit shown in FIG. 2 is shown in FIG. The case of analysis using the jIl extension time analysis device will be explained.

It is assumed that data regarding the connection relationship of the logic circuits shown in FIG. 2 is stored in the logic circuit data storage section 1.

The logic circuit shown in Figure 2 has input terminals A, B, C, D, E,
F and output terminals G, H.

1, and inverters (IV) ENI, EN2 . ... EN4. Two-person Kanoa circuit (NOR2) EN5. ...EN8 and two-person AND circuit (AN2) EN9゜ENIO,...
・, has EN17.

In addition, each inverter 9 used in the logic circuit in FIG.
(IV), 2-man power) 7 circuit (NOR2), 2-man AND circuit (8N2), etc. The delay time of each circuit element is stored in advance in the element delay data storage section 11 in the format shown in FIG. ing.

For the logic circuit shown in FIG. 2 stored in the logic circuit data storage section 1 in this way, the delay time calculation section 3 performs circuit analysis, searches for each signal propagation path in the logic circuit, and searches for each signal propagation path in the logic circuit. The delay time of each signal propagation path is calculated, and each calculated signal propagation path and each delay time are stored in the delay path data storage section 19. For this process, also refer to Flow 1C1~ of FIG. 3. I will explain.

First, the delay time calculation unit 3 calculates the names of all input terminals and output terminals in the circuit from the logic circuit data stored in the logic circuit data storage unit 1, and calculates the names of all input terminals and output terminals in the circuit, and It is then stored in the format shown in FIG.

Note that each signal propagation path of the searched logic circuit and the delay time of each signal propagation path are stored in the delay path data storage unit 19 in the format shown in FIG. It consists of the route, that is, the bus identification number, the delay time of the bus, the name of the circuit element of each bus L, and a specific bus search flag.

First, in the flow of FIG. 3, the repetition variable i for bus identification is set to "1", the bus identification number of the delay route data storage section 19 is set to , set its delay time to O (step 1
10.120). Then, start point and end point data storage section 1
3, one of the starting points stored as shown in FIG. =1)
rAJ is written as the element name, and j is set to 2 (step 130).

Next, it is confirmed that there is an element connected from the logic circuit data storage unit 1 to the starting point that has not been processed yet, and the ENI of the element connected to the starting point A, that is, the inverter < IV) is determined. , the inverter (IV) ENI
is not the end point (steps 140 to 160
). Inverter (IV) ENI connected to the starting point
When obtained, the delay times 3 and 5 of this inverter (IV) ENI are read out from the element delay data storage section 11 which stores them as shown in FIG.
(step 170), and add this inverter (IV) ENl to the j-th element name on the route in the delay path data storage unit 19, that is, the second element name in this case, as shown in FIG. (Step 18)
0). Then, increment j by +1 (step 190), return to step 150, and similarly, inverter (IV) ENI is next followed by two-person AND circuit (AN2) E.
N9. ENIO, ENll, ENl2゜ENl3. EN
l4. ENl5, and finally detects the route to the end point G, and stores the delayed route data storage unit 1 as shown in FIG.
9 is filled in with the names of the elements on these paths, and the delay times of each of these elements are sequentially added.

Then, when this path reaches the end point G, step 160
The process branches to step 200. After this step 200, the above-mentioned starting point A-EN9-ENIO-...E
For the bus 1 of Nl4-ENl5-end point G, another path 2 is detected by returning from the end point G side of this bus 1.

That is, in step 200, among the element names on the route of bus i stored in the delay route data storage unit 19, the element names excluding the end point and the delay time (21, 0) are assigned to the path (i+
1) Write as = 2, j = j-1 and t = t+1
Then, the process proceeds to step 230. In step 230, it is checked whether the j-th element of the element name on the path of bus 2, that is, the AND circuit EN15, is not the starting point. If it is not the starting point, the process returns to step 140. Step 140
Now, it is checked whether an unprocessed element is connected to the output side of the AND circuit EN15. However, since the output side of the AND circuit FN15 is connected only to the end point G and has already been processed, step 210 is performed. , subtract the delay time of this AND circuit EN15 from the delay time of path 2 to which the delay time of path 1 has been transferred, and delete this j-th element, AND circuit EN15, from the element name on the path of bus 2. and set j-1 to j (step 220), step 23
Go to 0. In step 230, pass 2
j-th element on the path, that is, AND circuit EN14
It is confirmed whether or not is not the starting point, and the process returns to step 140. Thereafter, by repeating such processing, a path 2 is searched for, in which the AND circuit EN14 is removed from the path 1 described above.

Further, after repeating the processes from steps 140 to 230 and searching for all routes returning from the end point G, if the process returns from the end point G to the start point, the process proceeds from step 230 to step 240, and another unprocessed start point is searched. If there is an unprocessed start point, set i+1 to 1 and return to step 120, search for a signal propagation path and calculate the delay time of the signal propagation path for all the start points in the same way, The delay route data is stored in the delay route data storage section 19 as shown in FIG.

As described above, when the search for the signal propagation path and the calculation of the delay time are completed by the delay time calculation unit 3 and are stored in the delay path data storage unit 19, these delay times are classified into a plurality of delay time bands. When the step width Jj, the number of delay time zones, and the number of Zunwara delay classes are inputted, these information is stored in the delay class data storage section 17 via the delay class determination section 5 as shown in FIG. be done. FIG. 8 shows a case where "2" is designated as the delay time step size and "13" is designated as the number of delay classes.

The delay class determination unit 5 generates the delay class stored in the delay class data storage unit 17 as shown in FIG. In addition to classifying all signal propagation paths into delay classes, the number of signal propagation paths for each delay class is calculated, and the results are written in the number-of-paths-by-delay-class storage section 15 as shown in FIG. That is, in FIG. 9, identification numbers 1 to 13 are attached to each delay class divided according to the delay time step size "2", and the minimum delay time and maximum delay are assigned for each delay time class. The number of signal propagation paths to be screened and the number of paths (all paths and specific buses) are stored corresponding to each delay class.

The process of the delay class determination unit 5 generating delay classes, calculating the number of paths for each delay class, and storing the result in the delay class number-by-bus number storage unit 15 as shown in FIG. 9 will be described next in FIG. This will be explained with reference to the flowchart.

In the flow shown in FIG. 7, first, the delay time step size m and the number n of delay classes as shown in FIG. 8 are read from the delay class data storage unit 17 (step 310). Then, the delay class number i in the delay class-specific bus number storage unit 15 is
, and write 1 to 13 as the minimum delay time as the delay class range of each delay class i.
i-1) Write J, add "monk i" to the maximum delay time, and initialize the total number of paths to O (step 3
20.330>.

Next, read the delay time tj = 21.0 of bus 1 = 1 stored in the delay route data storage unit 19 (step 340), and divide this delay time tj by the delay time step size m and add 1 to it. and the delay time t of the bus i=1, r=2
1. Identify the delay class of o (step 350). That is, tj/m 10i =21.0/2+1=11, and d-extension lath number 11 is identified. When a delay class number is identified in this way, the total number of paths in the delay class bus number storage unit 15 corresponding to the delay class number is added one by one for each identification. The above delay class identification operation and all bus addition operation are repeated for all buses stored in the delay class data storage section 17, that is, all buses i=1 to 13, and the final The total number of paths is calculated for each delay class as shown in FIG.

Once the total number of paths is determined for each delay class as described above, the stored data is displayed on the display device 9 via the delay time display section 7 from the bus number storage section 15 for each delay class. That is, as shown in FIG. 9, the number of passes for each delay class stored in the pass number storage unit 15 for each extension lath is read out, and as shown in FIG. 10, the horizontal axis corresponds to each delay class. The number of paths for each delay class is displayed as a columnar graph using the delay time step width of 2 in FIG. 8 on an orthogonal quadratic planar graph with time and the number of paths corresponding to each delay class on the vertical axis.

By considering the number of paths for each delay class displayed in this way, it is possible to accurately grasp the delay time of the circuit. Second, if the timing constraint of the logic circuit shown in the figure is 14, it can be seen at a glance from the R delay time distribution shown in FIG. 10 that there are eight critical buses.

Next, it is determined whether at least two or more buses among the critical paths detected from the delay time distribution shown in FIG. 10 as described above pass through a common partial route.

That is, as shown in FIG.
The bus numbers of one or more of the critical paths are designated via the specific bus designation unit 23 with reference to the delay route data stored in the bus 9 . For example, if you specify bus 1, the number ``1'' of this specified bus 1 will be the first
The route information is stored in the specific route data storage unit 21 in the format shown in FIG.

Next, the common bus search unit 25 searches for a bus that passes through a partial route common to the bus stored in the specific route data storage unit 21 as shown in FIG. 19, and writes the searched song to the specific bus search flag in the delay route data storage section 19 as shown in FIG.

This operation will be explained below with reference to the photo in FIG.

First, all specific bus search flags in the delay route data storage section 19 are turned off (step 410).

Then, as shown in FIG. 11, the buses stored in the specific route data storage section 21 are read out one by one, and the following processing is performed sequentially for all buses stored in the specific route data storage section 21 (1). (Step 420). In this case, only one bus 1 is stored in the specific route data storage unit 21, so this bus 1 is designated as a specific bus, and the following steps 440 and 450 are performed for this specific PASCO. Processing is done.

That is, in the next steps 440 and 450, each element included in the specific bus 1 stored in the delay path data storage section 19, that is, the inverter EN
I, AND circuits EN9.10, . . . , 15 are taken out one by one, and each element is
The target bus is checked to see if it is included in any of the buses stored in the list, and if it is included in the checked buses, a route that is partially common with the specified specific bus 1 is selected. Therefore, the specific search flag for the checked bus is turned on.

Note that in this example, only bus 1 is stored in the specific route data storage unit 21 as shown in FIG. 11, but if other buses are also stored, information about the other buses is Do the same.

As described above, a bus that has a partial common route with the critical specific bus specified by the specific bus specifying unit 23 is searched for, and the specific bus search flag is turned on for that bus as shown in FIG. Once set, the delay class determination unit 5 determines the number of paths by delay class as described above for only the buses for which the specific path search flag shown in FIG. 5 is on, according to the delay class shown in FIG. It is calculated by the same processing as steps 340 to 360 of the processing flow of the determining unit 5.

As a result, the calculated number of paths for each delay class having a partial common path with the critical specific bus is written into the number of buses for each delay class storage section 15 as the number of specific paths, as shown in FIG. In this way, the path number storage unit 15 for each delay class
The number of specific paths stored in is displayed as a columnar graph on the display device 9 via the delay time display section 7 as shown in FIG. In FIG. 13, the shaded and color-coded portions are specific buses that partially share a common route with the critical specific bus, and the non-hatched portions are all the buses described above. In this way, by color-coding the specific bus with diagonal lines and displaying it overlapping with all the paths, it is possible to compare and consider the two, and it is possible to obtain guidelines for timing verification.

For example, from the columnar graph in FIG.
Since all of the above buses are critical buses and have a common partial route with PASCO, it can be inferred that the partial circuit of bus 1 is the cause of the critical bus. Therefore, the circuit portion shown by the dotted line circle lυ in FIG. 2 can be converted into a three-person circuit (A
N3) EN18. i9 and two-person AND circuit (AN2
) By optimizing using EN20, it is expected that the delay time of the critical bus can be reduced.

FIG. 15 shows a columnar graph of the result of analyzing the logic circuit shown in FIG. 14 using the delay time analyzer of the present invention.
As can be seen from this figure, by modifying the part surrounded by the broken line in the logic circuit of Fig. 2 as shown in Fig. 14, it is possible to have the same logic function as the logic circuit of Fig. A logic circuit that satisfies constraint 14 can be formed.

a3, the present invention is not limited to the above embodiments,
For example, in the above embodiment, the delayed route data storage section 19 and the specific route data storage section 21 are provided separately, but by adding a flag indicating the specific route to the delayed route data storage section 19, it can be implemented using one storage section. It is also possible. In addition, when searching for a common bus, the bus number is specified and other buses containing the elements of the path 10 are searched as the common bus, but the common bus search is performed by specifying the element identification name instead of the bus number. If the unit 25 searches for a bus that includes an element with a specified element identification name, it is possible to search for a bus that includes a specific element, for example. Furthermore, when a certain partial circuit is changed, by storing the element identification name in that partial circuit in the specific route data storage unit 21, the delay time of the bus passing through that partial circuit can be calculated, and it is possible to actually change the circuit. It is possible to predict the delay time of the circuit after the change.

Further, in this embodiment, the range of delay times indicating the delay classes is set to the same step size, but the step size of each delay class may be changed. For example, by reducing the step size of delay classes that do not satisfy timing constraints, it is possible to know the bus distribution situation in more detail. Further, in this embodiment, the start point and end point data are automatically generated, but the designer can also freely specify the start point and end point. As a result, timing verification of the partial circuit can be performed.

[Effects of the Invention] As explained below, according to the present invention, the delay time of each signal propagation path in the circuit network is calculated, each delay time is classified into a plurality of delay time bands, and each The number of signal propagation paths corresponding to each delay time classified into delay time zones is calculated, a specific signal propagation path is specified, and a partial signal that is partially common with the specified specific signal propagation path is calculated. Since we are searching for signal propagation paths that have propagation paths, the distribution of delay times for each signal propagation path is clear, and we also know signal propagation paths that have partial paths that are common to a specific signal propagation path. Since it is possible to clearly understand the extent to which a specific route extends to other routes, it is possible to accurately and easily predict which parts of the circuit should be changed in design to meet timing constraints. It is possible to improve the efficiency of circuit design.

[Brief explanation of the drawing]

Fig. 1 is a circuit block diagram showing the configuration of a delay time analysis device according to an embodiment of the present invention; Fig. 2 is a circuit diagram showing an example of a logic circuit analyzed by the delay time analysis device of Fig. 1; 3
The figure is a flowchart showing the operation of the delay time calculation section used in the delay time analysis device shown in FIG. 1, and FIG. 5 is a diagram showing the start point and end point data, FIG. 5 is a diagram showing the delay route data stored in the delay route data storage unit used in the delay time analysis device of FIG. A diagram showing delay time data of each element stored in an element delay data storage unit used in the delay time analysis device,
FIG. 7 is a flowchart showing the operation of the delay class determining section used in the delay time analysis device of FIG. 1, and FIG.
Figure delay time analysis Sl! FIG. 9 is a diagram showing the delay time step size and the number of delay classes stored in the delay class data storage unit 17 used in the delay time analysis device shown in FIG. d stored in the section
Figure 10 is a columnar graph showing the number of buses by delay class displayed on the display device used in the delay time analysis device shown in Figure 1, and Figure 11 is a graph showing the number of buses by length class. FIG. 12 is a flowchart showing the operation of the common bus search section used in the delay time analysis device of FIG. 1; Figure 13 is a columnar graph showing the number of paths for each delay class of a specific bus displayed on the display device used in the delay time analysis device in Figure 1, and Figure 14 is a graph after adjusting the timing of the logic circuit in Figure 2. The circuit diagram of the logic circuit, FIG. 15, is a columnar graph in which the number of buses for each delay class of the logic circuit of FIG. 14 is displayed on a display device. 1...Logic circuit data storage unit 3...Delay time calculation unit 5...Delay class determination unit 7...Delay time display unit 9...Display device 15...Number of paths by delay class storage unit 17...Delay class data storage section 19...R extension route data storage section 21...Specific route data storage section 23...Specific bus designation section 25...Common path search section

Claims (2)

[Claims] (1) Delay time calculation means that searches each signal propagation path in the circuit network and calculates the delay time of each signal propagation path, and a plurality of delay times calculated by the delay time calculation means according to the delay time. delay time classification means for classifying into delay time zones and calculating the number of each signal propagation path corresponding to each delay time classified into each delay time zone; It is characterized by having a route designating means for designating a route, and a common route searching means for searching for a signal propagation route having a partial signal propagation route that is partially common to a specific signal propagation route designated by the route designation means. delay time analysis device. (2) The number of signal propagation paths corresponding to each delay time calculated by the delay time classification means and partial signal propagation paths partially common to the specific signal propagation path searched by the common path search means 2. The delay time analysis device according to claim 1, further comprising a display means for displaying the number of signal propagation paths having a delay time corresponding to the delay time period.