JPH0259611A - Absolute encoder - Google Patents

Abstract

PURPOSE:To fetch an absolute code signal having correct code contents being free from a read error at the time of inverting by detecting an absolute pattern in two parts on a rack. CONSTITUTION:On a code plate 1, a track 2 provided with an absolute pattern and a track 3 provided with an incremental pattern are provided together like concentric circles. In such a state, detection outputs of photosensors 4R and 4L are inputted to a right shift input terminal and a left shift input terminal, respectively through pulse shaping circuits 10R, 10RL. On the other hand, an A phase signal from a photosensor 5A and a B phase signal from a photosensor 5B are inputted to a direction classifying circuit 14 through pulse shaping circuits 10A, 10B, and a direction classifying signal is applied to a shift register 12. Also, from a one shot multivibrator 16, a shift clock is inputted to a shift register 12. Subsequently, binary code signals of 4 digits different in combination of '0, 1' are obtained from output terminals 20a - 20d.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an absolute encoder.

[Prior Art] Conventionally, absolute knee encoders have been disclosed in, for example, Japanese Unexamined Patent Application Publication No. 57-1987-x7szt1-q or Japanese Utility Model Application No. 60-15.
As shown in Japanese Patent No. 2916, the absolute pattern on the code plate is made into one track, a plurality of detectors are arranged in the length direction of this track, and the absolute position is detected by the combination code of the output of each detector. Magnetic or optical absolute encoders are known.

[Problems to be Solved by the Invention] In the conventional absolute encoder described above, whether magnetic or optical, the bits of the combination code are used to read the binary bits l-0, 1 of the absolute pattern. A large number of non-contact detectors are arranged on a track, but the spacing between the detectors in this arrangement requires high dimensional accuracy that corresponds to the absolute pattern of the track. Therefore, the assembly and adjustment of the encoder is extremely difficult. It contains problems that make it a difficult task. In addition, with this type of conventional absolute encoder, when the code plate is reversed, the encoder output with the correct code content cannot be obtained until a predetermined number of bits have elapsed, and this reading error occurs, making it difficult to use for bidirectional applications. is causing inconvenience.

Therefore, an object of the present invention is to solve the above-mentioned problems and inconveniences, eliminate the need for arranging a large number of detectors at predetermined intervals along a track, and detect an absolute pattern at three locations on the track. An object of the present invention is to obtain an absolute encoder which can extract an absolute code signal having correct code contents without any reading error during reversal.

[Means for Solving the Problems] The absolute encoder of the present invention includes a code plate provided with a track having an absolute pattern, a detector movable relative to the code plate in the longitudinal direction of the 1-rack. An absolute encoder comprising: first and second detectors arranged at a predetermined interval in the longitudinal direction of the track as the detectors; direction discrimination means for determining whether the relative movement is in a forward or reverse direction; Serial data from the first and second detectors, which are input separately to the shift inputs, are shifted left or right depending on the forward and reverse directions of the relative movement according to the output of the direction discrimination means, and a predetermined number of bits are shifted. The above-mentioned problem has been achieved by providing a serial/parallel data conversion means for converting into parallel data.

[Function] In the absolute encoder of the present invention, as the code plate and the detector move relative to each other, the first and second detectors detect the binary bits 0, . . . of the absolute pattern. Output the reading result of I as serial data. The direction discrimination means produces an output corresponding to the forward or reverse direction of relative movement between the code plate and the detector. When this relative movement direction is the positive direction, the serial data from the first detector is sequentially taken in by the converting means, and the data is transferred from the first detector by a right (left) shift conversion operation of the converting means in synchronization with the serial data. serial data is sequentially converted into parallel data of a predetermined number of bits and output. Furthermore, when the relative movement direction is in the opposite direction, the serial data from the second detector is sequentially taken in by the converting means, and a left (right) shift conversion operation of the converting means in synchronization with the serial data is transferred to the second detector. Serial data is sequentially converted into parallel data of a predetermined number of bits and output.

For example, if the absolute pattern of the code plate consists of a 4-bit absolute code, the first and second detectors are arranged at an interval corresponding to the 4 bits in the longitudinal direction of the track.

Generally, this interval is 2°-1X≦21+, where X is the number of scale divisions of the absolute pattern on the code plate, and λ is the pattern length (angular range of 1 bit along the track). For n that satisfies the relationship (1), an interval dimension corresponding to n·^ may be sufficient.

For example, when a 4-bit serial-in/parallel-out shift register is used as the serial/parallel data conversion means, serial data from the first detector is applied to the right shift input of the register as the relative movement in the positive direction occurs. The data is sequentially converted bit by bit into 4-bit parallel data. During this time, the second detector is detecting the 5th bit pattern with an interval of 4 bits, so it is essentially the same as always catching the data pushed out from the register in the right shift operation. It turns out. When the code plate is reversed and the relative movement direction is reversed, the direction discrimination signal from the direction discrimination means causes the serial data from the second detector to be applied to the left shift input of the shift register. or perform a left shift operation. As a result, immediately after the reversal, the data that was just pushed out of the register by the previous right shift operation or the left shift operation returns to the register in order, and the scale changes without a single bit shift when the direction is reversed. Reverse readout is achieved. Needless to say, the same applies when the relative movement in the opposite direction is reversed again in the forward direction.

The operation of the serial/parallel data conversion means is performed in synchronization with the serial data signal from the detector, and the synchronization signal for this purpose can be obtained from the detection signal of an incremental pattern of a constant pitch provided on the code plate, for example. That's fine.

In this case, a so-called A-phase output and a B-phase output whose phases are shifted by 90 degrees from each other are extracted as detection signals, and the direction discrimination means detects the phase relationship between these AB phases using a logic circuit to obtain a direction discrimination signal. Just do it.

Embodiments of the present invention will be described below with reference to the drawings.

[Embodiment] FIGS. 1(a) and 1(b) show an embodiment of the present invention in the case of an optical absolute encoder using a photoelectric conversion element as a detector.

In FIG. 1(a), a code plate 1 has a first circular track 2 provided with an absolute pattern consisting of ro and IJ bits made up of opaque parts and transparent parts, and a first circular track 2 in which the -period is divided into 16 equal parts. A second pattern is created in which each divided area is alternately made into an opaque part and a transparent part to create an incremental pattern.
A circular track 3 is arranged concentrically.

The absolute pattern formed on the circular track 2 of 'fJ1 divides the circumference into 16 parts (1 bit is π/
This is a 4-bit absolute code with 16 graduations (equivalent to 8 radians).

In the first circular track 2 of FIG. 1(a), 12
Clockwise from the hour position: four consecutive ``0'' bits due to the transparent bit, two consecutive ``1'' bits due to the opaque bit, a single ``0'' bit due to the transparent bit, and a single ``0'' bit due to the opaque bit. '1' bit, a single '0' bit due to the transparent bit, four consecutive '1' bits due to the opaque bit, two consecutive 'O' bits due to the transparent bit, and a single '0' bit due to the opaque bit. Therefore, the absolute code of this pattern is rOOOOllololllloolJ.

Here, λ is the length of one bit along the track 2, and since the number of graduations is 16 in the embodiment shown in FIG.
6=corresponds to 22.5 degrees (π/8 radians).

The inner second track 3 has an incremental pattern for obtaining the above-mentioned direction discrimination signal and a synchronization signal (clock signal) for the conversion operation, and on this track 3 there is a length dimension of exactly 1 bit. (Angular range) 16 sections corresponding to λ are arranged with alternating transparent and opaque states, forming an incremental pattern in which the entire circumference is divided into 16 sections.

The code plate 1 includes optical sensors 4R and 4L that are composed of a light source and a photoelectric conversion element that face each other with the code plate in between.

5A and 5B are combined as a detector, and the code plate 1 and these detectors perform relative rotation around a rotation axis 6. This detector includes a first optical sensor 4R and a second optical sensor 4L for reading an absolute pattern, which are arranged at a mutual spacing of 4λ along the track 2, and a first optical sensor 4R and a second optical sensor 4L, which are arranged at a mutual spacing of λ/2 along the track 3. A pair of optical sensors 5A for incremental pattern reading arranged at intervals
.

It consists of 5B.

FIG. 1(b) shows each of the optical sensors 4R, 4L and 5.
An example of a signal processing circuit for processing the detection outputs of A and 5B is shown.

That is, the detection outputs of the optical sensors 4R and 4L are waveform-shaped by the pulse shaping circuit 10R and IOL, respectively, and become serial data of an absolute pattern consisting of a rectangular wave signal, and the serial data from the optical sensor 4R is shifted to the right of the shift register 12. It is input to the input terminal, and the light sensor 4L
The serial data from is input to the left shift input terminal of the shift register 12.

On the other hand, each detection output of the A-phase signal from the optical sensor 5A and the B-phase signal from the optical sensor 5B is similarly transmitted to the pulse shaping circuit 10.
A, direction discrimination circuit 1 after waveform shaping by IOB
4, and from the direction discrimination circuit 14, the A phase signal is input to B.
The "lJ" signal is given to the shift register 12 when the phase signal is ahead of the phase signal, and the "O" signal is given to the shift register 12 when the B-phase signal is ahead of the A-phase signal. In addition, the one-shot multivibrator 16 is triggered by either of the AB phase signals, and pulses are generated at both the rising and falling edges of the signal, and the shift register 12 generates a shift clock corresponding to 16 bits divided into 16 bits per revolution of the code plate l. is being input. In this case, preferably, the timing of the rise and fall of the trigger signal of the multivibrator 16 for generating the shift clock signal is adjusted in units of minimum bits of the serial data input to the left and right shift input terminals of the shift register 12. The pulse width of the rectangular wave signal is synchronized to approximately the middle of the pulse width. This is because if the timing of loading the serial data into the shift register 12 is selected close to the rising and falling edges of the rectangular wave of the serial data, there is a high possibility that data with incorrect contents will be loaded into the shift register 12. This timing selection involves appropriately setting the phase difference between track 3 of the incremental pattern and the combination of detectors 4A and 4B of the incremental pattern with respect to the combination of track 2 of the absolute pattern and its detectors 4R and 4L. This can be easily achieved by doing this.

As described above, the shift register 12 takes in the serial data inputted to either the left or right shift input one bit at a time each time a lock pulse arrives, and stores it in the internal stage without sequentially shifting it to the right or left. This input selection and shift direction selection are performed by a direction discrimination signal from the direction discrimination circuit 14, and the shift register 12
When the direction discrimination signal is rl, it takes in the serial data from the detector 4R and performs a right shift operation, and conversely, when the direction discrimination signal is "0", it takes in the serial data from the detector 4L and shifts it to the left. Perform a shift operation. Also in this example,
Since the shift register 12 is a 4-bit one, it has four stages, and therefore, 4-bit parallel data output is obtained from the parallel output terminals 20a, 20b, 20c, and 20d of each stage at the timing of the clock pulse. A four-digit binary code signal with a different combination of ro and IJ is obtained from the four output terminals 20a to 20d for every rotation angle of π/8 radian of the code plate 1.

The state of each serial data input and the left/right shifting operation of the shift register 12 when the direction is reversed is shown in FIG. 2. In this case, if the track 2 of the code plate 1 moves to the left in the figure with respect to the fixed detector (see Fig. 1(
In a), the case where the code plate 1 rotates counterclockwise) is defined as the forward direction, and the opposite direction is defined as the reverse direction.

In FIG. 2, A, B of absolute track 2,
It is assumed that C, . . . I indicate "0" or "1". Also, as shown in the picture attached at the bottom of the absolute track 2, the shift clock pulses from the one-shot multivibrator 16 are transmitted a, b, c, . . . at timings corresponding to the bit center positions when the code plate is moving in the forward direction.
・It arrives like 1, and when moving in the opposite direction, i', h'
, g'...a.

The shift register 12 takes in serial data from the first detector 4R from the left stage according to the shift clock pulses a, b, c, . , whereas when moving in the reverse direction, shift clock pulses i', h',
g' . . . Serial data from the second detector 4L is taken in from the right stage by ao and sequentially shifted to the left. This situation is also shown in FIG. 2.

That is, in FIG. 2, the detector 4R is located at A of track 2, and the state in which A is taken into the leftmost stage of the 4 bits of the shift register 12 by clock a is the state shown in (1) in FIG. It is. As the track 2 moves in the forward direction, the contents of the stage of the shift register 12 are changed as shown in (2) of FIG. 2 due to the right shift operation based on the shift clocks b to d.

The address code corresponding to the position of the detector 4R at this time is r
It is DcBAJ. When the code plate l further moves in the positive direction, the shift clock e becomes as shown in (3), and the shift clock f becomes as shown in (4). At this time, the second detector 4L has long since taken B, which corresponds to the scale data pushed out from the shift register, onto the track 2, as shown in FIG. 2, and is outputting data B. This (4)
When the code plate is reversed and moved in the opposite direction after the state of , the shift register 12 shifts to the left shift operation by the discrimination signal from the direction discrimination circuit 14, and the second detector 4L is shifted by the shift clock f° that arrives immediately after the reversal. The data B from is taken into the rightmost stage, resulting in the state (5). Along with this movement in the reverse direction, data A and subsequent data from the detector 4L are sequentially taken in to the right stage by shift clocks e", do, etc. as shown in (6), and are shifted to the left within the register 12. .In this way, shift register 1
Correct encoder outputs can always be obtained at the output terminals 20a to 20d from each stage of the encoder.

Here, the absolute pattern will be explained. 1st
In the illustrated embodiment, since N=4 as described above, the absolute code is 2N=16 bits, and as shown in FIG. When the bits are shifted one bit at a time, the adjacent four bits have the same ro, I
The absolute pattern arrangement (absolute code) on track 2 is determined so that the coat signal of combination J is not generated.
o1101011+1001''.

Therefore, output terminal 27a is 2°, 27b is 2127c is 2°
When 227d is assigned to 23, a 4-bit absolute signal with different content is obtained for each relative rotation angle π/8 radian, and in Figure 3, the hexadecimal number corresponding to each absolute signal or the output value is appended on the right side. has been done. As you can see, if the 4 adjacent bits of the ko[ signal in Figure 3 are digitized as they are, it becomes 16 hexadecimal numbers, and this also becomes the same numerical value at each point when the code plate l is rotated once. Therefore, it can be seen that it is configured as an absolute encoder.

The sequence of the absolute code is determined as follows.

That is, when the number of bits is small, successive trials≦1↑ may be performed incorrectly, but when the number of bits increases, it may be necessary to use a computer for calculation.

To explain in the case of 4 bits as described above, for example, since there is always a case where each focus is "O", first consider a series of four "0"s ro, O, O, OJ. Then, if ``5 OJs occur in a row, the same combination will occur, so ``0
I think that after four consecutive ``1''s, there will always be a ``1''. In this way, "0" or "1" is added one after another, and the shift is sufficient so that when the bits are shifted one bit at a time in groups of four, no combinations of the same contents occur.

The results of the computer calculations are shown in FIGS. 4(a), (b), (c), and (d).

Figure 4(a) shows the absolute code for 5 bits, that is, N=5, and Figure 4(b) shows the absolute code for 6 bits, that is, N=5.
The absolute code for = 6 is shown in Figure 4 (c
) is the absolute code for 8 bits, ie N=8, and FIG. 4(C) is the absolute coat for 10 bits, ie N=8.
This is the absolute coat for case No. 10.

The absolute coats in Fig. 4(b),(c),(d) are
The last bit of a row is connected to the first bit of the next (lower) row to form a series.

When these absolute codes shown in FIG. 46 are used in a rotary encoder, the last bit of the bottom row is connected to the first bit of the first row so that they are continuous without any effll.

With such an absolute code, an absolute pattern can be realized in one track, so it is possible to obtain an absolute encoder whose size is almost the same as that of a so-called incremental encoder.

In the embodiments described above, the rotary encoder for reading rotational position was mainly explained, but the present invention can also be applied to a linear encoder for reading linear position. An absolute pattern as described above may be formed linearly on the moving code plate along the direction of relative movement. It goes without saying that the present invention is not limited to the optical encoder mentioned in the embodiments, but can be applied to an absolute encoder of any other detection method such as a magnetic type.

[Effects of the Invention] As described above, according to the present invention, the absolute pattern of the code plate is read by separate detectors at three locations on the track at predetermined intervals, and the serial data obtained at each location is read by separate detectors. , the left/right shift operation and the data acquisition end are selected depending on the forward or reverse direction of the relative movement of the detector and the code plate, and are sequentially converted into parallel data of a predetermined number of bits and output. There is no error in the encoder output, and there is no need to arrange as many detectors as the number of bits along the track at predetermined intervals to read the absolute pattern; the minimum number of detectors required is sufficient. Accordingly, it is possible to provide an absolute encoder that has a simple configuration and is relatively easy to assemble and adjust.

[Brief explanation of the drawing]

FIG. 1(a) is a schematic plan view of a date-type code plate of an optical absolute encoder according to an embodiment of the present invention, and FIG. 1(b) is a schematic plan view of a signal processing circuit for processing the detection output of the detector. A circuit diagram showing an example, FIG. 2 is an explanatory diagram showing the shift operation of the shift register, and FIG. 3 is an explanatory diagram showing the serial/parallel data conversion of read data of the absolute encoder according to an embodiment of the present invention. 4 are explanatory diagrams showing some examples of absolute codes for determining absolute patterns for obtaining absolute signals of different numbers of bits. (Explanation of symbols of main parts) 1: Code plate 2 NiDrac (Absolute) 3 NiDrac (Incremental) 4R, 4L: Optical sensor (Absolute) 5A, 5B:
Optical sensor (incremental) 6: Rotation axis 10R, L: Pulse shaping circuit 10A, B: Pulse shaping circuit 12: Shift register 14: Direction discrimination circuit 16: One-shot multivibrator 20a to d: Output terminal

Claims (1)

[Scope of Claims] An absolute encoder comprising a code plate provided with a track having an absolute pattern, and a detector movable relative to the code plate in the longitudinal direction of the track, wherein the track is used as the detector. first and second detectors arranged at a predetermined interval in the longitudinal direction; a direction discrimination means for determining whether the relative movement is in the forward or reverse direction; Serial/parallel data converting means for converting the serial data from the second detector into parallel data of a predetermined number of bits while shifting the serial data from the second detector to the left or right depending on the forward or reverse direction of the relative movement according to the output of the direction discriminating means. An absolute encoder characterized by: