JPH0256636A - Branching controller - Google Patents

Abstract

PURPOSE:To execute a branch instruction at a high speed without necessitating a complicated hardware, etc. by providing a simple register instead of a branch target cache and registering only a branch to an address being smaller than the present program counter. CONSTITUTION:When a branch destination address is smaller than a value of a program counter 4, a comparator 5 outputs a signal. On the other hand, the branch destination address is compared with a branch destination address register 7 by a comparator 10, and when the branch destination address register 7 and the branch destination address are equal to each other, this comparator 10 outputs a signal. This signal is brought to AND with a branch signal by a gate 11 and becomes a selecting signal, and this selecting signal shows a fact that the branch destination coincides with the most recent branch destination to the rear. The selecting signal is supplied to a selector 12, and selects the contents of a branch destination instruction register 9 instead of a regular instruction buffer. In such a way, an instruction of the branch destination which is fetched in advance is executed at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a branch control device used in computers and the like.

(Prior Art) Conventionally, techniques such as branch-target cache have been used in order to execute branch instructions such as combination instructions at high speed. This stores the branch destination address and instructions in a cache memory that can be accessed at high speed.
Then, when the second and subsequent branches have the same address te, the branch destination instruction is fetched from this cache.

However, the conventional technology requires complicated hardware to control the cash machine, resulting in a large and expensive device (problem to be solved by the invention). In the conventional technique, branch instructions were executed by cache control, which had the disadvantage of requiring complicated hardware.

Therefore, an object of the present invention is to provide a device that can execute branch instructions at high speed without requiring complicated hardware or the like.

[Structure of the invention]

(Means for Solving the Problems) In the present invention, in order to solve the above problems, a conductive register is provided in place of the branch target cache, and only a branch to an address smaller than the current program counter is executed. I would like to make a special note of this.

(Operation) Branch execution time becomes a problem when the same branch is executed many times in a loop. A loop is a branch to an address less than the current program counter, ie, backwards (see Figure 2). Therefore, by comparing the program counter and the branch destination address and registering a backward branch in a register as in the present invention, it is possible to execute a branch whose execution time is short at high speed. . vIj with multiple loops as shown in Figure 3
廿, since it starts from the innermost measurement loop, such F
The present invention works similarly on JA8-. If there is a non-loop branch in a loop, there will be a branch as shown in Figure 44, but since such a non-loop branch is not registered in the register, only the loop part is is accelerated. However, since a non-loop branch has a different branch destination each time, it is less likely that 1@ will pose a problem during execution compared to a loop.

(One Actual Example) A specific example of the disease will be described below with reference to FIG. 1ii.

Figure i1 is a diagram showing an embodiment of the present invention. An instruction to be normally executed is fetched from the instruction buffer 21 from memory 1, and a 0 branch branch instruction executed by the decode/execution unit 3 is processed by the branch control section in the decode/execution unit, and the branch signal and branch destination are An address is generated. The program color/ri4 is updated to the branch destination address by the branch signal.

Further, the branch target address is compared with the program counter before being updated by the comparator 5.

This comparator outputs a signal directly from the program e counter to the terminal whose branch destination address is "1". This signal is ANDed with the branch signal by gate 6, and becomes a latch signal. This latch signal indicates a backward branch. The latch signal outputs the branch destination address and the branch destination instruction after a delay of one foot by the delay device 8, respectively.
Write to register 713 and branch destination instruction register 9. On the other hand, the branch destination address is compared with the branch destination address register by comparator IO. This comparator outputs a signal when the branch destination address register and the branch destination address are equal. This signal is ANDed with the branch signal and gate 11 to become a selection signal. This selection signal indicates that the branch destination matches the most recent backward branch destination.The 1 selection signal is supplied to the selector 12, which selects the existence of the branch destination survival register instead of the normal instruction buffer. Since Nile's turn, the instruction at the branch destination, which has been punished as a fetish, is executed at high speed.

The present invention is not limited to the embodiments described above, and various modifications can be made without changing the gist thereof. For example, as shown in Figure @5, the selectors may be arranged like 112, or as shown in Figure 61, the decoding result of the instruction is stored in the decode result register 202 or the branch destination instead of the branch destination instruction itself. Decode, 'I! unregistered 2
09 may be latched and selected by the selector 212. The latter method enables high-speed execution due to one cycle of pipeline control. When branching to a pre-registered branch destination, it is necessary to use this selection signal to point the program counter to the next step. Also, 1! ! It is also necessary to increase the delay amount by one in the delay device 208.

〔Effect of the invention〕

As explained above, according to the present invention, branch instructions can be executed at high speed using simple hardware fζ.
The practical effects are extremely large.

[Brief explanation of the drawing]

@Figure 1 is a block diagram showing the configuration of the present invention, Figure 2, #c
Figures 3 and 4 are Figures 1 and 4 for detailed explanation of the present invention. Fifth. FIG. 6 is a diagram illustrating another embodiment of the present invention. l...Memory, 2...Instruction buffer, 3...Decode/execution unit% 4...Program counter,
5゜10... Comparison circuit, 6.11... AND circuit,
7... Branch destination address register, 8... Delay circuit,
9... Branch destination Chiso register, 12... Selector. Agent Patent Attorney Rules Near fI Direction
Hikaru Matsuyama 2nd figure 2nd figure 2nd figure

Claims (2)

[Claims] (1) In a device that has a memory that stores a program, a program counter that indicates the execution address of the program, and a decode/execution unit that includes a branch control function, the first step is to compare the branch destination address and the program counter. a branch destination address register that stores a branch destination address; a second comparison device that compares the branch destination address with the contents of the branch destination address register; and a branch destination that stores a branch destination instruction. instruction register and the branch destination address if the branch destination address is less than or equal to the value of the program counter.
latch control means for storing the branch destination address in a register and storing the branch destination instruction in the branch destination instruction register; and an instruction fetched from the memory when the contents of the branch destination address register and the branch destination address are equal. A branch control device comprising: selecting means for selecting an instruction in the branch destination instruction register instead of the branch destination instruction register. (2) The branch control device according to claim 1, wherein the branch destination instruction register stores a decoded instruction.