JPH0254362A - Parallel process computer - Google Patents

Abstract

PURPOSE:To improve the processing speed of a computer without complicating a bus monitor mechanism, etc., by using the memory reading and writing bases to secure the connection among plural processors and plural memory units. CONSTITUTION:When a CPU 11 gives an access to a main memory unit 12, a bus acquiring request is outputted to a bus controller 21 connected to a memory reading bus 14. Receiving this request, the controller 21 gives the bus acquiring permission to only one CPU 11. Thus this CPU 11 has a read access to the unit 12 via the bus 14. When the CPU 11 has a write access to the unit 12, the CPU 11 outputs a bus acquiring request to a bus controller 22 connected to a system bus 15 (memory writing bus). Then the controller 22 gives the bus acquiring permission to only one of several CPU 11 that outputted the bus acquring requests. Thus the permitted CPU 11 performs an access action via the bus 15.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a parallel processing computer in which a memory unit is shared by a plurality of processor units.

(Prior Art) Conventionally, a parallel processing computer has a configuration as shown in FIG. That is, on a single system bus 1,
A bus controller 2, a plurality of CPUs 3, a plurality of main memory units 4, and a plurality of I/O units perform bus acquisition control.
10 units (input/output crab units) 5 are connected.

Each CPU 3 and the plurality of main memory units 4 are connected to the system bus l via a bus interface 7.8 provided for each. A bus monitoring mechanism (not shown) of the cache memory 6 provided in each CPU 5 monitors writing to the main memory unit 4 by other CPUs or the I10 unit 5 by monitoring the system bus l. Then, the bus monitoring mechanism detects that writing to the main memory unit 4 has been performed,
and the data in the block corresponding to the write destination is
If the data is stored in the cache memory 6, the corresponding data in the cache memory B is rewritten to write data to the main memory unit 4. In this way, there is no mismatch between the contents of the main memory unit 4 and the cache memory 6.

By the way, in order to improve the processing speed in a parallel processing computer, it is possible to simply increase the number of CPUs 3.

However, in a configuration in which each CPU 3 and each main memory unit 4 are connected to a single system bus 1, read/write access to each main memory unit 4 of each CPU 3 is connected to the single system bus 1. I concentrate. For this reason, even if the number of single CPUs 3 is increased, each CPtJ3 cannot be used efficiently.

In addition, in a configuration in which there are multiple system buses 1 connecting each CPU 3 and each main memory unit 4, the bus monitoring mechanism of the cache memory 6 provided in each CPtJ 3 monitors all of the plurality of system buses provided. Since the target must be targeted, the configuration becomes significantly complicated.

(Problem to be solved by the invention) In this way, in the conventional parallel processing computer,
A method of simply increasing the number of CPUs has not been able to improve processing speed because the system bus capacity cannot be used efficiently. Further, in the method of increasing the number of system buses, there is a problem in that the bus monitoring mechanism of the cache memory provided in each processor unit becomes complicated.

The present invention has been made in view of the above points, and an object of the present invention is to provide a parallel processing computer that has a simple configuration and can improve processing speed.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a parallel processing computer including a plurality of processor units each having a cache memory and a plurality of memory units shared by the processor units. comprising first and second buses to which the and the memory unit are connected, and bus controller means for controlling the first and second buses, respectively;
Processor unit writes to memory unit.

The first bus is used when the processor unit reads from the memory unit, and the second bus is used when the processor unit reads from the memory unit.

(Function) In a parallel processing computer configured in this way, the first bus is used by each processor unit to write to each main memory unit, and the second bus is used by each processor unit to write to each main memory unit. By adopting a configuration that is used when reading from the unit, it is possible to reduce the usage rate of each bus and improve the usage efficiency of the processor unit. Furthermore, the cache memory bus monitoring mechanism provided in each processor unit only needs to monitor the first bus.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a parallel processing computer according to the same embodiment. As shown in FIG. 1, a plurality of CPU IIs and a plurality of main memory units 12 are connected to a memory read bus 14 and a memory write bus 15, respectively. Each CPU II is connected to a memory read bus 14 and a bus interface 16, and is connected to a memory write bus 15 and a bus interface 18, respectively. Main memory unit 12
is the memory read bus 14 and the bus interface 1.
7 and is connected to a memory write bus 15 and a bus interface 19. Also, each CP
The UII is provided with a character memory 20 having a bus monitoring mechanism for the memory write bus I5. The bus monitoring mechanism of the cache memory 20 monitors the memory write bus so that the main memory unit 1
2 is monitored to ensure that there is no mismatch between the contents of the main memory unit 12 and the cache memory 20. Memory read bus 1
A bus controller 21 that controls the bus 14 is connected to the memory write bus 15, and a bus controller 22 that controls the bus 15 is connected to the memory write bus 15. In addition, the memory write bus 15 includes a plurality of I10s.
Unit 23 is connected. This I10 unit 23 is an input/output interface of the computer system, and various 110 devices (not shown) are connected thereto.

The main memory unit 12 also has a memory read bus 1.
4, and when access requests from the memory write bus 15 occur at the same time, one access request is given priority,
It has the function of making the other party standby.

Next, the operation of this embodiment will be explained.

First, the case where the memory read bus 14 is used will be explained. When the CPU II performs read access to the main memory unit 12, it outputs a bus acquisition request to the bus controller 21 connected to the memory read bus 14. Upon receiving this bus acquisition request, the bus controller 21 grants bus acquisition permission to only one CPU II in response to bus acquisition requests from several CPU IIs. The CPU II, which has been given bus acquisition permission by the bus controller 21, makes read access to the target main memory unit 12 via the memory read bus 14, and abandons the memory read bus 14 after the processing is completed.

Next, the case where the memory write bus 15 is used will be explained. When the CPUIL performs write access to the main memory unit 12, when the CPU 11 performs read/write access to the I10 unit 23, and when the I10 unit 23 performs read/write access to the main memory unit 12, the CPU II or I10 unit 23
outputs a bus acquisition request to the bus controller 22 connected to the memory write bus 15. Upon receiving this bus acquisition request, the bus controller 22 grants bus acquisition permission to only one unit from among the several CPU IIs or I10 units 23 that have output the bus acquisition request. The unit that has been given bus acquisition permission performs read/write access to the target unit of the main memory unit 12 or I10 unit 23 via the memory write bus 15, and after the processing is completed, The memory write bus 15 is abandoned.

In this way, by dividing the bus connecting the CPU II and the main memory unit 12 into the memory read bus 14 and the memory write bus 15, the usage rate of each bus 14 and 15 is reduced. becomes possible. For example, if the ratio of reads and writes to the main memory unit 12 of the CPU II is equal, then the CPU II
The usage rates of the memory read bus 14 and the memory write bus 15 by I are respectively 1/2 compared to the case of a conventional single system bus. Therefore, even if the number of CPU IIs is doubled, the usage efficiency of the CPU IIs can be maintained at the same level as before. Also, write access to the main memory unit 12 is controlled by the memory write bus 15.
By concentrating on the memory write bus 15, the bus monitoring mechanism of the cache memory 20 provided in each CPU II is not complicated because it only needs to monitor the memory write bus 15.

In the above embodiment, all the I10 units 23 are connected to the memory write bus 15, but those that do not require writing to the main memory unit 12 are connected to the memory write bus 15.
Memory read bus 14 or memory write bus 1
The configuration may be such that it is connected to either side of 5.

[Effects of the Invention] As described above, according to the present invention, a plurality of processor units and a plurality of memory units shared by the processor units are connected by separate buses for memory read and memory write. By doing so, the usage rate of each bus can be reduced, so it is possible to improve the processing speed without complicating the bus monitoring mechanism or the like.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a parallel processing computer according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional parallel processing computer. 11... CPU, 12... Main memory unit, 14
...Memory read bus (second bus), 15...
Memory write bus (first bus), 20... cache memory, 21, 22... bus controller, 23
...I10 unit.

Claims (1)

Claims: A parallel processing computer comprising a plurality of processor units each having a cache memory and a plurality of memory units shared by the processor units, wherein a first a second bus; and bus controller means for controlling the first and second buses, respectively, wherein the processor unit uses the first bus when writing to the memory unit; A parallel processing computer, characterized in that the second bus is used when the processor unit reads from the memory unit.