JPH025063B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a data reproducing circuit used for reproducing digital data superimposed on, for example, a television signal.

[Technical background of the invention and its problems]

In the satellite broadcasting system, when transmitting television signals, a method has been proposed in which synchronization signals and audio signals are superimposed as digitized data 10 and transmitted within the retrace section (T), as shown in Figure 3. has been done. (AVS) is an analog television signal and (DVS) is a digitized television signal. When reproducing such digital data, the clock component is first extracted from the data portion and the clock is reproduced.
A PLL (phase locked loop) circuit is usually used for clock reproduction, and the phase of the clock component in the data and the oscillation output of the PLL circuit are compared.
The data and clock phases are made equal. Using the clock generated in this way,
As shown in FIG. 4, digital data is reproduced by sampling the data with a sampling clock at the phase position where the eye opening ratio of the data is greatest.

By the way, the clock reproduced by the PLL circuit is
The optimum phase as shown in FIG. 4 is not always achieved. For example, if the waveform is distorted due to echoes or receiver phase distortion, or
If the phase error of the PLL circuit remains,
A clock with the optimum phase cannot be obtained, and the data error rate increases. Particularly in the case of multilevel transmission as shown in FIG. 5, the horizontal spread of the eye pattern is small, so the clock phase shift becomes a big problem.

FIG. 6 shows a conventional example of a clock recovery circuit for demodulating digital data. The input signal passes through a waveform shaping filter 12 and is input to a latch circuit 13 and a clock component extraction circuit 14. The clock component extracted by the clock component extraction circuit 14 is input to the PLL circuit 15. This PLL circuit 15 generates a data clock, but the phase of this clock does not necessarily have an optimal phase relationship with the data signal as shown in FIG. Therefore, the phase of this clock is adjusted by the phase shift circuit 16 so that the rising edge of the clock is positioned at the widest point of the eye pattern.

Adjustment of the phase shift circuit 16 is performed manually during the manufacture of the receiver, but this process is a major factor in increasing costs during mass production.

Another problem is that it cannot adapt to phase shifts caused by waveform distortion due to changes in reception conditions and phase shifts caused by changes in circuitry over time. Therefore, there is a need for a clock phase control system that monitors the phase of the clock and always maintains it at the optimum phase.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a data reproducing circuit that can automatically maintain the phase of a reproducing clock for data reproducing at an optimum phase at all times.

[Summary of the invention]

In order to achieve the above object, the present invention provides a multi-value data determination circuit 24, for example, as shown in FIG.
The difference between the value of the input signal and the expected value of this input signal is determined by the subtractor 26,
6 are input to a plurality of accumulators 27 and 28 which accumulate the outputs at different phase positions. Then, from the relationship between the eye pattern and the sampling phase, it is assumed that the smallest accumulated data of the accumulators 27 and 28 is error data at a position close to the optimum sampling phase, and this is used as phase shift information of the sampling clock. It is something.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, a composite video signal is input to an input terminal 21, and this signal is quantized in an analog-to-digital converter 22. here,
The sampling clock (CKO) used in the analog-to-digital converter 22 has a frequency that is, for example, twice the transmission clock frequency of data superimposed on the video signal.

The digitized video signal is guided to a digital video processing section (not shown) and is input to a digital filter 23. This digital filter 23 is for extracting sampled data and shapes the waveform of the transmitted data.

In this case, to configure the digital filter,
A clock with a frequency at least twice that of the transmission clock is required, but since the data input here has been sampled in advance by a sampling clock (CKO) with a frequency twice that of the transmission clock,
This can be realized using a normal shaping filter (for example, cosine roll-off). The output of the digital filter 23 is input to a multi-value data determination circuit 24, where the level is determined and an estimated value of the transmission data is obtained. Next, the output data of the multi-value data determination circuit 24 and the output data of the digital filter 23 are input to a differentiator 26 to obtain difference data. The output of the differentiator 26 is then input to an accumulator 27 and an accumulator 28. In this case, the phases at which the accumulators 27 and 28 take in the difference data are the times when the clock (CKA) rises and the times when the clock (CKB) rises, respectively. The clocks (CKA) and (CKB) are obtained by dividing the previous sampling clock (CKO) into 1/2 by the flip-flop circuit 38, and their waveforms are in antiphase with each other. (See FIG. 2) The data accumulated in the accumulators 27 and 28 are judged by a comparator 29 as to whether the values are large or small. The comparator 29 determines the magnitude of the absolute values of the accumulated data (A) and (B), and selects the selector 30 so that the accumulated data with the smaller value is selected by the selector 30.
Switch. Therefore, the accumulated data with the smaller value is input to the digital-to-analog converter 31 through the selector 30. The output signal of this digital-to-analog converter 31 is input to a phase control terminal of a phase shift circuit 32 to control the phase of the sampling clock (CKO).

Further, the judgment output of the comparator 29 is also applied to a control terminal of a latch pulse selection switch 39. This latch pulse selection switch 39 is
Either one of the aforementioned clocks (CKA) and (CKB) is selected and supplied to the latch circuit 25 as a latch pulse.

For example, when the selector 30 selects the accumulated data of the accumulator 27, the latch pulse selection switch 39 selects the clock (CKA) used for the accumulator 27; When the accumulated data of the accumulator 28 is selected, the latch pulse selection switch 39 selects the accumulated data of the accumulator 28.
Select the clock (CKB) used for 8.
The latch circuit 25 latches the output data from the multi-value data determination circuit 24.

The sampling clock (CKO) is generated by a clock generation circuit using a phase locked loop. That is, from the video signal input to the input terminal 21, a clock component serving as the data reference phase is extracted by the clock component extraction circuit 33, and the extracted clock component is input to one input terminal of the phase comparator 34. Supplied. The voltage controlled oscillator 36 outputs an oscillation signal with twice the frequency of the transmission clock, and this oscillation signal is used as a sampling clock (CKO) through the phase shift circuit 32 and is also used as a 1/2 frequency divider. 37, the frequency is divided into 1/2, and the signal is supplied to the other input terminal of the phase comparator 34 mentioned above. The phase comparator 34 outputs a phase difference signal of two input signals, and this phase difference signal is smoothed by a low-pass filter 35 to become a DC voltage, which is applied to the frequency and phase control terminals of the voltage controlled oscillator 36. is input.

As mentioned above, the data reproducing circuit of the present invention is
In addition to obtaining the phase synchronization state of the system by the clock component, it also monitors the sampling data to make the data sampling phase accurate;
The difference between the sample value and a predetermined value is accumulated, and the phase control information of the sampling clock is obtained from the accumulated result.

The operating principle and effect will be explained below with reference to FIG.

Now, consider a case where the transmitted data is 4-value data. The analog waveform of the input signal forms an eye pattern as shown in FIG. 2a. Figure 2b
is a sampling clock, and d and e in the figure are the preceding clocks (CKA) and (CKB), respectively.

Assume now that the rising phase of the sampling clock (CKO) is shifted from the largest aperture position of the eye pattern as shown in the figure, and the clocks (CKA), (CKB) are The explanation will be given assuming that the rising phase position of is at the position shown in the figure. In such a case, the sample value is the expected value D ₁ ~
D None of ₄ apply. For example, at a point in time (to)
Even if D ₁ level data is sent,
The sample value of that waveform at the receiving end is shown in the figure
It will be at the level of _A1 . If the clock position is optimal, D ₁ =A ₁ and the difference should be zero. The differentiator 26 is a circuit that detects this difference.

Therefore, by detecting the difference between the sample value and the expected level (for example, D ₁ ) and controlling the phase of the sampling clock (CKO) so that this difference becomes zero, the optimal sampling phase can be set. can do. In this case, the sample point in the center of the eye pattern becomes meaningful data, but the sample points between the two eyes become indeterminate and have no meaning. Therefore, as shown in Figure 2c, every other sampling point is Point data is adopted.

Now, suppose that, for example, a sampled value (A ₁ ) is obtained at the sampling point (to). For this data, the multilevel data determination circuit 24 determines the expected value, for example, _D1 , which is closest to the sampled value ( _A1 ), and outputs the determination data value ( _D1 ) at this level. Here, the differentiator 26 performs the calculation of D ₁ -A ₁ and outputs the error signal (D ₁ -A ₁ ). The absolute value of this error signal is input into the accumulator 27 in this case. When such processing is performed one after another, the accumulated data (A) in the accumulator 27 and the accumulator 28
There will be a difference between the cumulative data (B) and the cumulative data (B).

In other words, under the phase relationship shown in Figure 2, the sample value based on the phase of the clock (CKA) is close to the correct value, and the sample value based on the phase of the clock (CKB) is almost meaningless because the eye is not open. Become. As a result, the cumulative value of the error signal at the sampling point of the clock (CKB), that is, the output of the accumulator 28, becomes a much larger value than the output of the accumulator 27, which accumulates the error signal at the approximately correct sampling point. . Therefore, the comparator 29 switches the selector 30 so that the smaller value, that is, the output of the accumulator 27, is input to the digital-to-analog converter 31, and also sets the switch 39 to select the clock (CKA). do. Therefore, a latch pulse is applied to the latch circuit 25 at a phase position where data exists. Further, a phase control signal corresponding to the error signal is obtained from the digital-to-analog converter 31, and the phase of the sampling clock (CKO) is adjusted based on this signal.
The eye is shifted to the most open position, that is, the error signal (D ₁ −A ₁ ) is zero.

The present invention is not limited to the above embodiment, and the frequency of the sampling clock (CKO) is not limited to twice the transmission data clock frequency.
It may be n times (n is any positive integer). In this case, n clocks having a period n times that of the sampling clock CKO and different phases are created, and n accumulators are prepared corresponding to each clock. Then, the smallest output of each accumulator may be selected and used as the phase control information of the sampling clock. Of course, in this case, the switch for taking out the latch pulse also has n clock input sections, any one of which can be selected. In this way, even finer phase adjustment becomes possible.

〔Effect of the invention〕

As described above, according to the present invention, the optimum phase of the sampling clock can be automatically obtained by monitoring the sampling value of the transmitted data. Therefore, even if there are variations in reception characteristics or residual phase errors in the PLL circuit, data reproduction with a low error rate can be obtained without adjustment. In addition, this circuit uses a sampling clock n times the transmission data clock in advance, so
There is no need to use a new n-times clock generation means used in the digital filter, which is effective in simplifying the configuration. Furthermore, since pulse shaping filters, multi-value judgment circuits, etc., which were conventionally made up of analog parts, are now digitized, converting them to LSI will be effective in reducing the number of parts and significantly improving reliability.

[Brief explanation of drawings]

FIG. 1 is a configuration explanatory diagram showing an embodiment of the present invention, FIG. 2 is a timing diagram shown to explain the operation of the circuit in FIG. 1, and FIG. FIGS. 4 and 5 are explanatory diagrams of the synchronization relationship between the eye pattern and the sampling clock, respectively, and FIG. 6 is an explanatory diagram of a conventional data reproducing circuit. 22...Analog-to-digital converter, 23...Digital filter, 24...Multi-value data determination circuit, 25...
Latch circuit, 26...Differentiator, 27, 28...Accumulator, 29...Comparator, 30...Selector, 31
...Digital-to-analog converter, 32...Phase shift circuit.

Claims (1)

[Claims] 1. Oscillation means for generating a basic clock having a frequency n times (n is a positive integer) a data clock of transmission data, and a clock input from the oscillation means capable of phase shifting. , a phase shift circuit that derives an output as a sampling clock; an analog-to-digital conversion means for sampling an input signal using the sampling clock to obtain an analog-to-digital conversion output; and a digital input output from the analog-to-digital conversion means. data determining means for determining the level of a signal and outputting a signal with an expected value that the signal should have; a difference device calculating a level difference between the input signal of the data determining means and the expected value signal; means for generating n clocks having a period n times that of the sampling clock and each having a different phase; each clock corresponding to the n clocks; means for determining cumulative data having the smallest absolute value among the cumulative data of the n accumulators and inputting the cumulative data to a digital-to-analog converter; A data reproducing circuit comprising means for inputting an output to the phase shift circuit as a phase shift amount control signal.