JPH0249573Y2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a sampling measurement device that samples and measures a circuit under test.The purpose of the invention is to provide sampling measurement equipment that can sample and measure a circuit under test that has zero drift without being affected by zero drift. The purpose of this invention is to provide a measuring device.

The present invention will be explained in detail below using the drawings. FIG. 1 is a block diagram showing an embodiment of a sampling measuring device according to the present invention. In FIG. 1, 1 is an oscillator that generates a reference clock with a frequency of ₀ as shown in FIG.
is an integer) to obtain the frequency as shown in Figure 2 B.
A frequency divider that generates a frequency divided pulse of ₀ /N, 3 is a pulse generator, which is triggered by the reference clock of oscillator 1 and is ON-OFF modulated by the frequency divided pulse of frequency divider 2, as shown in Fig. 2 (c). It generates pulses like this. Reference numeral 4 denotes a sampling pulse generator, which is provided with the reference clock and generates sampling pulses which are synchronized with the reference clock and delayed by a predetermined time that can be arbitrarily selected. Reference numeral 5 denotes a circuit to be measured, which sends out an electric signal that changes over time by receiving output pulses from a pulse generator at its input terminal, and is, for example, a signal transmission line. Reference numeral 6 denotes a sampler which is driven by the sampling pulse and samples and holds the output of the circuit under test 5. A synchronous rectifier 7 synchronously rectifies the output of the sampler 6 using the frequency-divided pulse. 8 is a smoother.

In such a configuration, the pulse generator 3
The reference clock shown in FIG. 2A output from the oscillator 1 and the output pulse shown in FIG. A modulated pulse as shown in Figure C is generated. When the circuit under test 5 receives this modulation pulse, the value decreases exponentially from the initial value corresponding to the input modulation pulse, as shown by the dotted line in FIG.
Sends out a repeating waveform that settles to zero within a cycle. A sampling pulse is applied from the sampling pulse generator 4 to the sampler 6. Note that this sampling pulse is generated with a delay of time t _d from the reference clock as shown in FIG. 2D. Sampler 6
is driven by a sampling pulse and samples and holds the output of the circuit under test 5 as shown in FIG. 2E. That is, the zero output e ₀ and the output e ₁ during operation of the circuit under test 5 are sampled and held. This hold value is synchronously rectified by the frequency division pulse of the frequency divider 2 in the synchronous rectifier 7 . In other words, when the output of frequency divider 2 is HIGH level, the sample hold value of sampler 6 is taken out as is without polarity inversion, and when the output of frequency divider 2 is LOW level, the sample hold value of sampler 6 is taken out with polarity inversion. and then taken out. Therefore, the output of frequency divider 2 is HIGH
When the output is at low level, the hold value e ₁ in Figure 2 E is output as is, and when the output of frequency divider 2 is at LOW level, the polarity of the hold value e ₀ (zero level value) in Figure 2 is inverted. (−e ₀ ) is output. By smoothing this output through the smoother 8, the second
A DC output (e ₁ −e ₀ ) as shown in the figure is obtained.

Note that if there is a zero drift of Δe in the circuit under test 5 and the sampler 6 as a whole (normally, zero drift changes slowly, such as between adjacent HIGH and LOW outputs of the frequency divider 2) (There is virtually no change over a short period of time)
, the output from sampler 6 is e ₁ +Δe
and e ₀ +Δe. However, the synchronously rectified and smoothed DC output becomes e ₁ +Δe−(e ₀ +Δe)=e ₁ −e ₀ , and after all, this DC output is not affected by zero drift.

If the delay time _td is gradually changed in the sampling pulse generator 4 during sampling output measurement, each point of the output waveform of the circuit under test 5 (the dotted line in Figure 2 E) can be sampled sequentially. A sampling output (DC output) corresponding to the output waveform of the circuit under test 5 can be obtained from the smoother 8. In this case, the period for sequentially changing the delay time t _d , so-called sampling scanning speed period, must be selected to be longer than one period of the frequency-divided pulse.

Note that the frequency-divided pulse is not limited to a pulse that divides the reference clock and is synchronized with it; if N is extremely large, that is, if the frequency of the frequency-divided pulse is extremely low compared to the frequency of the reference clock, the frequency-divided pulse is It may be asynchronous to the reference clock. Furthermore, if an integral type smoother is used as the smoother 8 and the frequency of the divided pulse is selected to be 1/2 of the power supply frequency, the effect of removing noise at the power supply frequency will be dramatically increased. In this case, harmonic noise becomes zero at the DC output due to synchronous rectification.

As explained above, according to the sampling measurement device of the present invention, ON--
The circuit under test is operated with an OFF-modulated modulation pulse, which causes it to output a repeating waveform intermittently, and the output of the circuit under test is sampled and held at fixed time intervals using a sampling pulse with a predetermined delay time. By synchronously rectifying the signal with the frequency-divided pulse and then smoothing it, the output waveform of the circuit under test can be sampled without being affected by the zero drift of the circuit under test and the sampler.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the sampling measuring device according to the present invention, and FIG. 2 is an operational waveform diagram of each part of the device shown in FIG. 1... Oscillator, 2... Frequency divider, 3... Pulse generator, 4... Sampling pulse generator, 5...
Circuit under test, 6... sampler, 7... synchronous rectifier, 8... smoother.

Claims (1)

[Claims for Utility Model Registration] An oscillator that generates a reference clock, and a frequency-divided pulse obtained by dividing the frequency of the reference clock to 1/N, or a frequency that is synchronous or asynchronous to the reference clock and is sufficiently lower than the frequency of the reference clock. a frequency divider that generates a pulse, a pulse generator that generates a pulse triggered by the reference clock and ON-OFF modulated by the output pulse of the frequency divider, and a pulse generator that is synchronized with the reference clock and delayed by a predetermined time. A sampling pulse generator that can generate a sampling pulse and change its delay time at a specific cycle, and a device to be measured that takes the output of this pulse generator as an input and outputs an electrical signal that changes over time in response to the input pulse. A sampler that samples and holds the output of the circuit using the sampling pulse, a synchronous rectifier that synchronously rectifies the output of the sampler using the output pulse of the frequency divider, and a smoother that smoothes the output of the synchronous rectifier. . A sampling measuring device, characterized in that the delay time of the sampling pulse generator is changed so that a value corresponding to the output waveform of the circuit under test at an arbitrary timing is obtained from a smoother.