JPH0248757A - Data communication system - Google Patents

Abstract

PURPOSE:To surely stop a DMAC so that restoring processing can be performed without delay even in the case of high speed transfer or in the case when a bus was not released by stopping the DMAC forcedly by detecting that DMA transfer is not performed within a time constant period. CONSTITUTION:A hardware timer circuit 43 is operated at every DMA transfer period by using a fact that a DMA (Direct Memory Access) response from a DMA controller (DMAC) 42 corresponds to the actual DMA transfer. When the DMA transfer is not performed within a time constant, the DMAC 42 is stopped forcedly, and the DMAC 42 and the hardware timer circuit 43 are initialized. Thus, since time supervision is performed regardless of a CPU cycle, the time supervision can be surely performed so that the DMAC can be stopped even in the case of the high speed transfer with no CPU cycle and in the case when the DMAC 42 does not release the bus for some reason, and besides, the CPU cycle need not be strictly supervised, and the restoring processing can be performed without delay.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data communication system for transferring data from a transfer source to a transfer destination using DMA.

Conventionally, communication-dedicated LSIs have often been used in data communication systems using microcomputers, and in particular,
DMA transfer needs to be used when CPU processing time is insufficient for high-speed data communication, or when reducing CPU processing associated with individual data transfers. In this case, a DMA controller is used to connect the communication-dedicated LSI and RAM.
(buffer 7 memory) without going through CPLI.
Transfer is performed, and the CPU performs batch processing on the communication data when the data communication ends due to DMA[r transfer. This results in
During data communication, the CPU does not need to perform communication processing,
The load on the CPU is reduced.

DMA transfer is performed without going through the CPU as described above (i.e.
It transfers data from a transfer source to a transfer destination (in terms of hardware), and as mentioned above, is required in communication systems that aim to reduce CPU processing.

[Conventional technology]

FIG. 5 shows a block diagram of an example of the conventional method.

In the figure, under the control of DMACl, DMA transfer is performed between RAM (buffer 7 memory) 2 and communication LSI 3, and for example, data from RAM 2 is transmitted to external communication circuit 4 via communication LSI 3, and , data from the external communication line 4 is received by the communication LSI 3 and sent to the RA.
It may be written to M2. At this time, data transfer is performed on the data bus 5 according to the address specified by DMACl. When DMAC1 is operating in this manner, DMAC1 is given the right to use the data bus 5 and address bus 6, and in this case, the CPU 7 is in a standby state. When the DMA transfer is completed, the DMAC
The CPU 7 shifts from the standby state to the operating state by the interrupt from 1, and the CPU 7 performs batch processing of communication data.

In this case, DMAC1 generally includes a transfer data word length counter, a memory/10 access interface,
FIFO buffer? It has a built-in hardware logic (first-in, first-out buffer, etc.), and operates according to the transfer data word length (for example, 10 bytes) designated by the CPU 7.

In this way, DMACl only transfers a preset data word length, so there is a particular problem when transmitting data when the data word length is known in advance (data transmission from RAM 2 to external communication line 4 via communication LDI 3). However, it cannot be used when receiving data from an external communication line 4 whose data word length is unknown.

That is, if the actual received data word length becomes shorter than the data word length preset in DMAC1 due to a malfunction on the communication line 4, DMACl remains in a processing standby state even after all received data is completed, and DMA transfer is not performed. does not end, therefore
A problem arises in that the bus is not released and data processing by the CPU cannot be started forever, causing the system to deadlock.

Therefore, conventionally, 1 byte of DMA transfer and 1 byte of next DMA transfer
CPL in the period (CPU cycle) between bytes
The software timer of I7 is operated to monitor time, and when DMA transfer is no longer performed at a predetermined timing (timeout), a reset command is issued to DMACl to stop DMAC1. If you do this, the DMA
C1 releases the bus, data processing is performed by CPU 7, and the system does not deadlock.

(Problem to be solved by the invention) This method of operating the software timer of C'PLI7 using CPU cycles to monitor time does not require CPU cycles when the data transfer interval is short, such as in the case of high-speed transfer. Therefore, there was a problem that the software timer could no longer operate and the DMAC1 could not be stopped. Further, even if the DMA transfer is completed, if DMACl does not release the bus for some reason, there will be no CPU cycles, so there is a problem that DMACl cannot be stopped in the same way as described above.

Furthermore, since this method waits for the DMA transfer period and then performs CPU processing, it is not suitable for systems that require strict monitoring of CPU cycles or systems that must respond quickly to recovery processing, etc. There were some issues that were appropriate.

The present invention reliably stops the DMAC and allows the CPU to process the data, especially in high-speed transfers, when the data to be transferred is shorter than the data word length preset in the DMAC and the DMAC does not complete its operation. The purpose is to provide a data communication method.

[Means to solve the problem]

FIG. 1 shows a block diagram of the principle of the present invention. In the same figure, 42
A DMAC controls the transfer of data from the transfer source circuit 40 to the transfer destination circuit 41 by DMA transfer at a predetermined cycle. 43 is a hardware timer circuit that is activated every DMA transfer cycle and is set with a time constant longer than the DMA transfer cycle, and when DMA transfer is not performed within the time constant period, it detects this and forces the DMAC 42. stop.

44 is a control means, which controls the DMAC 42 and the hardware timer circuit 4 by detection by the hardware timer circuit 43.
3 and performs re-communication processing.

[Effect]

In the present invention, the DMA response from the DMAC 42 is
Utilizing the fact that it supports MA transfer, the hardware timer circuit 43 is activated every DMA transfer cycle. If DMA transfer is not performed within a time constant, the DMAC 42 is forcibly stopped, and the DMAC 42 and hardware timer circuit 4
Initialize 3. In this way, time monitoring is performed regardless of CPU cycles, so even in the case of high-speed transfer without CPU cycles, or even if the DMAC 42 does not release the bus for some reason, the time can be reliably monitored and the DMA
C can be stopped, there is no need to closely monitor CPU cycles, and recovery processing can be performed quickly.

〔Example〕

FIG. 2 is a block diagram of an embodiment of the method of the present invention, FIG. 3 is an operation flowchart of the CPLJ in FIG. 2, and FIG. 4 is a timeout detection time chart. Here, high-speed G P I B (General purpose)
An example applied to 1nterface bus) communication is shown below.

In Figure 2, 10 is a DMA controller (DMAC),
For example, the data word length, such as 10 bytes, is preset by the CPU 13, and controls data transfer between the RAM (buffer memory) 11 and the GPIB controller 12, which is a communication LSI, during DMA transfer.CPLI 1
3 controls the entire system according to the flowchart shown in FIG. 14 is retriggerable mono-multi (re-trigger one-shot multi-vibrator) DMA
The configuration is such that a detection output is output if no bird is received within a predetermined time constant period from the timing of the DMA response of each byte of C10. A flip-flop 15 outputs a timeout interrupt signal based on the detection output of the retriggerable monomulti 14.

Next, the operation of the present invention will be explained with reference to FIGS. 2 to 4.

In FIG. 2, the CPU 13 is a GPI communication LSI.
Initialize the B controller 12 and DMAC 10 (step 20 in FIG. 3), then reset the flip-flop 15 (step 21), and then set the data word length corresponding to the number of received data in DMACl0. Step 22).

Next, reset the flip-flop 15 to OFF (step 23) and turn on DMAClO (step 24).
, puts the system into the data receiving state. In this state, the GPrBPr upper roller 12 DMs one byte at a time.
When A request (Fig. 4 (A)) is output, DMACl0 becomes D
An MA response (FIG. 4(B)) is performed, and the data input from the external GPIB communication line 16 is received by the GPrBPr upper roller 12, and is transferred to the GPIB under the control of the DMAC 10.
1 byte each D between controller 12 and RAM 11
MA data transfer (FIG. 4(C)) is performed. At this time, data transfer is performed on the data bus 5 according to the address specified by the DMAC 10.

In this case, the DMA response of DMACl0 (Figure 4 (B))
is supplied to the trigger terminal of the retriggerable monomulti 14, and when a retrigger is supplied within a time constant period set longer than the DMA transfer cycle, the time constant period is updated again from that timing. In this way, D
As long as MA transfer (Figure 4 (C)) is performed,
The output of the retriggerable monomulti 14 remains at the L level (FIG. 4(D)), and the output of the flip-flop 15 also remains at the L level (FIG. 4(E)).

When the DMA transfer is performed normally in this way and all 10 bytes of DMA transfer are completed, DMACl0 issues an end interrupt to the CPU 13, and the CPU 13 determines the interrupt type using the interrupt program (step 25 in FIG. 3). In this case, since it is a normal termination interrupt, the termination flag is set (step 26), and the process returns.

Next, it is determined that there is an interrupt input in the main program (normal termination interrupt) (step 27), and the flip 7
The 0 knob 15 is reset and turned on (step 28), the termination type is determined (step 29), and in this case, it is a normal termination, so the received data is processed (step 3).
0).

Here, if the word length of the received data becomes shorter than the data word length set in DMACl0 due to a malfunction on the external GPIB communication line 16, the received data ends before reaching the 10 bytes set in DMACl0. Then, as shown in FIGS. 4(A) and (B), the DMA request and DMA
The response stops midway, and DMA transfer (FIG. 4(C)) also stops. DMA from DMAC10
When the response (Fig. 4 (B)) disappears, the retriggerable
The time constant period of Monomulti 14 is about to end (Figure 4 (D))
, At this end timing, retriggerable mono multi 1
4 becomes H level (Fig. 4 (D)), and as a result, the output of the flip 70 knob 15 becomes H level, and is supplied to the CPU 13 as a timeout interrupt signal, while being supplied to the DMAC 10 as a forced stop signal. be done.

DMAC 10 is forcibly stopped by a forced stop signal from flip-flop 15, while CPU 13 is interrupted by a time-out interrupt signal from flip-flop 15. The CPU 13 determines the type of interrupt (step 25 in FIG. 3), and since it is a timeout interrupt in this case, it initializes the DMAC 10 (step 31).
Set the timeout flag (step 32) and return. Next, determine the interrupt input in the main program (step 27), and then reset the flip 70 knob 15 to the L level (L level in Figure 4 (F)) in step 2.
8), thereby the output of the flip-flop 15 becomes L level (FIG. 4(E)).

Next, the type of termination is determined (step 29). In this case, since it is a timeout termination, re-communication processing is started (step 33), and the operations from step 22 are repeated again.

In this way, even if the received data ends before the data word length set in DMACl0 is reached, the DMAC10 is reliably stopped and the bus is released, and then CPLJ1
3 ensures that the received data is processed. Moreover, in this case, instead of monitoring the time using a CPU software timer using the CPU cycle as in conventional devices, hardware such as the retriggerable monomulti 14 and flip-flop 15 is used to monitor the time regardless of the CPU cycle. Since monitoring is performed, the time can be reliably monitored even in the case of high-speed transfer without CPU cycles or if the DMAC does not release the bus for some reason.In addition, it is possible to reliably monitor the time even in the case of high-speed transfer without CPU cycles, or in cases where the CPU cycle must be strictly monitored It can also be applied to systems where processing must be performed quickly.

Next, even though there is received data, DM for some reason
A case where an A request and a DMA response are not performed will be explained. If there is no DMA response from the DMAC 10, the output of the retriggerable monomulti 14 remains at the H level, and no time-out interrupt is generated by the flip 70 tube 15.

Therefore, the CPU 13 determines that there is no interrupt input (step 27 in FIG. 3), starts the software timer of the CPU 13 at this point, and determines that a predetermined period of time has elapsed (timeout). The DMAC 10 is forcibly stopped in the same way as when a timeout interrupt from the DMAC 15 occurs. Next, set the timeout flag (step 35), flip 7
The 0 knob is reset and turned on (step 28).

In this way, even if there is no DMA response from the DMAC 10, the DMACl0 is reliably stopped, so deadlock can be prevented.

<If DMAC does not complete its operation, time is monitored regardless of CPU cycles, so DMAC can be reliably stopped and deadlock can be prevented even in the case of high-speed transfer without CPU cycles or if DMAC does not release the bus. In addition, there is no need to strictly monitor CPU cycles, and recovery processing can be performed quickly.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the method of the present invention, Fig. 3 is an operation flowchart of the CPU, Fig. 4 is a timeout detection time chart in the present invention, Fig. 5 is a block diagram of an example of a conventional method. (Effects of the Invention) As explained above, according to the present invention, when the actual received data word length is shorter than the data word length set in the DMAC due to a malfunction on the communication line, for example, 10.42 is DMA controller (DMAC), 11 is RAM (buffer 7 memory), 12 is GPIB controller, 13 is CPU. 14 is a retriggerable monomulti, 15 is a flip-flop, 16 is a GPIB communication line, 40 is a transfer source circuit, 41 is a transfer destination circuit, 43 is a hardware timer circuit, and 44 is a control means. Patent applicant Fujitsu Ltd.

Claims (1)

[Claims] Data is transferred using DMA (Direct Memo) at a predetermined period.
ry Access) transfer source circuit (40)
DMA that controls the transfer from to the transfer destination circuit (41)
In a data communication system provided with a controller (42), when the controller (42) is activated every DMA transfer cycle, a time constant longer than the DMA transfer cycle is set, and the DMA transfer is not performed within the time constant period. Detect this and DM the above
A hardware timer circuit (43) forcibly stopping the A controller (42); and initializing the DMA controller (42) and the hardware timer circuit (43) by the detection by the hardware timer circuit (43). 1. A data communication method, comprising: control means (44) for controlling the re-communication process.