JPH0245847A - Virtual address cache control device - Google Patents

Abstract

PURPOSE:To realize the high speed consistent processing of main storage to be needed for multi-processor constitution by wholly providing the entry address of a table, which is used for virtual storage control, in a cache. CONSTITUTION:When a low order part is latched by a bus monitor real address (real address for a main storage access) register 102 to be retrieved, the low order part is used to select one row of memories 106 and 107 through a decoder 111. In the memory 106, an area table entry address, which is an address value at the time of first table retrieval to be shown in a figure, is held. In the memory 107, an area table entry address, which is an address at the time of the second table retrieval to be shown in the figure, is held. For the contents of the bus monitor real address register 102, the contents of the memories 106 and 107 and the high order part of the above mentioned bus monitor address register 102 are simultaneously compared by comparators 108 and 109 in order to check possibility to whole reloading. Even when only one part is coincident, such a condition is transmitted to an effective bit array 105 and the correspondent row is made ineffective.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a control method for an address translation buffer or cache memory indexed by virtual addresses, and in particular to a virtual address cache device for managing memory consistency in a multiprocessor. Regarding the invalidation method.

Conventional technology Consistency management of storage contents is an essential issue when adopting a multiprocessor configuration in an address translation buffer (TLB) for converting virtual addresses to real addresses or in cache memory that has a copy of main memory. .

For example, if the contents of the main memory or the contents of the virtual memory management table are updated by a processor,
For other processors, TLB
Alternatively, it is necessary to rewrite or invalidate the contents of the cache memory. This is called TLB/cache matching processing.

In conventional computer technology, matching processing in an address translation node (TLB) for converting a virtual address to a real address is executed in the following procedure.

■ When the contents of the virtual memory management table are updated by a certain processor (hereinafter referred to as the changed processor), the real address of the updated result is notified to other processors (hereinafter referred to as the changed Bromo Sosa). .

■ In the modified processor, from the real address notified by the modified Bromo Nosa, in the virtual/real address pair,
A so-called reverse address translation, in which a virtual address is subtracted from a real address, is performed, and the corresponding TLB entry is cleared from the obtained virtual address.

In order to implement this method, an inter-processor communication mechanism is required that notifies the processors of the real address as a result of the conversion when the address space is changed between the processors.

Furthermore, the matching process of the cache memory that holds main memory data is executed in the following steps.

(2) When a certain processor (hereinafter referred to as a changing processor) updates the contents of the main memory, the real address of the main memory to be updated is notified to another processor (hereinafter referred to as a changed processor).

■ The modified processor searches the cache memory using the real address notified from the modified processor and clears the corresponding cache entry.

In order to implement this method, an inter-processor communication mechanism that monitors the real address during a memory write access that changes main memory between processors, and a A memory configuration or timing generation mechanism that can be used for monitoring is required.

In this way, the conventional TLB and cache matching process is
There is little compatibility in execution methods, implementation is separate, and requires a large amount of hardware cost. The background to this is the fact that it was common to adopt a hardware configuration method in which the TLB and cache memory were separated and implemented as independent mechanisms (cache memory indexing method using real addresses). I can say that.

Problem to be Solved by the Invention In order to separate TLB/cache, it is necessary to
It is necessary to provide real address memory in both B and cache, increasing hardware cost. Furthermore, in order to support multiprocessors, if matching processing is performed on both the TLB and the cache, a node is required for matching processing on the real address memories of both, and furthermore, hardware is required.・There is a disadvantage that the cost increases.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a virtual address cache control device that can perform storage consistency processing necessary for a multiprocessor configuration at high speed with less hardware.

Means for Solving the Problems A cache memory control device according to the present invention that searches a cache memory using virtual addresses includes a virtual address memory means for holding a virtual address indicating a data block existing in a cache data memory, and a virtual memory management device. one or more translation table entry address memory means for holding real addresses indicative of an address translation table used for the address translation table, data memory means for holding data obtained as a result of indexing the address translation table, and words in each of the memory means. effective bit array means for holding valid bits corresponding to each address, means for inputting an external address, and address comparison means for comparing the contents of the translation table entry address memory means and the external address. However, when the input of the external address is notified, the address comparison means clears a corresponding portion of the valid bit array means.

Further, if possible, a real address memory means for holding a real address obtained as a result of searching the address translation table, and a second address for comparing the contents of the real address memory means with the external address. and comparing means, and when the input of the external address is notified, the address comparing means and the second address comparing means simultaneously clear corresponding portions of the valid bit array means.

Operation The virtual address cache control device according to the present invention uses an address (abbreviated as a table entry address, TEA) that points to an entry used to convert the virtual address in a table used for virtual memory management (for example, a Hesy table). ), the virtual address is subtracted from the real address (, without performing the so-called reverse address translation), and the corresponding T
LB entry can be cleared.

Furthermore, the method of using the table entry address table in this way is compatible with the conventional cache memory matching processing method. Therefore, when implementing a virtual address cache that directly searches cache data using a virtual address, it is possible to clear the TLB entry and invalidate the cache data at the same time.

Therefore, the hardware cost required to invalidate a cache entry can be significantly reduced compared to the conventional TLB/real address cache separate configuration formula.

Next, embodiments of the present invention will be described with reference to the accompanying drawings.

Example 1 FIG. 1 is a block diagram of one embodiment of the present invention.

The illustrated embodiment is an example in which the address translation mechanism is implemented, and therefore does not include a cache memory portion that holds general main memory data.

The virtual address cache control device shown in FIG. 1 includes a virtual address register 1 that holds a virtual address to be translated.
01, and its virtual address register 101
has its lower part connected to the address decoder 110, and its upper part connected to part of one input of the comparator 113. The output of decoder 110 is connected to virtual address memory 103, process identification number memory 104 and valid bit array 105 to select those rows. The contents read from the selected row of virtual address memory 103 and process identification number memory 104 are sent to the other input of comparator 113.

A process identification register 112 is further connected to one input of the comparator 113, and the comparator 113
It is controlled according to the contents read from the selected row of the valid bit array 105. The output signal 152 of the comparator 113 controls the delivery of the real address memory 114 to the output cache memory.

Furthermore, a bus monitor real address register 102 is provided to hold a bus monitor real address to be searched. The lower part of the register 102 is an address decoder 111.
The output of the decoder is connected to area table entry address memory 106, page table entry address memory 107 and valid bit array 105,
6 and the contents of the selected row of page table entry address memory 107 are connected to one input of comparators 108 and 109. The comparators 108 and 109
The other input of bus monitor real address register 102
are connected, and their comparators 108 and 109
The output of controls the effective bit array 105.

Note that when this embodiment uses an associative method such as a set associative method, one memory 103 to 107 may exist for each associative unit. It is obvious that the following argument holds true even with such an extension.

The address conversion sequence of this embodiment will be explained based on FIG. Once the virtual address to be translated is latched into virtual address register 101, its lower part is used to select one row of each memory 103, 104, 105 through decoder 110.

A field corresponding to the upper part of the virtual address register 101 is held in the memory 103, and when the content according to the output of the decoder 103 is read, it is compared with the upper part of the virtual address register 101 by the comparator 113. Ru.

Further, the memory 104 holds a process identification number that specifies the virtual address stored in the memory 103, and when the content according to the output of the decoder 110 is read out, it is compared with the content of the process identification register 112 and the comparator 113. be compared.

The memory 105 holds information indicating whether the read row is valid or not, and when the contents according to the output of the decoder 103 are read, the comparator 113 is notified.

The comparator 113 compares both the address and the process,
Moreover, when the row is valid, a hit signal 152 is output. In the real address memory 114, a line specified by a lower part of a virtual address register (not shown) has been read out, and the data is transferred to the cache memory for the first time in response to a hit signal 152.

If the hit signal 152 is not activated, a replacement process, ie, replacement of the memo 'J130-107, is performed. In particular, a new virtual address is registered in the virtual address 103, and the process identification number memory 10
4, a new process identification number is registered, and the area table entry address memory 106 is registered with the address of the area table entry obtained during conversion.
The address of the page table entry obtained during the conversion is registered in the page table entry address memory 107, and upon completion of the conversion, the replaced row portion of the effective bit array 105 is set.

Next, a processing sequence for matching processing will be explained. It is assumed that the virtual storage system used here is two-level paging as shown in FIG.

The bus monitor real address to be searched (real address for main memory access) is the bus monitor real address register 102.
When the memo! is latched, the lower part of the memo! Used to select one row of J 106.107. Memo! J 106 includes the first part of Fig. 2.
The area table entry address that is the address at the time of the second table search is held, and the memory 107 stores the second area table entry address.
The page table entry address, which is the address at the time of the second table search in the figure, is held. Regardless of whether an area table entry or a page table entry is rewritten, the contents of the cache must be invalidated. Therefore, the contents of the bus monitor real address register 102 are stored in memory by comparators 108 and 109 in order to check the possibility of all its rewriting.
06.107 contents and bus monitor real address register 1
The upper part of 02 is compared at the same time. If even one match is obtained, it is a valid hit array 10.
5, the replaced row portion of the valid bit array 105 is cleared, and the corresponding row is invalidated.

Example 2 FIG. 3 is a block diagram of a second embodiment of the invention.

The second embodiment differs from the first embodiment in that it is a virtual address cache that handles TLB and cache simultaneously in one hardware block. Note that elements that are the same as those shown in FIG. 1 are given the same reference numerals, and description thereof will be omitted. As can be seen from a comparison between FIG. 1 and FIG. 3, the embodiment shown in FIG.
a real address memory 123 whose row is selected by 1;
a comparator 122 that compares the contents of the selected row of the real address memory 123 with the contents of the upper part of the bus monitor real address register 102;
24.

The cache index sequence of this embodiment will be explained based on FIG. Once the virtual address to be exchanged is latched into the virtual address register 101, its lower part is transferred to each memo 'J103.104.1 through the decoder 110.
Used to select one row of 05.

Contents of memory 103, 104, 105 and register 101
The comparison by the comparator 113 is the same as in the first embodiment.

The comparator 113 determines that both the address and the process match,
In addition, when the row is valid, a Hi/Soto signal 152 is output. In the cache memory data 124, a line specified by a lower part of a virtual address register (not shown) is read out, and the data is delivered to the data request source for the first time in response to the hint signal 152.

If the hit signal 152 is not activated, a replacement process, ie, replacement of the memories IJ 103-107, is performed. In particular, a new virtual address is registered in the virtual memory 103, and a process identification number memo 1J1 is registered.
A new process identification number is registered in 04, and the address of the area table entry obtained during conversion is registered in area table entry address memo 1 river 06.
The address of the page table entry obtained during the conversion is registered in the page table entry address memory 107, and upon completion of the conversion, the replaced row portion of the effective bit array 105 is set.

Next, a processing sequence for matching processing will be explained. It is assumed that the virtual storage system used here is also two-level paging as shown in FIG.

The bus monitor real address to be searched (real address for main memory access) is the bus monitor real address register 102.
, its lower part is used to select one row of memory 106.107.123 through decoder 111. The contents held in memory 106 and memory 107 are the same as in the first embodiment. The memory 123 holds real addresses that are the final results of address translation.

Regardless of whether the area table entry, page table entry, or in-page main memory data is rewritten, the contents of the cache must be invalidated. Therefore, the contents of the bus monitor real address register 102 are processed by the comparator 10 in order to check the possibility of all rewriting thereof.
8.109.122, memory 106.107.
The contents of 123 are compared with the upper part of 102 at the same time. 1
If any match is found, it is transmitted to the valid bit array 105, the replaced row portion of the valid bit 105 is cleared, and the corresponding row is invalidated.

As described in detail, the present invention is capable of executing main memory consistency processing necessary for a multiprocessor configuration at high speed by having all the entry addresses of the table used for virtual memory management in the cache. effective. In particular, there is an advantage that the corresponding TLB entry can be cleared at high speed without executing so-called reverse address translation, in which a virtual address is subtracted from a real address, as is done in conventional computers.

Furthermore, when implementing a virtual address cache that directly searches cache data using a virtual address, TLB invalidation and cache data invalidation can be executed simultaneously, reducing the hardware cost required to invalidate cache entries. This has the effect of significantly reducing the amount of traffic compared to the TLB/real address cache separate configuration method.

[Brief explanation of the drawing]

1 is a block diagram of a first embodiment of a virtual address cache control device according to the present invention; FIG. 2 is a diagram illustrating the flow of address translation in the virtual memory management system assumed in FIG. 1; FIG. 3 is a block diagram showing a second embodiment of the virtual address cache control device according to the present invention. [Main reference numbers] 101...Virtual address register 102...Bus monitor real address register 103...Virtual address memory 104...Process identification number memory 105...Valid focus array 106...Area table entry address memory 10
7...Page table entry address memory 108.
109.113...Comparator 110.111...Address recorder 112...Process identification register 114...Real address memory

Claims (1)

[Claims] A cache memory control device that indexes a cache memory by a virtual address, the virtual address memory means holding a virtual address indicating a data block existing in the cache data memory, and an address conversion table used for virtual memory management. one or more translation table entry address memory means for holding real addresses; data memory means for holding data obtained as a result of searching said address translation table; and holding valid bits corresponding to each word of each of said memory means. means for inputting an external address; and address comparing means for comparing the contents of the translation table entry address memory means with the external address; A virtual address cache control device characterized in that, when notified, said address comparison means clears a corresponding portion of said valid bit array means.