JPH0244838A - Dc compensation circuit - Google Patents

Abstract

PURPOSE:To compensate a long distorted waveform due to the cut-off of a low frequency by means of the less number of taps and to simplify a hardware scale by using a fixed IIR filter which is cascade-connected and a variable coefficient multiplier. CONSTITUTION:An identification circuit 21 reproduced an original data based on the output signal of a DC compensation circuit, which is obtained from an adding circuit 41. Data are supplied to a first means consisting of the serial circuit of plural fixed IIR filters 471-47n. Respective outputs of plural fixed IIR filters 471-47n are supplied to corresponding variable coefficient multiplication circuits 491-49n whose outputs are supplied to the adding circuit 41 to be added with input signals. The addition outputs turn into the outputs of the DC compensation circuit. Here, a second means variably controls respective coefficients of plural variable coefficient arithmetic circuit 491-49n based on an operated result obtained by the input and output of the identification circuit 21. Thus, hardware constitution can be miniaturized.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a DC compensation circuit, for example, a DC compensation circuit that reduces waveform distortion due to low frequency cutoff in a digital subscriber line transmission system. be.

[Conventional technology]

2. Description of the Related Art Conventionally, there has been a quantization feedback type DC compensation circuit having a configuration example as shown in FIG. 5 as a device for reducing waveform distortion due to low frequency cutoff in, for example, a digital subscriber line transmission system.

In the figure, for example, an input signal 13 supplied to an input terminal 11 from a transmission path (not shown) in a digital subscriber line transmission system is added with a compensation signal 17 in an adder circuit 15 to become an output signal 19. Output signal 19 is supplied to identification circuit 21 . Here, the original data to be transmitted from the transmission side (not shown) is identified and reproduced, and an identification result signal 23 is obtained. Thereafter, the identification result signal 23 is delayed by one time slot (T) in the delay circuit 25, and then is processed by an adaptive FIR (Finite Impulse Relay).
5ponse) is input to the filter 27. Adaptive FI
The R filter 27 outputs a compensation signal 1 that compensates for low-frequency cutoff distortion.
7 and supplies it to the adder circuit 15.

An example of the configuration of this adaptive FIR filter 27 is shown in FIG. In the figure, the output from the delay circuit 25 is output from n delay circuits 31 (delay circuits 311, 312, . . . , 3
1,) is supplied to the first delay circuit 311 in the series connection. Here, the delay circuit 31. ．． 3
1□,...,31. , are temporally delayed by one time slot (T,) and supply their outputs to the delay circuit 31 at the next stage. In addition, (n+1) variable coefficient multipliers 33 (variable coefficient multipliers 33..33□, . . .
..., 33°337°1), and their inputs are n delay circuits 31 (delay circuits 31...31□
, . . . 31, .), and the output is supplied to the adder circuit 35. This addition circuit 35
The output of is supplied to the adder circuit 15 as a compensation signal 17.

[Problem to be solved by the invention]

By the way, let's take a look at an example of compensation for an impulse response of a transmission line with respect to an isolated response waveform in the conventional DC compensation circuit described above.

FIG. 7 shows an example of an impulse response of a transmission line to an isolated waveform input. As shown in the figure, the isolated response waveform of the input signal 13 obtained from the transmission line is distorted over 100 time slots or more due to low frequency cutoff.

However, the above-described adaptive FIR filter 27 can only compensate for one time slot per tap. Therefore, as shown in Fig. 7, in order to compensate for a distorted waveform that spans over 100 time slots, the number of taps equivalent to the number of time slots affected by the distortion is required by the adaptive FI.
It is necessary for the R filter 27. Therefore, there is a problem in that the DC compensation circuit requires a large-scale hardware configuration.

The present invention was created in view of these points, and an object of the present invention is to provide a DC compensation circuit that can be realized on a small hardware scale.

[Means to solve the problem]

In order to achieve such an objective, the present invention includes:
It is equipped with an adder circuit that adds the input signal from the input terminal and the output signals of a plurality of variable coefficient multiplier circuits and obtains the added output to the output terminal, and identifies and reproduces the original data from the output signal of the adder circuit. A plurality of fixed I
I R (Infinite Impulse Re5po
nse) filters in series. The output of each of these fixed IIR filters is supplied to a corresponding variable coefficient multiplication circuit. Here, a desired calculation is performed between the input and output of the identification circuit, and each coefficient of the plurality of variable coefficient multiplication circuits is variably controlled based on the result.

[For production]

In the present invention, the original data is reproduced by the identification circuit based on the output signal of the DC compensation circuit obtained from the adder circuit, and is supplied to the first means comprising a series circuit of a plurality of fixed IIR filters.

The outputs of each of the plurality of fixed IIR filters are supplied to respective variable coefficient multiplier circuits, and their outputs are supplied to an adder circuit and summed with the input signal. This addition output becomes the output of the DC compensation circuit.

Here, each coefficient of the plurality of variable coefficient multiplication circuits is variably controlled by the second means based on the calculation results obtained by inputting and outputting the identification circuit.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

(2) Configuration of Embodiment FIG. 1 shows the configuration of a DC compensation circuit in an embodiment of the present invention. Here, the same symbols as in FIG. 5 indicate the same circuits, etc., and their details will be omitted.

In FIG. 1, an input signal 13 supplied to an input terminal 11 from a transmission line (not shown) in, for example, a digital subscriber line transmission system is sent to an adder circuit 41, which is connected to n variable coefficient multipliers 49 (variable coefficient multipliers). Container 49, .49□,...
・,49. ), and an output signal 43, which is the addition result, is obtained from the output terminal 29.

The output signal 43 is also supplied to the identification circuit 21, where the original data is identified and reproduced to obtain an identification result signal 45. This identification result signal 45 is generated by n fixed J I R (
Infinite Impulse Re5ponse
) filter 47 (fixed ITR filter 47., 47□.

......,47. ) is supplied to the series connected circuit.

n fixed IIR filters 47. ~47. ．． Each common connection point (tap) of the corresponding variable coefficient multiplier 4
9 (variable coefficient multiplier 49..49□..., 49.
,)It is connected to the.

Further, a subtraction circuit 51 is provided for subtracting both signals between the input terminal and the output terminal of the identification circuit 21,
The output signal is transmitted to a plurality of correlators 53 (correlators 53 . . . 5
3□, ..., 53□). Furthermore, these plurality of correlators 53 (correlators 53..53
□1...,53. ) are connected to respective common connection points (taps) of the corresponding fixed FIR filters 47 .

FIG. 2 shows an example of the configuration of the fixed IIR filter 47. Here, the fixed IIR filter 47 represents one of the plurality of filters shown in FIG. In one fixed IIR filter 47, the identification result signal 45 from the identification circuit 21 or the output signal from the previous stage fixed IIR filter 47 is input to the adding circuit 61, and the output is delayed by one time slot. The delayed output signal is commonly supplied to a fixed coefficient multiplier 65 for coefficient a and a fixed coefficient multiplier 67 for coefficient s.

The output signal of this fixed coefficient multiplier 67 is supplied to an adding circuit 61. Further, the output signal of the fixed coefficient multiplier 65 is input to the corresponding variable coefficient multiplier 49 and correlator 53.

(2) Operation of the embodiment Next, the operation of the embodiment of the present invention having the above-described configuration will be explained.

For a fixed IIR filter 47 as shown in FIG. 2, the response q to an isolated waveform in the i-th time slot is
(i) is q (i) −a e′b”
−(1). Here, a is a fixed coefficient of the fixed coefficient multiplier 65, b is a fixed coefficient of the fixed coefficient multiplier 67,
T is a time slot. It can be seen that the isolated response waveform in equation (1) above lasts for an infinite time.

Incidentally, FIG. 3 shows an example of the isolated waveform response p6 of each tap when the fixed IIR filter 47 is a first-order TIR filter. Here, the fixed IIR filter 471 is plotted on the vertical axis.
~47. ．． The amplitude of the output signal pA is plotted on the horizontal axis, and time is plotted as an integer multiple of the time slot T.

By combining such isolated waveform responses pk, a distorted waveform as shown in FIG. 7 can be compensated for.

In order to compensate for the distorted waveform, variable control (update) of the coefficient ah (k=1.2..., n) of the variable coefficient multiplier 49 is performed as follows.

ak ←a, C-R(p* (+), e (+))
=12) Here, C is a constant, R is the correlation function of the correlator 53, and pk(i) is the output of the fixed IIR filter 47 in the i-th time slot. Also, e(
i) is the identification error (obtained by the subtraction circuit 51) in the i-th time slot given by the following equation (3).

e (i) -r (i) -d (+)
-(3) Here, r(i) and d(i) are the output in the i-th time slot (output signal 43
), which is the identification result (identification result signal 45).

In this way, the coefficient ak (k=1.2.-.., n) of the variable coefficient multiplier 49 can be variably controlled (updated) based on the above equation (3).

By the way, the output ph(i) of the fixed IIR filter 47 in the i-th time slot and the discrimination error e(i) in the i-th time slot are obtained by the configuration of this embodiment, and based on these, the variable coefficient multiplier 4
It is possible to update the coefficient a□ of 9. Therefore, no special control circuit is required to update the variable coefficient a. Only the correlator 53 is sufficient as a control circuit for updating this coefficient a.

Furthermore, when correlating only the code (sgn), the circuit configuration of the correlator 53 is extremely simple because it can be configured with only an exclusive OR gate.

Next, the effects of the embodiment of the present invention will be shown by simulation. As the fixed IIR filter 47, the same primary II
Four R filters were used. Therefore, k=1-4.

Further, the coefficient of the fixed IIR filter was set to b=2-', the coefficient update was set to C=2-11 in the above equation (2), and the sign-only correlation given by the following equation (4) was used.

R(Pk(i), e(i))−sgn ph (
i)・sgn e(i)...(4) Here, k=1.2, 3.4. Further, the code is a four-level code and the transmission speed is 80 kilobaud.

FIG. 4 shows the coefficients (a, , az+83
+84) and the output signal 43 (vertical axis) over time (horizontal axis). Here, variable coefficient multiplier 49. ~49
It can be seen that the coefficients a1 to a4 of No. 4 all start from an initial value of zero, but converge to a constant value as time passes.

The waveform of the output signal 43 is initially distorted due to the low frequency cutoff, but the distortion becomes smaller as the coefficient am converges. After the coefficients converged, the low cutoff distortion was reduced to 0.2% (RMS). It can be seen that such a configuration allows for excellent compensation.

(2) Summary of the Embodiment As described above, in the embodiment of the present invention, in order to solve the problems of the conventional technology, the fixed IIR filter 47 and the variable coefficient multiplier are connected in cascade to the quantization feedback circuit. The main feature of this method is that it uses 49, and is different from the conventional technology.

By using the fixed IIR filter 47 in this way, a long distorted waveform due to low frequency cutoff can be compensated for with a small number of taps. Furthermore, if this fixed IIR filter 47 is made first-order, a waveform suitable for compensating for low-frequency cutoff distortion can be obtained. Therefore, the hardware scale can be simplified. Further, variable coefficient multipliers 49+ to 49. , coefficients a1 to a,
The circuit that performs variable control of the coefficients for , is the correlator 53
Since it can be formed by , the hardware scale is small.

(1) Modifications of the Invention It should be noted that the present invention is not limited to the above-described embodiments, and those skilled in the art can easily imagine that there are various modifications.

〔Effect of the invention〕

As described above, according to the present invention, a long distortion waveform due to low frequency cutoff can be compensated for with a small number of taps, and the hardware scale can be simplified.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a DC compensation circuit according to an embodiment of the present invention, FIG. 2 is a block diagram of a fixed IrR filter, and FIG. 3 is a diagram showing an example of a response waveform Ph of a fixed IIR filter to an isolated waveform input. Fig. 4 is a diagram showing an example of the time change between the coefficients of a variable coefficient multiplier and the output signal, Fig. 5 is a block diagram of a conventional quantization feedback type DC compensation circuit, and Fig. 6 is a diagram of an adaptive FIR filter. Diagram showing a configuration example, No. 7
The figure is an explanatory diagram of an example of an impulse response of a transmission line to an isolated waveform input. In the figure, 11 is an input terminal, 13 is an input signal, 15, 35, 41.61 is an addition circuit, 17 is a compensation signal, 19.43 is an output signal, 21 is an identification circuit, 23.45 is an identification result signal, 25 .31.63 is a delay circuit, 27 is an adaptive FIR filter, 29 is an output terminal, 33.49 is a variable coefficient multiplier, 47 is a fixed IIR filter, 51 is a subtraction circuit, 53 is a correlator, 65.67 is a fixed It is a coefficient multiplier. o 0 Shizu H --- Written amendment to ambiguity procedure (release) Case description Patent application No. 194922 of 1988 Name of the invention Person who makes direct current compensation circuit correction Relationship to the case Applicant's address Chiyoda-ku, Tokyo Uchisaiwaicho 1-1-6 Name (422) Nippon Telegraph and Telephone Corporation Agent Address: 151
! (03) 375-1631 Address: 2-11-2 Yoyogi, Shibuya-ku, Tokyo November 29, 1988 (Shipping port) 6. Subject to amendment

Claims (1)

[Claims] (1) a plurality of variable coefficient multiplier circuits; an adder circuit that adds an input signal obtained from a transmission line and an output signal of the plurality of variable coefficient multiplier circuits, and obtains the summed output at an output terminal; An identification circuit that identifies and reproduces the original data to be transmitted from an output signal and a plurality of fixed IIR filters having a desired time delay are connected in series, the output of the identification circuit is input, and the plurality of fixed IIR filters are connected in series. first means for supplying respective outputs of the filters to corresponding circuits of the plurality of variable coefficient multiplication circuits; and performing a desired operation between the output of the adder circuit and the input of the first means; A direct current compensation circuit comprising: second means for variably controlling each coefficient of the plurality of variable coefficient multiplication circuits based on the above.