JPH0236630A - Bit phase synchronizing circuit - Google Patents

Abstract

PURPOSE:To select a reproduced clock optimum to an input signal in a shorter time by regenerating a reproducing signal synchronously with the same clock in a high speed signal inputted in a different phase by means of a system common clock. CONSTITUTION:An output section 40 has flip-flops 41-43 whose reset terminals connect to outputs S1-S3 of flip-flops 31-33 of an optimum clock discrimination section 30, an input signal DI is given in common to each input terminal and clocks CK1-CK3 are given respectively to clock terminals. Then an input signal D2 reproduced by the flip-flop 42 is regenerated at a flip-flop 44 by using the clock CK1 into a reproducing signal D2'. Thus, the reproduced signal is regenerated by using the common system clock to obtain an output signal synchronously with the system clock. Thus, a high speed input signal including jitter is regenerated by using the optimum clock in a short time.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a phase synchronization circuit used in a communication path device of an exchange, and in particular, the present invention relates to a phase synchronization circuit used in a communication path device of an exchange, and in particular, a phase synchronization circuit that synchronizes high-speed signals input with different phases to the same clock. The present invention relates to a phase synchronized circuit suitable for signal reproduction.

[Conventional technology]

The communication path device of the exchange is equipped with a phase synchronization circuit that adjusts the phase of each input signal in order to reproduce signals input with different phases using the same clock.

As shown in FIG. 5, the conventional phase synchronization circuit includes flip-flops (FF) 1, 2.3, and delay circuits 4, 5.
Three phase clocks CKI, C shifted by one hour at
K2. Create CK3 and input the input signal to each clock CKI,
CK2. Punch out at CK3 and use the values as SL, S2. S3
(Figure 6). When the value S1 acquired at the clock CKI becomes equal to the value S3 acquired at the clock CK3, it is determined that the input signal and the clock are in phase with each other, and the value S2 acquired at the clock CK2 is used as the reproduced output. If S1≠83, the switch 6 is switched by a control signal to sequentially apply a delay of a fixed value to the input signal, and this is repeated until 51=S3.

In addition, as related to the conventional phase locked circuit, 198
6 “International Zurich Seminar on Digital Communication Papers” C4, 1-C
4,4 (1986 INTERNATIONAL ZU
RICHSEMINARON DIGITAL C
OMMUNICATIONS MARCHll-13
, 1986 ZURICH/5 WITZERLAND).

[Problem to be solved by the invention]

The above conventional technology has a configuration in which the delay value is changed one by one until 5L=83, so the configuration of the phase difference detection circuit and the optimum delay value setting circuit is complicated, and the process from detecting the phase difference to stabilizing it is complicated. The problem is that it takes time. Also, since S1 and 83 are compared every time, S1≠8 due to the influence of noise etc.
When the condition 3 occurs, the delay value of the input signal is reset each time so that 51=S3, and there is also a problem that there is little margin for noise in the input signal.

SUMMARY OF THE INVENTION An object of the present invention is to provide a bit phase synchronization circuit which can select the optimum recovered clock for an input signal in a shorter time and has a large margin against fluctuations in the input signal.

[Means to solve the problem]

The above purpose is to provide an n-phase clock generation circuit that generates n clocks with the same clock period but shifted by 1/n phase, a startup circuit that creates a startup signal synchronized with the rising edge of the input data signal, and an is connected to n flip-flops to which the start signal is commonly connected and each of the n-phase clocks is connected to a clock terminal, and by taking in the start signal at the time of change of the n-phase clock, it is possible to determine which clock phase changes. An optimum clock determination circuit determines whether the activation signal changes at a certain point in time and holds the change point, and an input data signal is commonly connected to each input terminal, and a clock having the opposite phase of the n-phase clock is connected to the clock terminal. n flip-flops for reproducing input signals, each of which has a reset terminal connected to the output of the optimum clock determination circuit; and input data signals regenerated by the n flip-flops to a system. This is achieved by providing an output that is re-clocked.

[Effect]

When input data signals are sequentially fetched at the n-phase clock transition points, the fetched value at the falling edge of the n-phase clock CKQ is the first rl(J In this case, the clock CKn
The input value at the clock change point, which is slightly delayed from the falling edge of , is reliably stable at rHJ, and by punching out the input data signal at this clock change point, a stable output can be obtained.

The present invention embodies this idea, and its effect will be explained below.

In the optimal clock determination circuit, a flip-flop FF is created by punching out the startup signal synchronized with the rising edge of the input signal created by the startup circuit at the falling edge CKQ of the n-phase clock.
-Q output is flip-flop FF・1 to FF-n
When the output becomes rHJ for the first time, the output of the previous flip-flop FF-Q-1 is held at "L". The reset terminals of n flip-flops RFP"RFFn for reproducing input signals have FF-1 to F
Since the output of F-n is connected, all flip-flops except RFFQ-1 are reset and RFFn-1
only works. An input signal is input to the input terminal of this RFFfl-1, and a clock CKQ of Q-1 phase is input to the clock terminal.
-1 is input.

The rise of clock CKQ-1 is from clock CKQ.
Since this is a clock with a slightly delayed change point, a stable output signal can be obtained by punching out this clock. RF
The input signal reproduced by FQ-1 is given an appropriate delay and then re-initiated using the system clock. This provides an output signal synchronized with the system clock.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1st
The figure is a circuit configuration diagram of a bit phase synchronization circuit according to an embodiment of the present invention. The bit phase synchronized circuit consists of a 3-phase clock generator 10, a start signal generator 20, an optimum clock determiner 30, an output unit 40, and a re-determination signal generator 50. The 63-phase clock generator 10 is a delay circuit. 11.12, from the system clock CK, a clock CKI having the same phase as the clock GK, and a clock CK2 . Create CK3.

The activation signal generation unit 20 is a flip-flop (SFF) 2
1, and generates an activation signal DI' in synchronization with the input signal DI.

The optimum clock determination unit 30 includes three flip-flops 3.
], , 32, 33 and NOR gates 34, 35, 36, the activation signal DI' is commonly connected to the input terminals of the flip-flops 1, 2.3, and the clock terminals thereof each have an opposite phase CKI of the clock.

CK2. CK3 is connected, and the logical sum (output of the OR gate 61) of the external reset signal R8T and the re-determination signal R8L from the re-determination signal generation section 5o is connected to the reset terminal. Flip flop FFI.

FF2. In FF3, the activation signal DI' is
KI, CK2. The value punched out by CK3 is Sl, S2
．． Let's call it S3. SL, S2, 53 (7) outputs are 1 each.
It is connected to one of the input terminals of the NOR gates 36 and 34°35 placed before the previous flip-flop 33°31 and 32, and the flip-flop 3
Controls the clock inputs of 3, 31 and 32. In other words, S
When either L, S2゜S3 becomes rHJ, one of the input terminals of the corresponding NOR gate 36, 34.35 becomes rHJ.
The clocks ck3., which are output from each NOR gate 36, 34, and 35. Fix ckl and ck2 to rlJ.

As a result, the corresponding flip-flops 33, 31,
32 output S3. ]1. Either S2 is held at "L".

The output section 40 outputs the outputs S1'', S2.S of the three flip-flops 31, 32, and 33 of the optimum clock determination section 30.
The flip-flops 41, 42, and 43 each have a reset terminal connected to the input signal DI, and the input signal DI is commonly connected to each input terminal, and the clock CKI is connected to the clock terminal.

CK2. CK3 are connected to each other. Note that this flip-flop begins to be reset when the input to the reset terminal is "I("), but is fixed at "L".The input signal D2 reproduced by the flip-flop 42 is input to the flip-flop At step 44, it is punched out again by CKI to become the reproduced signal D2'.The reproduced signals Di, D2'
, D3 are logically summed by a three-man OR gate 45, and finally, an output flip-flop 46 converts the system clock SCK (clock CKI into an inverter 4).
7) and becomes an output signal Do synchronized with ScK.

If a problem such as burst noise is generated in the input signal occurs in the optimum clock determination unit 30 and the outputs SL, S2 and S3 become rH, the re-determination signal generation unit 50 outputs All flip-flops in the output section 40 are reset, making it impossible to reproduce the input signal. Therefore, when the AND gate 51 detects that the condition 5L=82=33=1 has been reached, the input of the reset pulse generation circuit 52 becomes rHJ, and a pulse with a constant pulse width is output as the re-determination signal R3L. , the flip-flops 21, 31, 32, and 33 are reset via the OR gate 61, and the determination is made again.

Next, this operation will be explained using FIGS. 2 and 3. Second
The figure is a diagram illustrating how an input signal that comes in with a certain phase is reproduced with an optimal clock.

In the activation signal generation unit 20, when the set signal ST is "H", the activation signal DI' becomes "H" in synchronization with the rising edge of the input signal DI. This signal DI' is applied to the clocks CKI, CK2 . It is taken in at the rising edge of τY1. As shown in FIG. 2, the outputs S3 of the flip-flop 33 are SL, S2 . At the beginning of S3,
As a result, the input clock CK2 of the flip-flop 32 is fixed at "L", and the output S2 of the flip-flop 32 is therefore determined to be "LJ".Next, the output S1 of the flip-flop 31 also becomes "H". Therefore, the clock CK3 is fixed to "L" and S3 is fixed to rHJ.

In this way, the output S2 of the flip-flop 32 is r],
J, and 53=SL=rHJ.

Flip-flops 4.1.42 with SL and S3 connected to the reset terminals are both reset, and the outputs Di and D
3 becomes "L", and the input signal is reproduced by the clock CK2 in the flip-flop 42 and becomes D2.

Next, in the output section 40, the flip-flops 41.degree.42.
43, the input signals D1°D2. The procedure for synchronizing D3 with the system clock SCK will be explained using FIG.

The input signals DI that are input with respective phases have different optimal reproduction clocks depending on the phase, and the input signals Di and D reproduced by the flip-flops 41, 42, and 43
2. As shown in FIG. 3, the phases of D3 are shifted by 1/3 period. The purpose of this bit synchronization circuit is to reproduce input signals that come in different phases with the same phase, so that the input signals Di, D2 . It is necessary to synchronize D3 with the system clock SCK. Now, if the system clock is defined as CKI, input signal D2 is clock C
When playing with KI, setup time may be insufficient. Therefore, - degrees, input signal D2 is clocked G
It is decided to punch out D2' with K.1, and then punch out with the system clock.

By doing the above, the input signal input at each phase is first regenerated by either clock CKI, GK2゜CK3, and if it is regenerated by clock CK2, it is further regenerated by clock CK1. Then, it is reproduced by the system clock CKI and becomes an output signal.

Figure 4 shows that it is detected that the input signal becomes [I('') for the first time at the rising edge of clock CK2, and
This figure shows a case where CK1, which is the opposite phase of I, is used as the optimal clock. The concept of using clock CKI as the optimal clock will be explained below.

Flip-flops generally require a set-up time (the amount of time the input data must be established before the clock rises). When a bit phase synchronization circuit with input data of 150 Mb/s is constructed using flip-flops with a set-up time variation of 0 to 2 ns, the input pulse width (=clock period T) is approximately 6
．． It is 7ns.

Therefore, if the setup time is 2 ns maximum.

In order not to detect rHJ at the rising edge of CKI.

The difference between the rising edge of the input data and the rising edge of CKl must be 2 ns or less (DI■ in Figure 4) If the set-up time is minimum Ons, it is sufficient that the rising edge of the input data occurs immediately before the rising edge of CK2. (DI ■ in Figure 4).

Therefore, the variation in input data falls within the range of DI■ to DI■. Therefore, the optimal recovered clock is a CKI that passes through the middle of the common portion of the input signals in this range.

〔Effect of the invention〕

According to the present invention, it is possible to obtain, with a simple configuration, a bit phase synchronization circuit capable of regenerating high-speed input signals including jitter, which are input with different phases, in a short time using an optimal clock.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a bit phase synchronization circuit according to an embodiment of the present invention, Fig. 2 is a diagram explaining the operation up to reproducing the input signal with the optimum clock, and Fig. 3 is a diagram explaining the operation at the output section. Figure 4 is a diagram explaining the phase relationship between the input signal range and GKI with CKI as the optimum clock, Figure 5,
FIG. 6 is a diagram illustrating the prior art.10...3-phase clock generation section. 11.12...Delay circuit, 20...Start signal generation unit, 21.31, 32, 33, 41, 42, 43° 44.4
6... Flip-flop, 30... Optimum clock determination section, 34.35.36... NOR gate, 4o... Output section, 45.61... OR gate, 47... Inverter. 50... Re-judgment signal generation unit, 51... AND gate, 52... Reset pulse generation circuit.

Claims (1)

[Claims] 1. In a bit phase synchronization circuit that synchronizes the phase of a data signal that is input at an arbitrary phase with a clock, an n-phase clock generation circuit that generates n clocks with the same clock period but shifted by 1/n phase, and an input a startup circuit that creates a startup signal synchronized with a change point of a data signal, and n flip-flops whose input terminals are commonly connected to the startup signal and whose clock terminals are each connected to the n-phase clocks; An optimum clock determination circuit that determines at which clock phase change the start signal changes by taking in the start signal at the time of change of the n-phase clock, and holds that change point, and an optimum clock determination circuit that is common to each input terminal. are n flips for input signal regeneration, each of which has an input data signal connected to it, a clock terminal connected to a clock signal opposite to the n-phase clock, and a reset terminal each connected to the output of the optimum clock determination circuit. - A bit phase synchronization circuit comprising a flop and an output section that re-inputs the input data signal reproduced by the n flip-flops using a common clock of the system.