JPH0234039A - Circuit for controlling quantity of information - Google Patents

Abstract

PURPOSE:To preclude the possibility of the case of a threshold level reaching a permissible limit and to improve the picture quality of a decoded picture by controlling the threshold level of the bit allocation after the compression ratio of level compression is controlled to reduce the quantity of produced information to some degree. CONSTITUTION:An analog video signal fed to an input terminal 1 is given to an A/D converter 2 and a block processing circuit 3, from which a digital video signal converted in the order of blocks is given to a delay circuit 6. The circuit 6 retards a data by a time required to detect a maximum value MAX and a minimum value MIN and a time deciding a compression coefficient alphaand gives its output to a compression circuit 14. Thus, an input level is multiplied by a multiple of alpha, the values MAX and MIN are compressed and the quantity of produced information is controlled less. After the compression coefficient alpha is decided, a threshold level for bit assignment is controlled and decided via a threshold level decision circuit 9 to reduce the opportunity of the threshold level reaching a permissible limit and to improve the picture quality of the decoded picture.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to, for example, when recording a variable-length encoded digital video signal onto a magnetic tape, the transmission rate of recorded data is made to correspond to the transmission path. The present invention relates to an information amount control circuit applied to control the amount of information to a predetermined value.

(Summary of the invention) This invention sets multiple thresholds for data,
It has a processing circuit that processes signals related to data according to the threshold range to which each value of data belongs, and the frequency of occurrence of each value of data within a predetermined period is totaled, and the total frequency is calculated. The amount of data within a predetermined period is calculated based on a plurality of predetermined threshold values determined for each value of data, and the calculated data is compared with a target value.

The compression coefficient α (α≦1) for the signal related to the data is determined according to this comparison output, and the threshold value from the threshold setting means for setting a plurality of threshold values for each value of the data is set to (1). /α), the amount of data is calculated based on the multiple thresholds multiplied by (1/α) and the above aggregation results, this calculation output is compared with the target value, and the amount of data is calculated according to this comparison output. A threshold setting means is controlled to determine a set threshold, and a signal related to compressed data is processed based on the determined set threshold, and the amount of data to be transmitted is When the number of images is large, the amount of data can be compressed without deteriorating the image quality.

[Conventional technology]

The applicant of this application has determined a dynamic range defined by the maximum and minimum values of a plurality of pixels included in a two-dimensional block, as described in Japanese Patent Application No. 59-266407, and A high-efficiency encoding device that performs adaptive encoding is proposed. Furthermore, as described in Japanese Patent Application No. 60-232789, a high-efficiency encoding device performs encoding adapted to a dynamic range with respect to a three-dimensional block formed from pixels in areas included in each of a plurality of frames. is proposed. Furthermore, as described in Japanese Patent Application No. 60-268817, there is a variable length encoding method in which the number of bits changes depending on the dynamic range so that the maximum distortion caused when quantization is constant. Proposed.

High-efficiency code (AD) adapted to the above-mentioned dynamic range
RC) is suitable for application to digital VTRs because it can significantly compress the amount of data to be transmitted. In particular, variable length ADRC can increase the compression ratio. However, with variable length ADRC, the amount of data to be transmitted varies depending on the content of the image, so when using a fixed rate transmission path such as a digital VTR that records a predetermined amount of data as one track, the amount of recorded information cannot be controlled. buffering processing is required.

Conventionally, the output data of a variable-length encoding circuit is supplied to an information restriction circuit, the output data of the information restriction circuit is supplied to a buffer memory, and the amount of transmitted data is monitored in the buffer memory. A control signal for controlling the transmission data so as not to exceed the transmission rate is fed back from the buffer memory to the information amount limiting circuit, thereby controlling the amount of generated information.

In conventional buffering, if the sensitivity to the amount of feedback is increased too much, it will oscillate around the target value, and if the sensitivity is decreased too much, convergence will take a long time. When convergence takes time, it is necessary to increase the buffer memory capacity.

As described above, the conventional buffering process has the drawback that it requires a considerable amount of know-how in practical use.

In order to solve this problem, the applicant of the present application filed the patent application No. 61
As described in Japanese Patent No. 257,586, a feedforward type buffering device using a cumulative type frequency distribution table is proposed.

This buffering device changes the frequency distribution of the dynamic range within a block to an integrated type, and sets multiple thresholds for the dynamic range within the block in order to specify the number of bits to be allocated to the frequency distribution. The threshold value is varied so that the amount of information generated as a result of the application is less than or equal to the target value.

According to this buffering device, the convergence time of buffering can be shortened by quickly and easily calculating the amount of generated information.

When changing the threshold so that the amount of generated information is below the target value, it is difficult to do so based on experience, and if the threshold is set too large, there is a problem in which deterioration of the restored image such as block distortion becomes visible. . In other words, there is a threshold limit at which deterioration is recognized for each allocated bit number, and for example, O
When the bit allocation threshold reaches or exceeds the level where
If the threshold value is set too large to suppress the amount of 0-occurrence information that makes block distortion visible, deterioration such as block distortion will become noticeable.

To solve this problem, we focused on the fact that the threshold value for each bit allocation has a limit beyond which it cannot be increased, and by using the threshold value up to the allowable limit, we can reduce the amount of generated information below the target value. A device for controlling the amount of information has been proposed by the applicant (Japanese Patent Application No. 63-31608).
In other words, after the threshold value reaches the permissible limit value, the level of the transmitted data is compressed to reduce the amount of information while the threshold value is fixed at the permissible limit value. .

[Problem to be solved by the invention]

In the above method, the bit allocation threshold is first changed to the allowable limit and then the compression coefficient is controlled, so when there is a scene change, large movement, etc. in the screen, the threshold is fixed at the allowable limit. There was a problem that the image quality of the restored image was not sufficiently good.

Therefore, an object of the present invention is to reduce the amount of generated information to a certain extent by controlling the compression ratio of level compression, and then to control the threshold value of bit allocation, so that when the threshold value reaches the permissible limit value, An object of the present invention is to provide an information amount control circuit that can reduce the amount of information and improve the quality of restored images.

[Means to solve the problem]

In this invention, there is provided a frequency aggregation circuit that aggregates the frequency of occurrence of each type of data within a predetermined cycle, and a first calculation that calculates the amount of data based on a plurality of thresholds for each type of data and the output of the frequency aggregation circuit. a compression circuit that multiplies a signal related to data by a coefficient α (α≦1); and a compression circuit that compares the output of the first arithmetic circuit with a target value, and determines a coefficient αΦ value according to the comparison output. a coefficient determining circuit; a threshold setting circuit that sets a plurality of thresholds for each type of data; a second arithmetic circuit that multiplies the threshold from the threshold setting circuit by (1/α); A third arithmetic circuit calculates the amount of data based on the threshold value from the second arithmetic circuit and the output of the frequency aggregation circuit, and compares the output of the third arithmetic circuit with the target value, and A control circuit that controls the threshold setting circuit to determine a set threshold; and a processing circuit that processes a signal related to data from the compression circuit based on the set threshold from the threshold setting circuit. It is equipped.

[Effect]

For example, the sum of frequencies is calculated for each range divided by multiple thresholds of the dynamic range, and this sum of frequencies is multiplied by a weight (number of bits).
The generated information amount for each range is calculated, and the generated information amounts for the plurality of ranges are added to calculate the total generated information amount. Therefore, a series of calculations is required each time the threshold value is changed. However, if an integration table of the frequency of occurrence is created, even if the threshold value is changed, the frequency corresponding to the threshold value can be immediately known, and by multiplying each frequency by the number of bits, the amount of information on the occurrence can be immediately calculated. You can know.

Therefore, the convergence time of buffering processing can be shortened,
Also, the hardware can be simplified.

In this invention, by compressing the signal level, the amount of generated information is controlled based on the threshold value and the amount of generated information is controlled separately. - As an example, a threshold (limit value) is set as the limit at which deterioration of the restored image is recognized, and the amount of information generated at a predetermined threshold smaller than the limit value is compared with a target value. The compression coefficient α for the input data level is calculated based on this comparison output.When the amount of 0-generated information is less than the target value, it is determined as (α-1), and when the amount of generated information exceeds the target value, it is determined as (α-1). Therefore, when the amount of generated information is within the target value, the amount of generated information is reduced by compressing the input level.

Target value (transmission rate) for this compressed input signal
For example, a threshold value that is the maximum value that does not exceed is found, and signal processing is performed using this threshold value.
Even if the threshold value is not increased to the critical threshold value, the amount of generated information can be reduced and deterioration of the restored image can be prevented.

In other words, if the input level is compressed by multiplying it by α (α × 1), the frequency distribution of the dynamic range can be brought closer to the O side, and the amount of generated information can be reduced without increasing the threshold value beyond the limit value. can be reduced. This compression coefficient α is determined every predetermined period.

〔Example〕

A digital VTR to which the present invention is applied will be described in detail with reference to the drawings. This explanation is made according to the following items.

a. Configuration of transmitting side and receiving side, variable length quantization and puffing e. L threshold determination circuit d, modification. In the case of a digital VTR, the transmitting side corresponds to the recording side, and the receiving side corresponds to the reproducing side. handle.

a. Configuration of transmitting side and receiving side In FIG. 1, an analog video signal is supplied to the input terminal indicated by 1, this video signal is supplied to the A/D converter 2, and from the A/D converter 2, for example, 1 is supplied. , a digital video signal is obtained in which the samples are quantized to 8 bits. A digital video signal is supplied to a blocking circuit 3.

The blocking circuit 3 converts the input digital video signal into continuous signals for each two-dimensional block, which is a unit of encoding. The blocking circuit 3 subdivides one frame of screen, for example (488 lines x 720 pixels), into a large number of blocks. One block has a size of (4 lines x 4 pixels), for example, as shown in FIG.

A blocking circuit 3 generates a digital video signal converted into a block order.

The output signal of the blocking circuit 3 is supplied to a maximum value detection circuit 4 that detects the maximum value MAX for each block, a minimum value detection circuit 5 that detects the minimum value MIN for each block, and a delay circuit 6. The detected maximum value MAX and minimum value MIN are supplied to the subtraction circuit 7, and the dynamic range DR, which is the difference between the maximum value MAX and the minimum value MIN, is obtained from the subtraction circuit 7. The delay circuit 6 delays the data for the time required to detect the maximum value MAX and the minimum value MIN and for the time required to determine the compression coefficient α, which will be described later.

Video data from delay circuit 6 is supplied to compression circuit 14 . The compression circuit 14 is supplied with an address code Pi from a threshold determining circuit 9, which will be described later, and obtains an output signal from the compression circuit 14, which is the address code Pi multiplied by a compression coefficient α (≦1). The compression circuit 14 is composed of, for example, a ROM to which input data and compression coefficient α are supplied as addresses.

Address code Pi from threshold value determination circuit 9 is supplied to offset value generation circuit 16 . This offset value generation circuit 16 generates an offset value according to the compression coefficient α. This offset value generation circuit 16 is constituted by a ROM to which an address code Pl corresponding to the compression coefficient α is supplied as an address.

The output signal of the compression circuit 14 and the output signal of the offset value generation circuit 16 are supplied to the addition circuit 15, and the addition circuit 15 generates data to which an offset value has been added. The offset value can be added not only to the output side of the compression circuit 14 but also to the output side of the minimum value detection circuit 18, which will be described later.

A maximum value detection circuit 17 for detecting the maximum value MAX of the output signal of the adder circuit 15 for each block. The signal is supplied to a minimum value detection circuit 18 and a delay circuit 19 that detect the minimum value MIN for each block. The detected maximum value MAX and minimum value MIN are supplied to the subtraction circuit 20, and the maximum value MAX and minimum value ME
A dynamic range DR, which is the difference of N, is obtained from the subtraction circuit 20. The delay circuit 19 delays the output data of the compression circuit 14 for the time necessary to detect the maximum value MAX and the minimum value MIN.

The minimum value MIN is subtracted from the output signal of the delay circuit 19 by the circuit 2.
1, and the subtraction circuit 21 obtains data PDI after the minimum value has been removed. Data P after minimum value removal
DI is supplied to the encoding circuit 22. The encoding circuit 22 also receives an address code P from the threshold determining circuit 9.
1 and the dynamic range DR from the subtraction circuit 20.

The encoding circuit 22 performs variable length ADRC encoding to quantize the data PDI. In other words, the encoding circuit 22 quantizes the pixel data PDI from which the minimum value MIN shared by the pixel data in the block has been removed. A code signal DT corresponding to the value divided by the width Δi is formed. This encoding circuit 22 includes a threshold table that generates a threshold value from the address code Pi.

Since the video signal has two-dimensional correlation and three-dimensional correlation, the dynamic range DR within the block is smaller than the original data value, and there are 0 bits, 1 bits, and 1 bits less than 8 bits. Quantization distortion is not noticeable even when data is quantized with a bit number of 2, 3, or 4 bits.The encoding circuit 22 stores a threshold table for generating a threshold from the address code Pi. R
It is composed of an OM, pixel data PCI, a dynamic range DR, and a ROM that generates a code signal DT from the above-mentioned threshold value.

With digital VTRs, the transmission rate of recorded data is constant, so if the amount of transmitted data is not limited, some data may not be recorded, or the quality of the reproduced image will deteriorate due to unnecessarily high compression rates. I do things. Therefore, buffering processing is performed to perform optimal variable length encoding.

The dynamic range DR for each block detected by the subtraction circuit 7 is supplied to a frequency distribution generation circuit 8, and an integrated frequency distribution table is formed. This frequency distribution table is supplied to the threshold determining circuit 9 through a terminal 10. The threshold value determination circuit 9 is supplied with a reset signal of one frame period and a target value of the amount of generated information from terminals 11 and 12, for example. The threshold determining circuit 9 determines the compression coefficient α so that the transmission data rate is constant, and also determines the thresholds TI, T2 . T3. T4 is required.

The compression coefficient α is output from the output terminal 13, and the address code Pi corresponding to the threshold value is output from the terminal 25.

The address code Pi, dynamic range DR and minimum value MIN from the threshold determining circuit 9 and the code signal DT from the encoding circuit 22 are supplied to the framing circuit 23. The framing circuit 23 includes a code signal DT as variable length data, an additional code Pi as fixed length data,
Output terminal 24 of the framing circuit 23, which performs error correction encoding on DR and MIN and adds a synchronization signal.
Transmission data can be obtained. One address code Pi is transmitted for two frames of data, DR and MIN data are transmitted for each block, and a code signal DT is transmitted for each pixel.

The received data is supplied to an input terminal indicated by 31 in FIG.
It is decomposed into each of the minimum values MIN. Frame disassembly circuit 3
Address code pH dynamic range DR from 2,
Code signal DT is supplied to decoding circuit 33.

The decoding circuit 33 is the encoding circuit 2 of the ADRC encoder.
0, the code signal DT is converted to a restored level. This decoding circuit 33 is composed of, for example, a ROM. The restored level from the decoding circuit 33 is supplied to the adding circuit 34, and the minimum value MIN passed through the delay circuit 35 is added to the restored level. The restored data from the adder circuit 34 is supplied to the block decomposition circuit 36. Block decomposition circuit 3
Output data in the same order as the television signal is obtained at the output terminal 6. This restored signal is sent to the D/A converter 3.
7, and the analog video signal reproduced at the output terminal 38 is taken out.

b. Variable length quantization and buffering FIG. 5 explains variable length quantization performed in the encoding circuit 22. In the following description, TI,
T2. T3. T4 is a threshold value for determining the number of allocated bits, and is for the dynamic range DR. These threshold values have a relationship of (T4<T3<T2<TI).

Dynamic range DRC socket MAX-MIN) is (DR
-T4-1), as shown in FIG. 5A, only the maximum value MAX and minimum value MIN are transmitted, and on the receiving side, the intermediate level LO between the two is taken as the restoration level. Therefore,
As shown in FIG. 5A, the dynamic range DR is (T
4-1), the quantization width becomes ΔO. When the dynamic range DR is (0≦DR≦74-1), the number of allocated bits is 0 bits.

FIG. 5B shows a case where the dynamic range DR is (T3-1), and the dynamic range DR is (T4≦DR≦
At the time of T3-1), the number of allocated bits is set to 1 bit. Therefore, the detected dynamic range DR is divided into two level ranges, and the level range to which the pixel data PD■ after removing the minimum value of the block belongs is determined using the quantization width Δ1, and "0" corresponding to the level range is determined. or “1”
One code signal is assigned and the restoration level is LO.
Or Ll.

In the variable length coding shown in FIG. 5, the larger the dynamic range, the smaller the quantization width Δi (ΔO
Non-linear quantization is performed to increase Δ3<Δ4. Nonlinear quantization reduces the maximum distortion in blocks with a small dynamic range where quantization distortion is easily noticeable, and conversely increases the maximum distortion in blocks with a large dynamic range, thereby increasing the compression ratio.

When the dynamic range DR is (T2-1), as shown in FIG. 5C, the detected dynamic range D
R is divided into four level ranges, 2 bits (00) (01) (10) (11>) are assigned to each level range, and the center level of each level range is the restoration level LO, Ll. , L2°L3. Therefore, the level range to which the data PDI belongs is determined using the quantization width Δ2.The dynamic range DR is (T3≦DR≦T2−
In case 1), the number of allocated bits is 2 bits.

Furthermore, when the dynamic range DR is (T I -1), the detected dynamic range DR is divided into 8 level ranges, and 3 bits are set for each level range, as shown in Figure 5. (000) (001)
... (111) are assigned, and the center level of each level range is set as the restoration level LO, Ll...Ll. Therefore, the quantization width is Δ3. Dynamic range D
When R is (T2≦DR5TI-1), the number of allocated bits is 3 bits.

Furthermore, when the dynamic range is maximum 255,
As shown in Figure 5, the detected dynamic range DR is divided into 16 level ranges, and for each level range, 4 bits (0000) (0001)
... (1111) are assigned, and the center level of each level range is set as the restoration level LO, Ll...Ll5. Therefore, the quantization width is Δ4. When the dynamic range DR is (TI≦DR<256), the number of allocated bits is 4 bits.

FIG. 6 shows an example of a frequency distribution in which the horizontal axis is the dynamic range DR in the range (0 to 255) and the vertical axis is the frequency of occurrence. X 3+ X 4r X
As described above, each % represents the number of blocks included in the five ranges of the dynamic range DR divided by the thresholds T1 to T4. Since θ bits are assigned to blocks with a dynamic range DR of (T4-'1) or less, the number of blocks Xs does not contribute to the amount of generated information. Therefore, the amount of generated information is 4 XI + 3 Xt + 2 Xs + X4. Seek.

This amount of generated information is compared with a target value, and when the amount of generated information exceeds the target value, a larger set of threshold values is applied and the amount of generated information is calculated in the same manner. To perform the above equation, it is necessary to calculate the sum of the frequency distributions in each range for each set of set threshold values, multiply this sum by the number of allocated bits, and add the sum. However, if the above process is performed every time the threshold set is changed, a problem arises in that it takes time to find the optimal threshold set.

In this embodiment, in the frequency distribution generating circuit 8, the sixth
The frequency distribution shown in the figure is obtained, and then the frequency distribution shown in FIG. 6 is converted into the cumulative type frequency distribution shown in FIG. 7. By converting to a cumulative frequency distribution, different sets of thresholds and the corresponding amount of generated information can be calculated faster.
Therefore, the convergence time until an optimal set of threshold values is obtained is shortened.

As understood from Fig. 7, the dynamic range DR
starts from the maximum frequency of occurrence, and the frequencies of occurrence of smaller dynamic ranges DR are successively integrated to obtain an integrated frequency distribution graph.

Therefore, the cumulative frequency up to the threshold Tl is x, the cumulative frequency up to the threshold T2 is (X, +Xa), and the cumulative frequency up to the threshold T3 is (x, 1x, +xs). ,
The cumulative frequency up to threshold T4 is (X, +xt +x, +X
4).

The amount of generated information for the thresholds Tl to T4 is 4 (xt
0)+3 ((xt +X*) xt)+
2 ((X+ +x, +x,) (X+ +Xz
))+1 ((x, +x, +x= +Xa )-(xt
+xz +Xs)-4Xt +3x, +2XS +
1) [4 is found. If you first create the cumulative frequency distribution graph (cumulative frequency distribution table) shown in Figure 7, when you update the threshold set, you can immediately calculate the amount of generated information by the sum of the four numbers. be able to.

In this embodiment, a compression circuit 14 is provided, and the input level is multiplied by α. This means that the maximum value MAX and the minimum value MIN
will also be compressed, and the dynamic range DR will also be
In Fig. 6, the dynamic range D
This means that the distribution of R moves towards O. Therefore, by reducing α, the amount of generated information can be controlled to be smaller.

Since the entire signal level is multiplied by α, when (α × 1),
The brightness of the restored image will decrease.

Therefore, when the moving parts of the image increase and the amount of information increases, a problem arises in which the brightness suddenly decreases.

In this embodiment, since an offset value corresponding to the compression coefficient α is added to the data, the overall signal level increases as shown in FIG. Therefore, the reduction in brightness of the restored image is suppressed, and the above-mentioned problem is prevented from occurring. Also,
The offset value is set to a larger value as the value of α is smaller, and thus the compression ratio is larger, and the problem of lowering the overall brightness of the image can be effectively suppressed.

The limit value of each threshold value is the value immediately before the deterioration of the restored image is recognized when each threshold value is gradually increased, and such limit value can be set in advance based on the accuracy of the image. . Since the value of the compression coefficient α differs depending on the input data, it is determined by the threshold determining circuit 9. That is, in order to find the optimal compression coefficient α when the amount of generated information does not become less than the target value at a predetermined threshold value, the set of threshold values Tl to T4 are simultaneously set (1/
α) times, and the amount of generated information is determined.

c, L threshold determination circuit FIG. 4 shows an example of the threshold value determination circuit 9.

In FIG. 4, reference numeral 41 indicates a ROM in which a table of compression coefficients α is stored. The ROM 41 is supplied with an address code A1 from an address counter . The address counter 42 is supplied with a reset signal of one frame period from the terminal 11.

An example of the coefficient α table stored in the ROM 41 is shown in FIG. 10. The visual limit value of the coefficient α is a value at which problems such as block distortion are not visually noticeable when looking at the restored image. Ru. In the example of FIG. 10, the limit value of the coefficient α is 0
．． It is 70.

43 is a threshold generation circuit that generates a predetermined threshold set smaller than the limit value of the threshold of the assigned bits. The predetermined threshold value from the threshold generation circuit 43 is for determining the coefficient α at a threshold value that is gentler than the limit value. The set of predetermined threshold values from the threshold generation circuit 43 is supplied to the information amount calculation circuit 45 via the calculation circuit 44 which multiplies the set by (1/α).

The arithmetic circuit 44 is supplied with the coefficient α from the ROM 41 .

The information amount calculation circuit 45 is supplied with an integrated frequency distribution table from the terminal 10 . As described above, the amount of generated information corresponding to the predetermined threshold set multiplied by (1/α) from the arithmetic circuit 44 is determined by the information amount arithmetic circuit 45. The amount of information generated when the input data is compressed by α times is determined by multiplying the threshold value by (1/α), and the amount of information generated as 0 is supplied to the comparison circuit 46. The comparison circuit 46 includes
A constant value K is calculated by the subtraction circuit 47 from the target value M1 from the terminal 12.
The target value M2 from which is subtracted is supplied.

The output signal of the comparison circuit 46 is supplied as a clock to the address counter 42, and the address counter 42 is incremented by the output signal of the comparison circuit 46 generated when the amount of generated information is larger than the target value M2.The amount of 0 generated information is the target value M2. Incrementing is stopped when:

As shown in FIG. 1O, the initial value of the coefficient α is 1.

Therefore, the amount of generated information when the predetermined threshold value is reached is the target value M2
When the amount of information generated is less than the target value M2, it is always (α-1).
The value is gradually decreased to (α-0,70).

As described above, the coefficient α generated from the ROM 41 is determined. This coefficient α is supplied from the output terminal 13 to the compression circuit 14 and the offset value generation circuit 16. Therefore, when the amount of generated information for a set of predetermined threshold values is larger than the target value M2 and is set to (α<1), the level of the input data is compressed by this compression coefficient α. Then, the offset value generation circuit 16 generates an offset value corresponding to the coefficient α, and is added to the output signal of the compression circuit 14. The offset value is level compressed to compensate for the overall reduction in brightness.

After the compression factor α is determined, the bit allocation threshold is determined.

In FIG. 4, numeral 51 indicates a ROM in which a bit allocation threshold table is stored. The ROM 51 is supplied with an address code Pi from an address counter 52. A reset signal is supplied to the address counter 52 from the terminal 11 every frame. address counter 5
The address code Pi generated from 2 is taken out to the output terminal 25 and supplied to the encoding circuit 22 and the framing circuit 23.

An example of the threshold table stored in the ROM 51 is shown in FIG. ROM5J has (PO to P31) as address codes, and for example, the threshold value at (PI3) (T4-j!0.T3=/!1, T2=j!2.T
l-13) is considered to be the limit value. This threshold value T1~
The manner and magnitude of change in T4 are set while checking the image quality. The threshold value of the first address code PO is set to a very small value. Further, when calculating the amount of generated information, when the address code is sequentially changed toward P31, the amount of generated information is made to decrease monotonically.

A set of threshold values table read from the ROM 51 is supplied to the (1/α) times arithmetic circuit 53, and each threshold value T
I, T2. T3. T4 is multiplied by (1/α). This (1
/α) The set of multiplied threshold values is the information amount calculation circuit 54
supplied to The information amount calculation circuit 54 is supplied with an integrated frequency distribution table from a terminal IO. In the same manner as described above, the amount of generated information corresponding to the threshold set from the calculation circuit 53 is determined by the information amount calculation circuit 54. The determined amount of generated information is supplied to the comparison circuit 55.

The comparison circuit 55 is supplied with the target value Ml from the terminal 12. The output signal of the comparison circuit 55 is sent to the address counter 5.
The address counter 52 is incremented by the output signal of the comparator circuit 55, which is supplied as a clock to the address counter 52 and generated when the amount of generated information is larger than the target value.When the amount of generated information becomes equal to or less than the target value, incrementing is stopped. .

In the information amount calculation circuit 54 of the threshold value determination circuit 9 described above,
The amount of information generated for a set of threshold values in a threshold table using a cumulative frequency distribution table, that is, the code signal DT when ADRC encoding is performed by applying a selected set of threshold values. The total number of bits is calculated. In this case, calculation of the amount of generated information is started from the set of threshold values that minimize quantization distortion (the set of threshold values specified by the address code PO).

A comparison circuit 55 compares the determined amount of generated information and the target value M1. The target value M1 is the maximum value of the transmission rate of the transmission data, and when the amount of 0 generation information, which is (2 bits/1 pixel), is less than the target value, ADRC quantization is performed using the threshold set. is done. Therefore, the address code Pl when the amount of generated information is less than or equal to the target value is supplied from the output terminal 25 to the encoding circuit 22. If the amount of generated information exceeds the target value, the address counter 52
is incremented, the threshold set is updated, and then the same process as described above is repeated for a new threshold set that can reduce the amount of generated information. Then, the encoding circuit 22 performs ADRC encoding using the threshold set when the amount of generated information becomes equal to or less than the target value M1.

As described above, when the amount of generated information is large, the input level is compressed, so the amount of generated information is controlled to be below the target value. At this time, the compression coefficient α is determined as a value that does not cause the amount of generated information to exceed a predetermined target value M2 in the case of a predetermined threshold set smaller than the limit value. ADRC quantization is performed using a target value Ml for input data compressed by this compression coefficient α.
This is done using a threshold set with a maximum value that does not exceed (transmission rate). In this set of threshold values, since the amount of generated information is reduced to some extent by the compression coefficient α, the threshold value is less likely to be reached. Therefore, visual deterioration such as block distortion and edge business is reduced in the restored image.

Furthermore, since the compression circuit 14 performs level compression, the overall signal level decreases, but since an offset value corresponding to the compression ratio is added, the decrease in brightness is corrected in the restored image.

In addition to the code signal DT, the dynamic range DR,
The minimum value MIN, address code Pi, and redundant code of error correction code are transmitted, but since these data have a fixed length, when checking the transmission data rate, it is necessary to set an offset to the target value. Can be ignored.

d. Modification The present invention can also be applied to ADRC of three-dimensional blocks. For example, when a three-dimensional block is composed of two two-dimensional regions each corresponding to two frames, the number of pixels in one block is doubled. Also, ADRC of 3D block
In order to increase the compression rate, the presence or absence of movement is determined between two two-dimensional areas, and if there is movement, the pixel data of the two two-dimensional areas, that is, the code of all pixel data in the block, is determined. When there is no movement, the pixel data of one two-dimensional area is encoded. Therefore, the amount of generated information is (1:2) between the still part and the moving image part.

Furthermore, the present invention can also be applied to cases in which the maximum frame difference information for each block is taken into account in the buffering of the three-dimensional blocks described above, and when ADRC is performed after subsampling to increase the compression rate. can also be applied.

Furthermore, instead of outputting the address code Pt, the values of the thresholds T4 to T1 themselves may be outputted.

Furthermore, the present invention is not limited to buffering used in conjunction with a high-efficiency encoding method, but can be widely used for the purpose of keeping the amount of transmitted data constant.

[Effects of the Invention] In this invention, when the amount of generated information increases, the level of input data is compressed before encoding or other processing is performed, thereby preventing noticeable deterioration such as block distortion in restored image quality. can do. In addition, in this invention, the threshold value for bit allocation is determined after determining the compression coefficient α under predetermined conditions, so even in the case of (α minus 1), the threshold value is less likely to become the limit value. This makes it possible to prevent deterioration such as block distortion from occurring in the restored image.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the transmitting side of an embodiment of the present invention, FIG. 2 is a route diagram for explaining the blocks, and FIG.
The figure is a block diagram of the receiving side, Figure 4 is a block diagram of an example of a threshold determination circuit, Figure 5 is a route diagram for explaining variable length quantization, and Figures 6 and 7 are frequency distribution tables. FIG. 8 is a route map for explaining level compression, FIG. 9 is a route map for explaining adding offset values,
FIG. 10 is a route map of an example of a table regarding the compression coefficient α, and FIG. 11 is a route map of an example of a threshold table used for encoding. 41: 51: 42° 44° 45° 46° ROM storing a table of compression coefficient α, ROM storing a threshold table, 52 Near address counter, 53: (1/α) multiplication circuit, 54 : Information amount calculation circuit, 55: Comparison circuit. Agent Patent Attorney Masato Sugiura Explanation of main symbols in the drawing 1: Analog video signal input terminal, 3-niblock circuit, 4.17: Maximum value detection circuit, 5.18: Minimum value detection circuit, 7. 20.21: Subtraction circuit, 22: Encoding circuit, 9:
Threshold determination circuit, t Fig. 9 Fig. 11

Claims (1)

[Claims] A frequency aggregation means for aggregating the frequency of occurrence of each value of the data within a predetermined period; and a data amount is calculated based on a plurality of thresholds for each value of the data and the output of the frequency aggregation means. a first calculation means for calculating; a compression means for multiplying a signal related to the data by a coefficient α (α≦1); and a comparison output for comparing the output of the first calculation means with a target value. coefficient determining means for determining the value of the coefficient α according to the value of the coefficient α; threshold setting means for setting a plurality of threshold values for each value of the data; /α) second calculation means for multiplying, third calculation means for calculating the amount of data based on the threshold value from the second calculation means and the output of the frequency aggregation means; control means for comparing the output of the arithmetic means with a target value and controlling the threshold setting means in accordance with the comparison output to determine a set threshold; 1. An information amount control circuit comprising: processing means for processing based on a set threshold value from a threshold value setting means.