JPH0232656B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for transmitting data between central units or processors in a multiple processor system comprising one or several central units with multiple memories.

Two different techniques have been used for internal processor data transmission in multiple processor systems. That is, one is I/O technology and the other is DMA technology. Traditional I/
In Input/Output technology, a processor reads data sent by other processors one word or byte at a time, stores them in its memory, and reads them one word or byte at a time from this memory. read and write them to other processors via the data transmission bus. Furthermore, if the data transmission is fast, the write processor must ensure that the read processor must have time to read the previous data before the next data is written. This method of controlling data transmission is relatively slow due to the fact that a processor must have several different operations in order to transmit a word or a byte to another processor. Additionally, the use of I/O techniques slows down the processor's execution of other programs. This is because, during said operation, execution of other programs must be halted, which also requires additional storage and restoration of processor state. I/O techniques can only be used in cases of data transmission that is slow or has a limited amount.

Another method of controlling internal processor data transmission is DMA (Direct Memory Access) technology. This technique transmits data to and from the processor's memory without any practical involvement of the processor itself to the proper data transmission conditions. This is often accomplished by stopping the processors involved in the transmission operation during the transmission state. In this way, extra storage and recall operations performed in I/O technology can be avoided and transmissions can be made faster. The reason is that it can be implemented with logic circuits configured precisely for this purpose. In other words, this logic circuit does not read and store, for example, but instead stores the arriving data directly in memory.
However, this mode requires fairly complex logic circuitry, which makes the technique expensive. Additionally, this logic slows down the processor when the need for data transmission is high. The reason for this is that the length of the interruption time increases or the interruption time repeats at a high frequency. A similar situation occurs when there are several processors writing to or reading from the same memory. This is because such transmissions are generally possible between two processors at once. DMA technology has made it possible to implement such an arrangement in which internal processor data transfers occur to coupled memory. The system in this case has a memory that can be written to by all processors and read by all processors, but this memory is only used by one processor at a time. I can't. This makes it clear that any processor or at least DMA
technology also requires waiting for the completion of data transmission by other logic circuits or processors. In this way, in interfacing more than two, the interruptions caused by DMA techniques can be reduced, but still require waiting states for the appropriate transmission state. Other drawbacks of DMA technology are its thick busbars and fast data transmission signals that introduce insufficient interference tolerance.
DMA technology can be used when data transmission demands are high and there are not many devices that require simultaneous data transmission.

The object of the method and apparatus of the present invention is to eliminate the aforementioned drawbacks and to provide a reliable and economical data system for multiple processor systems.

The method according to the invention is characterized in that the data to be transmitted between the central units is separated from the local buses of the central units by a coupling memory, and the data transmission between the coupling memories is carried out by separate copying means. In this case, the advantage is that data can be transferred between the memories of the central unit without bothering the central unit.

According to a preferred embodiment of the method of the invention, the copying means simultaneously copies the write block of each central unit to the same block of all other central units. In this case, synchronization of the data processing processes performed by the central units connected to these combined memories is facilitated. The reason is,
This is because the copying means updates data in all combined memories simultaneously.

In a further preferred embodiment of the method of the invention, the copying means perform data transmission without interruption while the system is running.

In a third preferred embodiment of the method of the invention, updating of data between combined memories is performed without bothering the central unit. In this case, one central unit can have several combined memory buses, with the advantage that this central unit is not burdened by these combined memory buses.

According to a preferred embodiment of the method according to the invention, the data transmission between the combined memories is carried out in serial form 1...n bits in parallel.

According to a further advantageous embodiment of the inventive method, the addressing of the data in the copying phase takes place between the combined memories with the aid of special address counters synchronized by the copying means. A common advantage of these two embodiments is that address data does not need to be transmitted on the combined memory bus, so the combined memory bus can be kept thin. Furthermore, a narrow busbar width and its acceptable low speed mean that: This means that the manufacturing costs of this busbar can be reduced, and the central unit connected to this busbar can be easily electrically isolated, a measure which also reduces manufacturing costs.

The invention also relates to a device for carrying out the aforementioned method. The device comprises one or several central units with memory. The apparatus of the invention has the copying means connected to the combined memory bus, one combined memory for each central unit connected to the combined memory bus, and the combined memories connected to the central units by local buses. It is beneficial for the central unit to be able to perform normal write and read operations with combined memory. Another advantage is the low price of this device.

Hereinafter, the present invention will be explained in detail based on drawings and examples.

FIG. 1 is a block diagram illustrating the principle of the invention.

FIG. 2 is a block diagram showing the configuration of a combined memory having ancillary circuits.

FIG. 3 is a diagram showing a memory copy state.

For simplicity, the description of the invention will be limited to data transmission between central units. However, what is described below can also be applied, without much modification, to data transmission between internal processors of a central unit, for example. For example, when referring to a "central unit" in the method of the present invention, this term can be replaced with the term "processor." In the method of the invention, a very simple processor, hereinafter referred to as copying means 1, for transmitting data between the combined memories 2 is used. Data transmission takes place along the combined memory bus 5. The connection from the combined memory bus 5 to the central unit 3 is formed by each central unit's own so-called combined memory 2 and local bus 6. Since the combined memory bus 5 is driven at a low frequency and synchronously with the central unit, the use of the combined memory 2 of the central unit 3 does not affect the operation of the combined memory bus 5. A slightly more expensive way to operate the coupling memory 2 of the central unit 3 without affecting the operation of the coupling memory bus 5 is to adjust the operation of the coupling memory bus 5 with respect to the timing of the local buses of the central unit 3. Insert
During periods when the central unit 3 cannot be active with respect to the joint memory 2,
is used by the coupled memory bus 5. The combined memory 2 further includes a large number of sections (A, B,
C..., N). The copying means 1 is
The write memory of each central unit 3, shown as a hatched block in the figure, is simultaneously copied to the same block of all other central units.

The copying means 1 of the combined memory bus 5 are clock generators synchronized to the central unit 3. The central unit 3 is configured such that no change occurs on the address bus 18 of any central unit 3 and the combined memory bus 5
is connected to the combined memory bus 5 so that there is a period in which the address can be changed. The central unit addresses the combined memory by address bus 18. The copying means 1 generates at least the following signals to the combined memory bus 5. That is, clock pulse 7 and synchronization pulse 8
That is. This clock pulse increments the address counters 10 of all combined memories 2, and this synchronization pulse causes all address counters 10 to be checked at least once per copy round.

The basic principle for the operation of a coupled memory is as follows. That is, each copy in the combined memory bus 5 is performed at a sufficiently low speed that the central unit 3 can read from or write to the combined memory 2 in the middle of the copying phase without being disturbed by the operation of the combined memory bus 5. ie, the central unit 3 "steals" time or inserts operations from the combined memory 2, as explained above. The role of the address counter 10 is to operate in synchronization with the clock pulse 7 from the copying means 1, and to operate in accordance with the clock pulse 7 from the copying means 1.
It is to count the addresses to 2. Synchronization takes place by synchronization pulses 8. unit 11
is called a read/write selection unit. This is the logic unit that performs the selection between read and write blocks and their timing as described above. The sending data holding unit 13 performs the following operations. That is, while the central unit 3 continues writing to the bus 5,
When it is desired to use the RAM type memory 12, the data on the bus 5 can be held unchanged. It is also readily conceivable to those skilled in the art to add an incoming data holding unit 15 to the circuit. The RAM unit has terminals to the local bus 6 of the central unit 3 and to the combined memory bus 5. The bus buffer 14 is a circuit that allows the RAM type memory 12 and the combined memory bus 5 to be electrically shared.

It will be obvious to those skilled in the art that the present invention is not limited only to the embodiments described above, and that modifications and changes can be made within the scope of the present invention.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the principle of the present invention;
FIG. 2 is a block diagram showing the configuration of a combined memory having attached circuits, and FIG. 3 is a diagram showing a copy state of the memory. 1... Copy means, 2... Combined memory, 3...
Central unit, 4... Memory, 5... Combined memory bus, 6... Local bus, 10... Address counter, 11... Read/write selection unit, 12...
RAM type memory, 13... Sending data holding unit, 14... Bus line buffer, 15... Incoming data holding unit, 18... Address bus line.

Claims (1)

Claims: 1. A method for transmitting data between central units or processors in a multiprocessor system comprising a plurality of central units 3 having memories 4, comprising: A coupling memory 2 separates the central unit or processor from the local bus 6 and allows data transmission between the coupling memories 2 to be carried out by writing blocks of each central unit 3 or processor to the same block of all other central units or processors. A data transmission method characterized in that the data transmission method is carried out by separate copying means 1 that perform simultaneous copying. 2. A data transmission method according to claim 1, wherein the copying means 1 performs data transmission without interruption while operating the system. 3. The method according to claim 1 or 2, characterized in that the data between the joint memories 2 is completely updated without bothering the central unit 3 or the processor. Transmission method. 4. A data transmission method according to any one of claims 1 to 3, characterized in that the data transmission between the combined memories 2 is performed in serial format 1...n bits in parallel. 5. In the method according to any one of claims 1 to 4, the address of the data in the copying stage is transferred between the combined memories by a separate address counter 10 synchronized by the copying means 1. A data transmission method characterized by performing the following: 6 In a device for transmitting data between central units or processors in a multiprocessor system comprising a plurality of central units 3 having memories 4, the write block of each central unit 3 or processor is Alternatively, a copying means 1 for simultaneously copying the same block of processors is connected to the joint memory bus 5, one joint memory 2 for each central unit 3 or processor is connected to the joint memory bus 5, and a joint memory is connected to the joint memory bus 5 for each central unit 3 or processor. A data transmission device, characterized in that it is further connected to a central unit 3 or a processor by 6.