JPH02311943A - Wait action control circuit for cpu - Google Patents

Abstract

PURPOSE:To prevent the deterioration of the CPU processing speed by outputting a wait cancel signal to a CPU to control the wait action of the CPU after the prescribed wait number is counted when the CPU reads and write data out of and to a memory and other I/O devices. CONSTITUTION:The optimum wait number is individually set to a register circuit for each read/write action and for each device with the signal received from a CPU 1. Thus it is possible to deal with such a case where the change of the wait number of the CPU 1 is required owing to addition of a new memory or a new I/O device serving as a peripheral circuit of the CPU 1 or the exchange carried out to a new memory or a new I/O device just by correcting a program which actuates the CPU 1. Furthermore the optimum wait number can be individually set for each read/write action and then for each of devices like the memories 2 and 3, the I/O devices 4 and 5, etc. Thus it is possible to prevent the deterioration of the processing speed due to a fact that the excessive wait is forced to the CPU 1.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a method for reading and writing data from or to memory or other I/O devices (input/output devices) when a CPU (central processing unit) reads or writes data to or from memory or other I/O devices. After counting a predetermined number of waits, a wait release signal is output to the CPU, and the CPU
The present invention relates to an L wait operation control circuit that controls the wait operation of the L wait operation.

[Prior Art] FIG. 2 is a block diagram for explaining a conventional example of a wait operation control circuit for a CPU.
and 3 are memories, 4 and 5 are I/O devices, 6 is a conventional wait operation control circuit, and 7 is a chip selection circuit.

For the memories 2 and 3 and the I/O devices 4 and 5, C
The operations when the PT and TI read and write data are as follows.

When the CPUI reads data from the memory 2 or the memory 3, the CPU first outputs the address in the memory to be read onto the address bus b. Then, depending on the address input to the chip selection circuit 7, the chip selection circuit 7 selects either memory 2 or memory 3 and outputs either the chip selection signal e or the chip selection signal f. do. When the chip selection signal e is output, it means that the memory 2 is selected.

After outputting an address onto the address bus b, the CPU l outputs a memory data read signal onto the control bus a.

When memory 2 is selected, memory 2 outputs data onto data bus C in response to chip selection signal e and a memory data read signal on control bus a. The data output on the data bus C is taken into the CPUI. In this case, the wait operation control circuit 6 is operated by the memory data read signal outputted by the CPU, and after counting the number of waits of the CPU, which is a fixed value, outputs the wait release signal d to the CPU. do.

When the chip selection circuit 7 outputs the chip selection signal f, it means that the memory 3 is selected, and as in the case of the memory 2 described above, the memory 3 outputs data on the data bus C, and the data is is taken into CPU1.

Next, when the CPUI writes data to the memory 2 or the memory 3, the CPUI first outputs the address in the memory at which the data is to be written onto the address bus b. Then, the chip selection circuit 7 selects either the memory 2 or the memory 3 according to the address input to the chip selection circuit 7, and outputs either the chip selection signal e or the chip selection signal f.

When the chip selection signal e is output, it means that the memory 2 is selected.

The CPtJl outputs an address onto the address bus b, and then outputs data to be written onto the data bus C. Furthermore, the CPUI outputs a memory data write signal onto the control bus a.

When the memory 2 is selected, the memory 2 receives the data bus C output by the CPU 1 in response to the chip selection signal e and the memory write signal output to the control bus a.
Import the above data. In this case, the memory data write signal output on control bus a causes
The wait operation control circuit 6 operates and the CPU which is a constant value
After counting the number of waits, a wait release signal d is output to the CPUI.

When the chip selection circuit 7 outputs the chip selection signal f, it means that the memory 3 is selected, and as in the case of the memory 2 described above, the memory 3 takes in the data on the data bus C output by the CPUI. .

Next, when the CPUI reads data from the I/O device 4 or 1/O device 5, the CPU first reads the data from the address b.
At the top, output the address of the I/O device you want to read.

Then, according to the address input to the chip selection circuit 7,
The chip selection circuit 7 selects either the I/O device 4 or the I/O device 5, and outputs either a chip selection signal g or a chip selection signal. When the chip selection signal g is output, it means that the I/O device 4 is selected.

After outputting an address onto address bus b, the CPUI outputs an I/O data read signal onto control bus a.

If the I/O device 4 is selected, the I/O device 4 is
Data is output onto the data bus C in response to the chip selection signal g and the I/O data read signal on the control bus a. The data output on data bus C is
It is taken into l.

In this case, the wait operation control circuit 6 is operated by the I/O data read signal outputted by the CPU 1, and after counting the number of waits of the CPU which is a constant value, outputs the wait release signal d to the CPUI.

When the chip selection circuit 7 outputs a chip selection signal, it means that the I/O device 5 is selected, and the above-mentioned I/O
As in the case of device 4, I/O device 5 outputs data onto data bus C, and the data is taken in by CPUI.

Next, when the CPUI writes data to the I/O device 4 or the I/O device 5, the CPUI outputs the address of the I/O device to be written onto the address bus b. Then, the chip selection circuit 7 selects either the I/O device 4 or the I/O device 5 according to the address input to the chip selection circuit 7, and selects either the chip selection signal g or the chip selection signal R. Output a signal. When the chip selection signal g is output, it means that the ■/○ device 4 has been selected.

The CPU 1 outputs an address onto the address bus b, and then outputs data to be written onto the data bus C. Furthermore, the CPUI has I/O on the control bus a.
Outputs data write signal.

When the I/O device 4 is selected, the I/O device 4 receives the chip selection signal g and the I/O device output on the control bus a.
The data on the data bus C output by the CPU 1 is taken in by the O data write signal. In this case, the wait operation control circuit 6 is activated by the I/O data read signal output on the control bus a, and after counting the number of CPU waits, which is a constant value, the wait release signal d is sent to the CPU l. Output against.

When the chip selection circuit 7 outputs the chip selection signal, it means that the I/O device 5 is selected, and the I/O device 4
Similarly to the above case, the I/O device 5 takes in the data on the data bus C output by the CPU I.

In the above, the read and write operations by the CPU were explained, but in the case of the conventional device, the number of CPU waits counted by the wait operation control circuit 6 is
The memory 2, 3 is a fixed value determined when designing the peripheral circuits such as the memory 2.
It was commonly used when reading and writing to I/O devices 4 and 3 and I/O devices 4 and 5.

[Problems to be Solved by the Invention] By the way, the number of waits for a CPU varies depending on the performance of devices such as memory and I/O devices to be operated, and
Even when operating the same device, there may be differences between reading and writing. Therefore, the CPU
In order to improve processing speed, it is desirable to set the optimal number of waits for each device and read/write operation.

However, as described above, when the weight number of the wait operation control circuit 6 is set to a fixed value and one weight number is commonly used for various devices, for example, the memories 2 and 3 or the I/O device 4 The number of weights must be set according to the device that requires the largest number of weights within ゜5, and when other devices with smaller weight numbers are operating, it is necessary to force the CPU to use extra weight. There was a problem that this caused a delay in processing speed.

Furthermore, in the conventional wait operation control circuit 6, new memory or I/O devices can be added, or new memory or I/O devices can be added.
There is also a problem in that when it becomes necessary to increase the number of CPU waits by replacing the device, troublesome circuit changes must be performed, such as replacing the wait operation control circuit 6 itself. .

Furthermore, if the number of waits in the CPU can be reduced due to replacement of memory or I/O devices, etc., unless the wait operation control circuit 6 is replaced with one with a smaller number of waits, there will always be a surplus in the CPU. There is also the problem that the processing speed is further increased due to the heavy weights.

Therefore, solving these problems was considered a future problem.

The present invention was made in view of the above-mentioned circumstances, and by adding a new memory or I/O device as a peripheral circuit of the CPU or replacing it with a new memory or I/O device, it is possible to increase the weight of the CPU. Even if it is necessary to change the wait operation control circuit itself, there is no need for troublesome circuit changes such as replacing the wait operation control circuit itself, and it is also possible to prevent delays in processing speed caused by forcing the CPU to carry extra weight.
An object of the present invention is to provide a wait operation control circuit for a PU.

[Means for Solving the Problems] A wait operation control circuit for a CPU according to the present invention is a CPU wait operation control circuit according to the present invention.
When reading or writing data to or from a memory or other I/O device, a wait release signal is output to the CPU after counting a predetermined number of eights.
This controls the wait operation of the PU.

Specifically, the configuration includes a register circuit and a release signal output circuit.

The register circuit is configured such that the optimal number of waits is individually set for each read and write operation, and further for each device to be operated, in response to a signal from the CPU.

Further, the release signal output circuit is configured to output a wait release signal to the CPU after counting up to the optimum number of waits set in the register circuit.

[Function] The CPU wait operation control circuit according to the present invention sets the wait number using a register circuit, and since the wait number setting in this register circuit is based on a signal from the CPU, If it is necessary to change the number of CPU waits due to adding new memory or I/O devices to the circuit, or replacing it with new memory or I/O devices, please change the number of waits for the CPU to the program that operates the CPU. This can be done by simply making adjustments, and there is no need for troublesome circuit changes such as replacing the weight operation control circuit itself.

Moreover, in the register circuit, the optimal number of waits can be set individually for each read and write operation, and also for each device such as memory and I/O equipment, so that unnecessary waits are not forced on the CPU. This makes it possible to prevent delays in processing speed due to this, thereby making it possible to maximize the processing speed of the CPU.

[Embodiment] FIG. 1 shows an embodiment of a CPU wait operation control circuit according to the present invention, and FIG. 31 shows a CPU peripheral circuit including a wait operation control circuit 8 according to an embodiment. It is something that

In addition, in Fig. 3, the functions that are the same as before are as follows:
The same numbers as those in FIGS. 2 and 2 are given.

First, to memories 2, 3 and r7o devices 4, 5.

On the other hand, the operation when the CPU reads and writes data will be explained based on FIG. 3.

Before accessing the memories 2, 3 and I/O devices 4.5, the CPU 1 uses the data bus C to perform further processing on the wait operation control circuit 8 for each read and write operation. CP for each device to operate
Outputs a signal for setting the weight number of U. Then, read data from memory 2, write data to memory 2, read data from memory 3, and read data from memory 3.
Devices or operations such as writing data to, reading data from I/O device 4, writing data to I/O device 4, reading data from I/O device 5, and writing data to 1/O device 5. Each time, the optimum number of weights is individually held in a register circuit (described later) of the weight control circuit 8.

Next, when the CPU I reads data from memory 2 or memory 3, the CPU l first reads the data from the address bus b.
Output the address in memory you want to read. Then, the chip selection circuit 7 selects either memory 2 or memory 3 according to the address input to the chip selection circuit 7, and outputs either the chip selection signal e or the chip selection signal f. . When the chip selection signal e is output, it means that the memory 2 is selected.

After outputting an address onto the address bus b, the CPUI outputs a memory data read signal RM onto the control bus a.

When memory 2 is selected, memory 2 outputs data onto data bus C in response to chip selection signal e and memory data read signal Rs on control bus a. The data output onto the data bus C is taken into the CPU1. In this case, the wait operation control circuit 8 operates according to the memory data read signal R14 outputted by the CPUI and the chip selection signal e outputted from the chip selection circuit 7. Here, the wait operation control circuit 8 counts the wait number corresponding to "reading data from the memory 2" among the wait numbers set by the CPU' 1 before the first memory access, and then issues a wait release signal. Output d to cpul.

When the chip selection circuit 7 outputs the chip selection signal f, it means that the memory 3 is selected, and similarly to the case of the memory 2 described above, the memory 3 outputs data on the data bus C, and the memory 3 outputs data on the data bus C. Data is loaded into the CPUI.

Next, when the CPU 1 writes data to the memory 2 or the memory 3, the CPU outputs the address in the memory to be written onto the address bus b. Then, depending on the address input to the chip selection circuit 7, the chip selection circuit 7
selects either memory 2 or memory 3 and outputs either a chip selection signal e or a chip selection signal f.

When the chip selection signal e is output, it means that the memory 2 is selected.

After CPU I outputs an address onto address bus B, it transfers the data to be written onto data bus C.

Output. Furthermore, the CPUI outputs a memory data write signal WM onto the control bus a.

When memory 2 is selected, memory 2 writes the data on data bus C output by CP-Ul using chip selection signal e and memory data write signal W, 4 output on control bus a. take in. In this case, the wait operation control circuit 8 is operated by the memory data write signal WM outputted onto the control bus a and the chip selection signal e outputted from the chip selection 7.

Here, the wait operation control circuit 8 counts the wait number corresponding to "writing data to memory 2" among the wait numbers set by the CPU before the first memory access, and then transmits the wait release signal d to the CPU. Output for.

When the chip selection circuit 7 outputs the chip selection signal f, it means that the memory 3 is selected, and similarly to the case of the memory 2 described above, the memory 3 receives the data on the data bus C output by the CPU 1. take in. - Next 4i: CPU1 is I/O device 4 or l*I/O device 5
When reading the data, the CPU 1 first outputs the address of the I/O device to be read onto the address bus b. Then, depending on the address input to the chip selection circuit 7, the chip selection circuit 7 selects the I/O device 4 or the I/O device.
One of the O devices 5 is selected and a chip selection signal, either the chip selection signal g or the chip selection signal r, is output. When the chip selection output g is output, it means that the I/O device 4 has been selected. After outputting an address onto the address bus b, the CPU outputs an I/O data read signal R onto the control bus a.

If the I/O device 4 is selected, the I/O device 4 is
Data is output onto the data bus C in response to the chip selection signal g and the 170 data read signal R1 on the control bus a. The data output on data bus C is
Incorporated into PUI.

In this case, the wait operation control circuit 8 operates according to the I/O data read signal R1 outputted by the CPUI and the chip selection signal g outputted from the chip selection circuit 7. Here, the wait operation control circuit 8 counts the wait number corresponding to "reading data from the !/O device 4" among the wait numbers set by the CPU before the first I/O access, and then cancels the wait. A signal d is output to the CPU1.

When the chip selection circuit 7 outputs a chip selection signal, it means that the I/O device 5 is selected, and the above-mentioned I/O
Similarly to device 4, [/O device 5 outputs data onto data bus C, and the data is taken into CPU 1.

Next, when the CPUI writes data to the I/O device 4 or the I/O device 5, the CPUI writes data to the address bus b.
Output the address of the I/O device you want to write to. Then, according to the address input to the chip selection circuit 7, the chip selection circuit 7 selects either the I/O device 4 or the I/O device 5, and selects the chip from either the chip selection signal g or the chip selection signal R. Outputs selection signal. When the chip selection signal g is output, it means that the I/O device 4 has been selected.

The CPUI outputs the data to be written onto the data bus C after outputting an address onto the address bus b. Furthermore, the CPUI outputs an I/O data write signal W1 onto the control bus a.

When the r/○ device 4 is selected, the I/O device 4 receives the chip selection signal g and the I/O output on the control bus a.
The data on the data bus C output by the CPUI is taken in by the O data write signal W1. In this case, the wait operation control circuit 8 operates according to the I/O data write signal W1 outputted onto the control bus a and the chip selection signal g outputted from the chip selection circuit 7.

Here, the wait operation control circuit 8 selects ll/O out of the wait number set by the CPU before the first memory access.
After counting the number of waits corresponding to "data writing to device 4", a wait release signal d is output to the CPUI.

When the chip selection circuit 7 outputs a chip selection signal, it means that the I/O device 5 is selected, and similarly to the case of the I/O device 4 described above, the chip selection signal on the data bus C output by the CPU 1 is The I/O device 5 takes in the data.

Next, the configuration of the wait operation control circuit 8 in FIG. 3 is as follows.
This will be explained based on FIG.

The wait operation control circuit 8 outputs a wait release signal d to the CPU after counting a predetermined number of waits when the CPU reads or writes data to the memory 2.3 or the I/O devices 4 and 5. It controls the wait operation of the CPU, and specifically includes a register circuit IO and a release signal output circuit 20.

In this embodiment, the register circuit/O has a total of 8 register circuits/O.
It is formed by registers 11-18. Each register receives a signal from the CPUI via the data bus C, and before accessing the memory or I/O device starts, the register receives a signal from the CPUI.
The number of weights is set. Of these eight registers, register 11 is for "reading data from memory 2", register 12 is for "writing data to memory 2,"
Register 13 is for "reading data from memory 3",
Register 14 is for "writing data to memory 3", register 15 is for "reading data from ll/O device 4",
Register 16 is for writing data to I/O device 4, and register 17 is for reading data from N/O device 5.
The register 18 is for "writing data to the I/O device 5."

That is, each register constituting the register circuit/O is as follows:
They are prepared for different uses for each read and write operation, and also for each device operated by the CPU, allowing the optimal number of weights to be set individually for each operation and device.

The release signal output circuit 20 includes a total of eight counters 21 to 28 provided corresponding to each of the above-mentioned registers, and a total of eight counters provided corresponding to each of these counters to control the output of each counter. The device selected by the chip selection circuit 7 is configured to include AND gates 31 to 38 of After counting up to the number of waits set in the corresponding register and star,
A wait release signal d is output to the CPUI.

Each of the counters 21 to 28 described above has a corresponding register 21.
By receiving the signal from ~28 and the operation signal (read signal or write signal) from control bus a, the counting operation is started, and when the optimal weight number wheel set in the corresponding register is counted, the signal to appear.

Each of the AND gates 31 to 38 described above is connected to the chip selection circuit 7.
The chip selection signal from the control bus a, the operation signal from the control bus a, and the output signal of the corresponding counter are received, and when all these signals are present, the signal is output.

The above-mentioned AND gate 40 outputs a predetermined signal when receiving a signal from one of the AND gates,
The output signal of the OR gate 40 is a wait release signal for the CPUI.

The operation of the release signal output circuit 20 during read processing and write processing by the CPUI will be briefly described below.

When the CPUI performs a data read operation of the memory 2, the counter 21 and the counter 23 start counting operations in response to the memory data read signal RM outputted from the CPUI to the control bus a.

Counter 21 and counter 23 attempt to open gate 31 and gate 33, respectively, after counting the CPU wait numbers set in register 11 and register 13 by CPU 1, but the memory 2 chip selection signal e Therefore, only gate 31 opens and other gates 32 to 38 open.
won't open.

The signal i output from the gate 31 passes through the gate 40 and is sent to the CPU 1 as the weight release signal d.

Similarly, when reading data from the memory 3, after the counter 23 counts the wait number set in the memory 3 read register 13 by the CPU 1, the signal output from the gate 33 passes through the gate 40, and a wait release signal is sent. d
and send it to the CPUI as

When the CPUI writes data to the memory 2, the counter 22 is triggered by the memory data write signal WM.
and the counter 24 start counting operation. counter 2
2 and the counter 24 attempt to open the gate 32 and the gate 34, respectively, after counting the wait numbers set in the register 12 and the register 14, respectively, but due to the previous memory 20 chip selection signal e, the gate 32 (Other games) 31, 33-38 do not open.

The signal j output from the gate 32 passes through the gate 40 and is sent to the CPUI as the weight release signal d.

Similarly, when writing data to memory 3, C
After the counter 24 counts the wait number set in the memory 3 write register 14 by P and Ul, the gate 3
The signal 12 outputted from 4. passes through the gate 40 and is sent to the CPU 1 as a wait release signal d.

When the CPUI performs a data read operation of the ■/○ device 4, the counter 25 and the counter 27 count the weight H set in the register 15 and the register 17, respectively, according to the I/O data read signal Rr, and then
They try to open the gates 35 and 37, but only the gate 35 opens because of the previous I/O device 4 selection signal g. Then, the signal m outputted from the gate 35 passes through the gate 40 and is sent to the CPU 1 as the weight release signal d.

Similarly, when reading data from the I/O device 5, the gate 3
7 output signal 0. is sent to the CPU through the gate 40 as the wait release signal d.

When the CPUI writes data to the I/O device 4, the I/O
O data write signal W causes counter 26 and counter 28 to start counting operations. The counter 26 and the counter 28 are each set to the register 16 by the CPUI.
After counting the number of waits set in the register 18, each of the gates 36 and 38 is attempted to be opened, but only the gate 36 is opened due to the previous I/O device 4 selection signal g. The signal n outputted from gate 36 is output from gate 4
0 and is sent to the CPU 1 as a wait release signal d.

Similarly, when writing data to the I/O device 5, the output signal p of the gate 38 passes through the gate 40 and is sent to the CPU as the wait release signal d.

As is clear from the above description, the wait operation setting circuit 8 of the above embodiment sets the number of waits using a register circuit /O, and the number of waits in this register circuit IO is set by a signal from the CPUI. Therefore, if you add new memory or I/O devices to CPU1's peripheral circuits, or replace them with new memory or I/O devices, it becomes necessary to change the CPU weight number. This can be handled by simply modifying the program that operates the CPU, and there is no need for troublesome circuit modification work such as replacing the wait operation control circuit 8 itself.

Moreover, in the register circuit/O, the optimal number of waits can be set individually for each read and write operation, and also for each device such as memory and I/O equipment, so there is no unnecessary weight on the CPU. It becomes possible to prevent delays in processing speed caused by forcing
This makes it possible to maximize the processing speed of the CPU 1.

[Effects of the Invention] As is clear from the above description, the CPU wait operation setting circuit according to the present invention sets the wait number using a register circuit, and the wait number setting in this register circuit is performed by the CPU. Since it is based on signals from
If you need to change the number of CPU weights due to adding an O device or replacing with a new memory or I/O device, you can do so by simply modifying the program that operates the CPU. There is no need for troublesome circuit modification work such as replacing the weight operation control circuit itself.

However, in the register circuit described above, the optimal number of waits can be set individually for each read and write operation, and also for each device such as memory and I/O equipment, so it does not force the CPU to perform extra waits. It becomes possible to prevent delays in processing speed caused by this, and thereby it becomes possible to maximize the processing speed of the CPU.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the configuration of one embodiment of the present invention, FIG. 2 is an explanatory diagram of a CPU peripheral circuit including a conventional wait operation control circuit, and FIG. 3 is a CPU peripheral circuit including the above-mentioned embodiment. FIG. l...CPU, 2.3...Memory, 4
, 5... I/O device, 6... wait operation control circuit, 7... chip selection circuit, 8...
...Wait operation control circuit, /O...Register circuit, 11-18...Register, 20...
. . . Release signal output circuit, 21 to 28 . . . Counter, 31 to 38 . . . AND gate, 40.
・・・・・・Logical sum gate.

Claims (1)

[Claims] When a CPU reads or writes data to a memory or other I/O device, after counting a predetermined number of waits, a wait release signal is output to the CPU to perform a wait operation of the CPU. A register circuit that controls the wait operation control circuit, in which the optimum number of waits is individually set for each read and write operation and also for each device to be operated, according to a signal from the CPU; and a release signal output circuit that outputs a wait release signal to the CPU after counting up to the optimal number of waits.
Wait operation control circuit.