JPH02310738A - Microprocessor ic - Google Patents

Abstract

PURPOSE:To trace the operating state of a microprocessor IC in real time by providing a buffer which stores the trace data of a processing executed in the inside at every execution unit. CONSTITUTION:The address of an instruction and the content of a register, etc., executed in a central processing unit 2 are sent to a buffer part 5 via an internal data bus 9 as the trace data 8, and a buffer control part 6 sends the address and write information to the buffer part 5 by using an internal address bus 19 and a read/write control signal line 16, and writes them on the buffer part 5 as the trace data 8. A data bus switching part 7 is operated by making active a read requesting signal line 22 from the outside, and the trace data can be read out from the buffer part 5 to the outside via an internal data bus 14 and a data bus 21. In such a manner, it is possible to trace the operation of the microprocessor IC 1-2 regardless of the presence/absence of corresponding data in a cache memory part 4.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a microprocessor IC with a built-in cache.
Regarding.

[Conventional technology]

These seven types of conventional microprocessor ICs, as shown in FIG. and 17, an internal data bus 13, a data bus control signal line 18, an external memory access request bus 20, and a data bus 21.

The microprocessor ICl-3 shown in FIG.
When a request is made to the cache control section 3 to read an execution instruction through the cache control section 10 and 12, the cache control section 3 searches the cache memory section 4 for the corresponding instruction. As a result of the search, if there is a corresponding instruction in the cache memory unit 4, the cache control unit 3 reads it through the internal bus 1゛7, and through the internal buses 12, 10゜11,
A command is sent to the central processing unit 2. As a result of the search, if there is no corresponding instruction in the cache memory section 4, the cache control section 3 sends an instruction via the external memory access request bus 20.
Outputs address and read control information to external memory. This causes the instruction to be read from external memory. At this time, the cache control section 3 controls the data bus switching section 7 using the data bus control signal line 18 to connect the data bus 21 and the internal data bus 13. The read instructions are transferred to the data bus 21. Internal data bus 1
3. It is sent to the central processing unit 2 via internal buses 10 and 11. As a result, the instructions sent by the central processing unit 2 are executed. If the instruction to be executed at this time is an instruction that requests reading from an external memory, the reading process is performed by the central processing unit 2 in the same manner as the procedure for reading the instruction. At this time, the microprocessor ICl-3
The state is not traced internally.

[Problem to be solved by the invention]

As described above, in a microprocessor IC having a built-in cache, whether or not the external memory is accessed depends on whether or not the internal cache memory section stores necessary data.

In other words, when the necessary data is stored in the internal cache memory section, no access request is made to the external memory, so the external memory access l bus 2
Information such as address and status is not output from the microprocessor IC through 0. Therefore, the operating state of this microprocessor IC is
When tracing externally, cache-related operations are stopped and all processing is performed by the microprocessor IC.
This has the disadvantage that real-time performance is lost because information must be output to the outside of the microprocessor IC, and tracing is performed in a state different from the actual operation of the microprocessor IC.

[Means to solve the problem]

The microprocessor IC of the present invention is a cache built-in microprocessor IC, and stores trace data for each execution unit, including address values and data values of internally executed instructions, and information indicating the distinction between the execution units. a buffer for controlling the trace data, and a control means for controlling writing and reading of the trace data to the buffer;
and an external terminal for inputting a control signal from the outside to the control means.

〔Example〕

Next, a first embodiment of the present invention will be described using FIG. 1.

1-1 is a microprocessor IC, 2 is a central processing unit,
3 is a cache control unit, 4 is a cache memory unit, 5 is a buffer unit, 6 is a buffer control unit, 7 is a data bus switching unit, 8 is trace data, 9.13 and 14 are internal data buses, 10, 11゜12 and 17 is an internal bus, 15
1 is a write request signal line, 16 is a read/write control signal line, 18 is a data bus control signal line, 19 is an internal address bus, 20 is an external memory access request bus, 21 is a data bus, 22 is a read request signal line, 23 is the read response signal line.

First, in the microphone p processor ICl-1, the tracing operation is selected depending on the state of the read request signal line 22. That is, it has two functions: performing a trace operation when the read request signal line 22 is inactive, and interrupting the trace operation and reading trace data from the buffer unit 5 when the read request signal line 22 is active. Each function will be explained below.

When performing trace operation, external read request signal line 2
Make 2 inactive. As a result, the data bus switching unit 7 operates to switch between the data bus 21 and the internal data bus 13.
Connect. Next, when the central processing unit 2 requests reading of an instruction, the instruction is sent to the central processing unit 2 in accordance with the operation described in the prior art. This causes the central processing unit 2 to execute the command. At this time, the address of the executed instruction, the contents of the register, etc. are sent as trace data 8 to the buffer section 5 through the internal data bus 9.

Further, the central processing unit 2 requests the buffer control unit 6 to write the trace data 8 to the buffer unit 5 through the internal bus 11.10 and the write request signal line 15. In response to this, the buffer control section 6 sends the address and write control information to the buffer section 5 using the internal address bus 19 and the read/write control signal line 16. As a result, the trace data 8 is written into the buffer section 5. Next, the buffer control unit 6 increments the address and repeats the above operation. In this way, trace data is written sequentially.

When reading trace data from the buffer section 5, the read request signal line 22 is made active from the outside. As a result, the data bus switching section 7 operates to connect the data bus 21 and the internal data bus 14. next,
The buffer control section 6 sends the address and read control information to the buffer section 5 using the internal address bus 19 and the read/write control signal line 16 as in the case of writing. As a result, trace data is read out from the buffer section 5 through the internal data bus 14 and the data bus 21.

Next, the buffer control unit 6 increments the address and repeats the above operation. In this way, the trace data is read out sequentially, and when the final address of the buffer section 5 is reached,
The buffer control unit 6 notifies the outside via the read response signal line 23 that reading of this trace data is completed. In contrast, reading is completed by making the read request signal line 22 inactive externally.

FIG. 2 is a block diagram of a second embodiment of the invention. The microprocessor IC shown in FIG. 2 has the same basic operation as the first embodiment shown in FIG. ing.

According to the embodiment shown in FIG. 2, only the trace data of a necessary process execution unit can be stored in the buffer section.

〔Effect of the invention〕

As explained above, the present invention provides a microprocessor I
It has a buffer that stores trace data of processes executed inside C for each execution unit, and can be read out using an external control signal, regardless of the presence or absence of the corresponding data in the built-in cache memory. This has the effect of being able to trace the operation of the microprocessor IC.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a block diagram of a second embodiment of a MyMelo processor IC of the present invention, and FIG. 3 is a block diagram of a conventional cache-embedded microprocessor IC. It is a block diagram. 1-1.1-2.1-3...Microprocessor IC, 2...Central processing unit, 3...
Cache control unit, 4... Cache memory unit, 5... Buffer unit, 6... Buffer control unit, 7... Data bus switching unit, 8.・・・
...Trace data, 9,13゜14...Internal data bus, 10,11,12.17...Internal bus, 15...Write request signal line, 16・・・
...Read/write control signal line, 18...
Data bus control signal line, 19... Internal address bus, 20... External memory access request bus,
21...mark/data bus, 22...read request signal line, 23...read response signal line.

Claims (1)

[Claims] In a microprocessor IC with built-in cache,
A buffer that stores trace data for each execution unit, including address values and data values of internally executed instructions, and information indicating the distinction between the execution units, and a control that controls writing and reading of the trace data to and from the buffer. and an external terminal for inputting a control signal from the outside to the control means.