JPH02305282A - Picture information transmission system - Google Patents

Abstract

PURPOSE:To efficiently transmit picture information of high quality by using data free from error, which corresponds to the same picture as data where error occurs, to interpolate data where error occurs at the time of the occurrence of error of data on a transmission line. CONSTITUTION:If maximum value data Dmax, minimum value data Dmin, or a division code i,j is erroneous, an address generating circuit 208 outputs the read address, which reads out Dmax, Dmin, or i,j in transmission data corresponding to picture element blocks placed in the periphery on the picture or in picture element blocks, to a memory 202 in response to error detection data supplied from an error detection data memory 206. A calculating circuit 209 uses data supplied from the memory 202 to calculate interpolating maximum value data Dmax', interpolating minimum value data Dmin', and an interpolating division code i,j' and supplies them to the terminal A of a data selector 207. Consequently, the transmission efficiency is improved because unnecessary data is not transmitted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to an image information transmission system, and particularly to an image information transmission system that enables highly efficient encoding.

[Prior Art] Conventionally, as this type of image information transmission system, for example, a high efficiency encoding system for television signals has been known. This television signal high-efficiency encoding system adopts the so-called old N-MAX method, which reduces the average number of bits per pixel due to the necessity of narrowing the transmission band. This MIN-MAX method will be explained below.

Television signals have strong spatiotemporal correlation. When an image is divided into small blocks, each block often has only a small dynamic range due to local correlation. Therefore, very efficient compression can be achieved by determining the strength of each block and adaptively encoding it.

Therefore, with specific reference to the drawings regarding this encoding,
I'll explain.

FIG. 3 is a diagram showing a schematic configuration of an image information transmission system as an example of conventional technology. Reference numeral 301 in the figure is an input terminal, which samples a raster-scanned analog image signal such as a television signal at a predetermined frequency.
Digital image data digitized into n bits of data per sample is input. This 2n gradation digital image data is supplied to the pixel block division circuit 302.

FIG. 4 is a diagram showing how all pixel data for one screen is divided into pixel blocks. Pixel block division circuit 302
, all pixel data for one screen is stored in a memory etc., and as shown in Fig.
Pixel data is read out in units of pixel blocks each consisting of (text x m) pixels, with text pixels in the vertical direction (hereinafter referred to as the ■ direction) and m pixels in the vertical direction (hereinafter referred to as the ■ direction). That is, output is performed for each data of each pixel block.

FIG. 5 shows the configuration of each pixel block. In the figure, Dl,
l~D-1? indicates each pixel data.

The image data output from the pixel block division circuit 302 is sent to the maximum value detection circuit 303. If the minimum value detection circuit 3 (14) is inputted to the timing adjustment circuit 305, all pixel data (D, 1 to D, . . .
, ), the one with the maximum value (D, a,) and the one with the minimum value (Dl, .).
4 and output.

On the other hand, in the timing adjustment circuit 305, the maximum value detection circuit 3 (13) and the minimum value detection circuit 3 ()4 are D□.+
All pixel data is delayed by the time required to detect Dmi'n, and the pixel data is sent to the division value conversion circuit 306 in a predetermined order for each pixel block. For example, Dl, l, D2.1103 for each pixel block
．． 1+..., D1□+D1.2+...+DIm, 2
++++ + Dl, (J-+1 +
-” + Dm ku (6-11+ Dl,
/? ”' + D incense Al.

In this way, all pixel data (Dl
, +~D-,, ) and their maximum values (D, , , X) and minimum values (D□, .) are input to the division value conversion circuit 306, and for each pixel data, D
It is compared with the quantization level obtained by dividing n into 2 to obtain a 2-bit division code (Δ11 to Δyo1.). Here, k is an integer smaller than n, and the state of its quantization is shown in Figure 6 (
Shown in a).

As shown in FIG. 6(a), △ and J are output as two-bit binary symbols. The bit division code △1 obtained in this way. ．． and n-bit glue. aX and Dmin
are parallel-to-serial (p-s) converters 307, respectively.
, 307', 307'' as serial data,
The data selector 308 converts the data into serial data as shown in FIG. 7(a).

The data output from the data selector 308 is added with a p-bit error correction code by the error correction code addition circuit 309 as shown in FIG. ), a time axis adjustment process is performed so that a constant data transmission rate I~ is applied, and a synchronization signal (=J) is added by a synchronization adder circuit 311, and the transmission line (for example, a VTR (magnetic recording/reproducing system).

Regarding the addition of synchronization signals, for each pixel block,
This may be performed for each of a plurality of pixel blocks. Note that the operation timing of each of the circuits described above is determined based on a timing signal output from the timing control section 313.

FIG. 8 is a clock diagram showing a schematic configuration of a receiving side corresponding to the data transmitting side shown in FIG. 3. FIG. In FIG. 8, reference numeral 821 is a terminal to which the transmission data encoded with high efficiency on the transmission side described above is input, and the input transmission data is supplied to a synchronization signal separation circuit 822 and an error correction circuit 823.

The synchronization signal separation circuit 822 separates a synchronization signal from the input transmission data and supplies it to an error correction circuit 823 and a timing control circuit 83.

The error correction circuit 823 includes a synchronization signal separation circuit 8
In synchronization with the synchronization signal supplied from 22, the error correction code in the transmission data is separated, and according to the error correction code, data errors occurring on the transmission path are detected, and after correcting them, the data is is supplied to selector 824.

Further, the roll circuit 831 to the timing controller 1 controls the operation timing of each circuit on the receiving side based on the synchronization signal supplied from the synchronization signal separation circuit 822.

On the other hand, in the data selector 824, the transmission data is sorted into data Dma*+Dmtn of the middle hit, and codes △□ and j obtained by bit quantization between each pixel data, , X, D□, and n. These are converted into parallel data by serial-parallel (s-p) converters 825 and 825', respectively. The maximum value data Dmax and the minimum value data D□ in each pixel block are converted into parallel data by the sp converter 825. are latched by latch circuits 826 and 827, respectively, and the latched maximum value data DIIlaM and minimum value data Dmin are output to a divided value inverse conversion circuit 828, respectively. On the other hand, the division code △1, 4 for each pixel data in each pixel block
are outputted by the S-P converter 825' in the predetermined order as described above, and supplied to the divided value inverse conversion circuit 828.

FIG. 6(b) shows division codes △i, j and D mnk+D
mi.

, j is decoded from the original pixel data. As shown in the figure, the representative value is, for example, I.
l'1llaxl Dmi. is set to the middle of each quantization level divided into two. The n-bit representative illumination data CD' obtained from the division value inversion circuit 828 in this way
r, +~o L , , ) are output for each pixel block in the above-mentioned order. The scan converter circuit 829 converts the output data of the divided value inverse conversion circuit 828 into an order corresponding to raster scan, and outputs it to an output terminal 830 as decoded image data.

[Problems to be Solved by the Invention] However, in the above conventional example, in order to correct data errors that occur on the transmission line, the transmitting side adds an error correction code to the transmitted data, and then The error correction code is used on the receiving side to correct data errors that occur on the transmission path, and the redundancy of the transmitted data increases by the amount of the error correction code, resulting in poor transmission efficiency. It was something that didn't exist.

SUMMARY OF THE INVENTION In view of the above-mentioned points, an object of the present invention is to provide an image information transmission system that can efficiently transmit high-quality image information.

[Means for solving the problem] The image information transmission method of the present invention divides the plurality of pixel data for one screen into a plurality of pixel blocks for each predetermined number of pixel data, and Sending distribution data representing the distribution of data values and position data representing where each pixel data in the block is located in the distribution of values of the pixel data represented by the distribution data onto a transmission path;
If an error occurs in the data on the transmission path, the data with the error is interpolated using data that corresponds to the same screen as the data where the error occurred and does not have an error. It is characterized by forming interpolated data for

[Operation] With the method described above, even if there is an error in the data on the transmission path when transmitting image information, the image information can be transmitted using data that corresponds to the same screen as the error-prone data and that does not contain the error. It becomes possible to interpolate data where errors have occurred.

[Example] The present invention will be explained below using examples of the present invention.

FIG. 1(a) shows a schematic configuration of a transmission system in an image information transmission system as an embodiment of the present invention.

In FIG. 1(a), the same components as in FIG. 3 are given the same reference numerals, and detailed explanations will be omitted.

The transmission system shown in FIG. 1(a) differs from the transmission system No. 1 shown in FIG. As shown in FIG. 1(b), it is configured to add an error detection code of q bits and r bits and supply it to the FTFO memory 310.

With the above-described configuration, the error detection code added in the error detection code addition circuit 101 needs to have an extremely smaller number of bits than the error correction code in order to detect whether or not an error has occurred in the data. Redundancy of transmitted data can be reduced.

Further, FIG. 2 shows a schematic configuration of a receiving system in an image information transmission system 8 as an embodiment of the present invention.

In FIG. 2, 201 is an input terminal to which transmission data (see FIG. 1(b)) encoded with high efficiency in the transmission system shown in FIG. 1(a) is input; The data is supplied to memories 202 and 203, an error detection circuit 204, and a synchronization signal separation circuit 205.

The synchronization signal separation circuit 205 separates a synchronization signal from the input transmission data and supplies it to an error detection circuit 2114 and a timing control circuit 217.

The timing control circuit 217 controls the operation timing of each circuit on the receiving side based on the synchronization signal supplied from the synchronization signal separation circuit 205.

Further, transmission data inputted from the input terminal 201 is sequentially stored in memories 202 and 203, and is stored in the error detection circuit 204.
is the maximum value data D□aX+minimum value data Dmin+division code △ in the transmission data input from the input terminal 201.
0. Error detection data indicating which of the errors is incorrect is output, and the error detection data output from the error detection circuit 204 is stored in an error detection data memory 206.

As described above, after the transmission data corresponding to the image data for the field is stored in the memory 2 fl 2 , 2 [13, and the error detection data corresponding to the transmission data is stored in the error detection data memory 206, Start reading data stored in each memory. In addition, while each memory is reading data, each memory is being supplied with newly input transmission data or error detection data, and each memory is receiving data instead of the read data. Stores newly supplied data.

The transmission data stored in the memory 203 is read out in the order in which it was stored, and is supplied to the B terminal of the data selector 207 in the figure.

In addition, the address generation circuit 208 responds to the error detection data supplied from the error detection data memory 206, and if the maximum value data Dmax or the minimum value data Dmin is incorrect, the pixels located around the screen are Do or Dmi in the transmission data corresponding to the block
The read address for reading n is output to the memory 202, and if the division code △i, j is incorrect, △I+J corresponding to the surrounding pixels in the pixel block is output.
The read addresses 1 to 1 for reading out are output to the memory 202, and the address generation circuit 208 is output from the memory 202.
The stored data is read out according to the read address output from the arithmetic circuit 209 and supplied to the arithmetic circuit 209 .

Then, the arithmetic circuit 209 uses the data supplied from the memory 202 to generate interpolated maximum value data DIRal+'+
Interpolated minimum value data D. , n', interpolation division code △0. J'
is calculated and supplied to the A terminal of the data selector 207 in the figure.

On the other hand, the error detection data read from the error detection data memory 2()b is also supplied to the data selector control circuit 210, and the data selector control circuit 210 detects a data error caused by the supplied error detection data. If it is instructed that no data error has occurred, connect the data selector 207 to the A terminal side in the figure, and if it is instructed that no data error has occurred, connect the data selector 207 to the B terminal side in the figure. However, if an error occurs in the transmission data read from the memory 203, the erroneous data is replaced with interpolated data output from the arithmetic circuit 209 and output.

Then, the transmission data outputted from the data selector 207 is converted into n-bit data DmR + Dmin and a division code by the data selector 21'l. .

Serial-Parallel (S-P)
The data is converted into parallel data by converters 2], 2, and 213.

The maximum value data Dmaw and minimum value data Dmin, which are converted into parallel data by the S+P converter 212, are latched by latch circuits 214 and 21.5, respectively, and the latched maximum value data Dmax and minimum value data D0, □
are respectively supplied to the divided value inverse conversion circuit 216.

Further, the divided codes Δi,j converted into parallel data by the S-+P converter 2]3 are also supplied to the divided value inverse conversion circuit 216.

Then, in the divided value inverse conversion circuit 216, the eighth
Similar to the receiving system shown in the figure, division codes △□, J and D I
ll,,X + D m I. The representative value data of n hits related to the original pixel data D0. J is decoded and supplied to the scan converter circuit 218, and the scan converter 1
~A circuit 218 converts the output data of the divided value inverse conversion circuit 2]6 into an order corresponding to raster scanning, and outputs it from an output terminal 219 as decoded image data.

As explained above, even if highly redundant data such as error correction codes are not added when transmitting image data, errors in the data that occur on the transmission path can be easily detected due to deterioration in image quality. Since no extra data is transmitted, transmission efficiency can be improved.

[Effects of the Invention] As explained above, according to the present invention, it is possible to provide an image information transmission system that efficiently transmits high-quality image information.

[Brief explanation of the drawing]

FIG. 1(a) is a schematic configuration diagram of a transmission system of an image information transmission system as an embodiment of the present invention, and FIG. 1(b) is a transmission output from the transmission system shown in FIG. 1(a). A diagram showing a data string; FIG. 2 is a schematic configuration diagram of a receiving system of an image information transmission system as an embodiment of the present invention; FIG. 3 is a schematic configuration diagram of a transmitting side of an image information transmission system according to the prior art; Figure 4 is a diagram showing how all image data is divided into pixel block groups, Figure 5 is a diagram showing the data arrangement of each pixel block, and Figure 6 (a) is the conversion of the division value conversion section in Figure 3. FIG. 6(b) is a diagram showing the conversion characteristics of the divided value inverse converter in FIG. 8. FIG. 7(a) is a diagram showing the data string output from the data selector 308 in FIG. Figure 7(b) is a diagram showing the transmission data string output from the transmission system shown in Figure 3, and Figure 8 corresponds to the transmission side of the image information transmission system shown in Figure 3. FIG. 2 is a diagram showing a schematic configuration of a receiving side. 101...Error detection code addition circuit 202.203...Memory 204...Error detection circuit 206...Error detection data memory 17
, -207...Data selector 208...Address generation circuit 209...Arithmetic circuit 210...Data selector control circuit ^^ 18

Claims (1)

[Scope of Claims] A method of transmitting image information in which one screen is composed of a plurality of pixel data, wherein the one screen of the plurality of pixel data is divided into a plurality of pixel blocks for each predetermined number of pixel data. distribution data representing the distribution of pixel data values within each block, and position data representing where each pixel data within the block is located in the distribution of pixel data values represented by the distribution data. If an error occurs in the data on the transmission path, use data that corresponds to the same screen as the data in which the error occurred and that does not have an error to detect the occurrence of the error. An image information transmission method characterized by forming interpolated data for interpolating existing data.