JPH02298109A - Integrated type piezoelectric thin film functional element - Google Patents

Integrated type piezoelectric thin film functional element

Info

Publication number
JPH02298109A
JPH02298109A JP11836689A JP11836689A JPH02298109A JP H02298109 A JPH02298109 A JP H02298109A JP 11836689 A JP11836689 A JP 11836689A JP 11836689 A JP11836689 A JP 11836689A JP H02298109 A JPH02298109 A JP H02298109A
Authority
JP
Japan
Prior art keywords
thin film
piezoelectric thin
resonator
integrated circuit
film resonator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11836689A
Other languages
Japanese (ja)
Inventor
Hitoshi Suzuki
仁 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP11836689A priority Critical patent/JPH02298109A/en
Publication of JPH02298109A publication Critical patent/JPH02298109A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the reduction of the insulation resistance of a piezoelectric thin film resonator by capacitively coupling a piezoelectric thin film resonator and an integrated circuit with a coupling capacitor formed by using a passivation film as a dielectric layer to suppress the diffusion of electrode metallic atoms to the resonator. CONSTITUTION:A piezoelectric thin film resonator 2 made of a ZnO piezoelectric film on a semiconductor substrate 1 and an integrated circuit circuit 3 forming an oscillation circuit are formed integrally. Then connection pads 6a, 6b are provided to the part opposite wiring patterns 5a, 5b of the integrated circuit 3 and wiring patterns 4a, 4b of the piezoelectric thin film resonator 2. The piezoelectric thin film resonator 2 and the integrated circuit 3 are capacitively coupled via coupling capacitors Ca, Cb formed by using the connection pads 6a, 6b whose pattern faces are opposite to each other as electrodes and the passivation film 7 to protect the pattern face as the dielectric layer. Since the DC potential fed to the piezoelectric thin film resonator is suppressed lower, the characteristic deterioration of the resonator caused by the deterioration of the insulation resistance due to the state of DC potential is prevented.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) この発明は圧電薄膜を振動膜に用いた共振子と半導体集
積回路とを同一基板上に一体化して構成した集積型圧電
薄膜機能素子に関するのもである。
[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) This invention relates to an integrated piezoelectric device in which a resonator using a piezoelectric thin film as a vibrating membrane and a semiconductor integrated circuit are integrated on the same substrate. The present invention relates to thin film functional elements.

(従来の技術) 薄膜加工で形成される圧電薄膜共振子と増幅器、フィル
タ等とを半導体基板上に一体的に形成し、VHF帯U 
HF帯のような高周波帯で使用できる超小形でワンチッ
プのモノリシックタイプ高周波回路の実現が可能である
(Prior art) A piezoelectric thin film resonator formed by thin film processing, an amplifier, a filter, etc. are integrally formed on a semiconductor substrate, and VHF band U
It is possible to realize an ultra-small, one-chip, monolithic type high-frequency circuit that can be used in a high-frequency band such as the HF band.

すでに本発明者等は、電子情報通信学会技術研究報告 
US86−71 (1987年1月30日)、特開昭6
3−138808号公報等に圧電薄膜共振子と集積回路
とを一体化したワンチップ型発振器の作製例を報告開示
している。
The inventors have already submitted a technical research report to the Institute of Electronics, Information and Communication Engineers.
US86-71 (January 30, 1987), Japanese Patent Publication No. 6
No. 3-138808 and the like disclose an example of fabricating a one-chip oscillator that integrates a piezoelectric thin film resonator and an integrated circuit.

(発明が解決しようとする課題) これらに報告開示した技術によって回路構成したワンチ
ップ発振器の試験サンプルを直流電源電圧6vで温度8
5℃の条件で連続動作の信頼性′t、験を行ったところ
、500時間経過後に発振周波数の変動や発振の停止が
生じ、1000時間経過後は10個の試験サンプル全数
が発振停止した。
(Problem to be solved by the invention) A test sample of a one-chip oscillator configured as a circuit according to the disclosed technology was tested at a DC power supply voltage of 6 V and a temperature of 8 V.
When testing the reliability of continuous operation under the condition of 5°C, the oscillation frequency fluctuated or stopped oscillating after 500 hours, and all 10 test samples stopped oscillating after 1000 hours.

この原因を究明するため詳細に圧電薄膜共振子の特性を
測定し分析検討した結果、共振損失の増加、共振周波数
の変動、特に反共振レベルが著しく劣化していた。この
現象は電気的には共振子と並列に抵抗が付加されたと等
価であり、ZnO圧電膜の絶縁抵抗が著しく低下したこ
とを意味し、このような共振子の劣化現象は直流電圧を
印加しない場合には発生しないことから、この劣化現象
は印加された直流電源の電界の影響によるものと考えら
れる。
In order to investigate the cause of this, we measured and analyzed the characteristics of the piezoelectric thin film resonator in detail, and found that the resonance loss increased, the resonance frequency fluctuated, and especially the anti-resonance level deteriorated significantly. This phenomenon is electrically equivalent to adding a resistance in parallel with the resonator, and means that the insulation resistance of the ZnO piezoelectric film has decreased significantly.Such a resonator deterioration phenomenon occurs when no DC voltage is applied. This deterioration phenomenon is considered to be due to the influence of the electric field of the applied DC power source, since it does not occur in the case of the wafer.

共振子を構成するZnO圧電膜は結晶構造が繊維状多結
晶であり、多数の結晶粒界が走っていることから、この
粒界に沿って金属原子の移動が起こり易い構造をしてお
り、このため印加された直流電圧の電界によってZnO
圧電膜を挾む上下電極の金属原子がZnO圧電膜中に拡
散し、さらに高温の状態ではより活性化されてこの拡散
が促進され、共振子の絶縁抵抗を低下させるものと考え
られる。
The ZnO piezoelectric film that makes up the resonator has a fibrous polycrystalline crystal structure, with many grain boundaries running through it, so it has a structure in which metal atoms easily move along these grain boundaries. Therefore, due to the electric field of the applied DC voltage, ZnO
It is thought that the metal atoms of the upper and lower electrodes sandwiching the piezoelectric film diffuse into the ZnO piezoelectric film, and are further activated at high temperatures to promote this diffusion, thereby lowering the insulation resistance of the resonator.

この発明は上記した問題を解決するためになされたもの
で、直流電圧による特性劣化を抑圧した集積型圧電薄膜
機能素子を提供することを目的としている。
The present invention was made to solve the above-mentioned problems, and an object of the present invention is to provide an integrated piezoelectric thin film functional element that suppresses characteristic deterioration due to DC voltage.

[発明の構成] (課題を解決するための手段) この発明は、半導体基板上に半導体集積回路と圧電薄膜
共振子とが一体的に形成された集積型圧電薄膜機能素子
において、前記半導体集積回路と前記半導体基板上の少
なくとも一部に形成されたパッシベーション膜を介して
、半導体集積回路と圧電薄膜共振子とが容量結合により
接続されていることを特徴としている。
[Structure of the Invention] (Means for Solving the Problem) The present invention provides an integrated piezoelectric thin film functional element in which a semiconductor integrated circuit and a piezoelectric thin film resonator are integrally formed on a semiconductor substrate. The semiconductor integrated circuit and the piezoelectric thin film resonator are connected by capacitive coupling via a passivation film formed on at least a portion of the semiconductor substrate.

(作用) このように圧電薄膜共振子と集積回路とをパッシベーシ
ョン膜を誘電体層として形成される結合容量により容量
結合させることにより、集積回路側よりの直流電圧を結
合容量によって分圧し、圧電薄膜共振子に加えられる直
流電圧を低くし、電極金属原子の共振子への拡散を抑え
て、圧電薄膜共振子の絶縁抵抗の低下を防止する。
(Function) By capacitively coupling the piezoelectric thin film resonator and the integrated circuit using the coupling capacitance formed using the passivation film as a dielectric layer, the DC voltage from the integrated circuit side is divided by the coupling capacitance, and the piezoelectric thin film resonator and the integrated circuit are capacitively coupled. By lowering the DC voltage applied to the resonator and suppressing the diffusion of electrode metal atoms into the resonator, a decrease in insulation resistance of the piezoelectric thin film resonator is prevented.

(実施例) 以下図面を参照しながらこの発明の一実施例を説明する
。第1図(aHb)は半導体基板上にワンチップ発振器
をこの発明を適用して構成した実施例の構造図で(a)
図は平面図、fb)図は(a)図のB−B断面図である
。同図において半導体基板1上にZnO圧電膜で構成さ
れる圧電薄膜共振子2と発振回路を構成する集積回路3
とが一体的に形成され、圧電薄膜共振子2flllの配
線パターン4a。
(Example) An example of the present invention will be described below with reference to the drawings. Figure 1 (aHb) is a structural diagram of an embodiment in which a one-chip oscillator is constructed on a semiconductor substrate by applying this invention.
The figure is a plan view, and the fb) figure is a BB sectional view of figure (a). In the figure, a piezoelectric thin film resonator 2 made of a ZnO piezoelectric film and an integrated circuit 3 forming an oscillation circuit are mounted on a semiconductor substrate 1.
are integrally formed, and the wiring pattern 4a of the piezoelectric thin film resonator 2flll.

4bと集積回路3側の配線パターン5a、 5bの相対
向する部分には接続バッド6a、 6bが設けられ、こ
のパターン面が対向している接続パッド6a、 6bを
電極とし、パターン面を保護するためのパッシベーショ
ン膜7を誘電体層として形成される結合容量Ca 、C
bを介して圧電薄膜共振子2と集積回路3とが容量結合
されている。
Connecting pads 6a, 6b are provided at opposing portions of wiring patterns 5a, 5b on the integrated circuit 3 side, and the connecting pads 6a, 6b whose pattern surfaces are facing each other are used as electrodes to protect the pattern surfaces. Coupling capacitances Ca and C formed using the passivation film 7 as a dielectric layer for
The piezoelectric thin film resonator 2 and the integrated circuit 3 are capacitively coupled via b.

なお同図において8a、 8bは電源端子と接地端子を
また9a、 9bはそれぞれ出力端子を示している。
In the figure, 8a and 8b represent a power supply terminal and a ground terminal, and 9a and 9b represent output terminals, respectively.

第2図はこの実施例のワンチップ発振器の回路図で二点
鎖線で示す部分はそれぞれ圧電薄膜共振子2の等価回路
および発振回路を構成する集積回路3の具体的な回路例
である。
FIG. 2 is a circuit diagram of the one-chip oscillator of this embodiment, and the portions indicated by two-dot chain lines are an equivalent circuit of the piezoelectric thin film resonator 2 and a specific circuit example of the integrated circuit 3 constituting the oscillation circuit, respectively.

圧電薄膜共振子2の電気的等価回路は同図に示すように
通常の水晶振動子と同様に表され、この等価回路でCO
は並列等価容量と呼ばれ、共振子が単にコンデンサとし
て働いている場合の容量であり、共振子の電極間容址に
リード線等の浮遊容量を含んだものである。Llおよび
C1はそれぞれ等個直列インダクタンス、等個直列容量
と呼ばれ、圧電薄膜共振子2が電気機械振動系として動
作するときの等価定数であり、振動モード、材料、電極
の構造寸法によって定まる定数である。なおR1は共振
子の損失を表す等個直列抵抗である。
As shown in the figure, the electrical equivalent circuit of the piezoelectric thin film resonator 2 is expressed in the same way as a normal crystal resonator, and in this equivalent circuit, CO
is called the parallel equivalent capacitance, and is the capacitance when the resonator simply functions as a capacitor, and includes stray capacitance such as lead wires in the capacitance between the electrodes of the resonator. Ll and C1 are called equal series inductance and equal series capacitance, respectively, and are equivalent constants when the piezoelectric thin film resonator 2 operates as an electromechanical vibration system, and are constants determined by the vibration mode, material, and structural dimensions of the electrodes. It is. Note that R1 is an equal series resistance representing the loss of the resonator.

集積回路3の発振回路は変形コルピッツ型の発振回路で
、同図において発振回路の増幅部を構成するトランジス
タT「はコレクタが電源端子8aを介して直流電源Eに
接続され、エミッタは抵抗R2を介し接地端子8bを通
して接地されおり、またペースにはコレクタとベース間
およびベースと接地間にそれぞれ接続されているバイア
ス抵抗R3。
The oscillation circuit of the integrated circuit 3 is a modified Colpitts type oscillation circuit, and in the figure, the collector of the transistor T" constituting the amplification section of the oscillation circuit is connected to the DC power supply E via the power supply terminal 8a, and the emitter is connected to the resistor R2. A bias resistor R3 is connected to the ground through the ground terminal 8b, and is connected to the base between the collector and the base and between the base and the ground.

R4により直流バイアスE′が与えられている。A DC bias E' is applied by R4.

エミッタと接地間には負荷容量C2、C3とが直列に接
続されてておりその接続点と接地間より出力端子9a、
 9bを通して出力が取り出される。なおコレクタと接
地間に接続されているC4は高周波バイパス用の容量で
ある。
Load capacitances C2 and C3 are connected in series between the emitter and the ground, and the output terminal 9a is connected between the connection point and the ground.
Output is taken through 9b. Note that C4 connected between the collector and ground is a capacitor for high frequency bypass.

圧電薄膜共振子2と集積回路3の発振回路とは前記した
接続パッド6a 、6bで形成される結合容量Ca 、
Cbによって容量結合され全体として発振器が構成され
ている。
The piezoelectric thin film resonator 2 and the oscillation circuit of the integrated circuit 3 have a coupling capacitance Ca formed by the connection pads 6a and 6b,
Capacitively coupled by Cb, the oscillator is constructed as a whole.

この実施例では接続バッド6a 、6bのそれぞれの寸
法を一約100μm角とし、誘電物質を兼ねるパッシベ
ーションII!7としては絶縁耐圧が圧電薄膜共振子2
を構成するZnO膜と比べて一桁以上優れた値108V
/m程度と高く信頼性のよいP−3iN膜を使用し、膜
厚は通常用いられている膜厚1μmとして結合容JiC
a 、cbを形成した。
In this embodiment, the dimensions of each of the connection pads 6a and 6b are approximately 100 μm square, and the passivation pads 6a and 6b serve as dielectric materials. As for 7, the dielectric strength is piezoelectric thin film resonator 2.
108V, which is an order of magnitude better than the ZnO film that makes up the
A P-3iN film with high reliability of about /m is used, and the film thickness is 1 μm, which is the commonly used film thickness, and the coupling capacity JiC
a, formed cb.

この結合容量Ca 、Cbの容量値は次式で算出できる
The capacitance values of the coupling capacitances Ca and Cb can be calculated using the following equation.

Ca 、 Cb =EO・εr ・S/l−・−(1)
但し C0・・・真空の誘電率   約8.9 xlo−12
F/nε「・・・P−3iNの比誘電率 約7,5S・
・・・・・パッド6abの面積 1O−8rr?t・・
・・・・P−3iNの膜厚   1μm上記の数値を(
1)式に代入して算出するとCa 、Cbは約0.7p
Fとなる。
Ca, Cb = EO・εr・S/l−・−(1)
However, C0...Dielectric constant of vacuum approximately 8.9 xlo-12
F/nε "... Relative dielectric constant of P-3iN approximately 7.5S・
...area of pad 6ab 1O-8rr? T...
...P-3iN film thickness 1μm The above value is (
1) When calculated by substituting into the formula, Ca and Cb are approximately 0.7p
It becomes F.

一方、ZnO圧電膜を使用した400MH2帯の圧電薄
膜共振子2の並列等価容量COはZnOの膜厚を2.5
μm、比誘電率を約8.8とし、電極寸法を100μm
角としてこれらの数値を上記の(1)式に代入して算出
するとCOの容量は約0.3pFとなる。
On the other hand, the parallel equivalent capacitance CO of the 400MH2 band piezoelectric thin film resonator 2 using the ZnO piezoelectric film is 2.5
μm, the relative permittivity is approximately 8.8, and the electrode size is 100 μm.
When calculated by substituting these values into equation (1) above, the capacitance of CO is approximately 0.3 pF.

結合容量ca 、cbと並列等価容量COの容量値より
、直流バイアスE′によって圧電薄膜共振子2に加えら
れる電位EOは、通常CGが01に比べて十分に大きい
ので次式で求められる。
From the capacitance values of the coupling capacitances ca and cb and the parallel equivalent capacitance CO, the potential EO applied to the piezoelectric thin film resonator 2 by the DC bias E' is usually determined by the following equation since CG is sufficiently larger than 01.

EO=Ct /Co ・E′・・・・・・(2)但しC
1はca 、cbおよびCOの合成容量であり、まなこ
の合成容量Ctは次式で求められる。
EO=Ct/Co ・E′・・・・・・(2) However, C
1 is the composite capacitance of ca, cb, and CO, and Manako's composite capacitance Ct is determined by the following equation.

Ct =Ca −Cb −Co / Ca −Cb +Ca = Co +Cb −C0この
式に(1)式で求めたCa 、Cb 、Coの容量値を
代入すると合成容量C1は約0.169 Fとなり、さ
らにこの合成容量Ctの容量値を(2)式に代入すると
、 EO=0.1610.3 x E ’ =0.53E 
′となり、圧電薄膜共振子2に加えられる電位EOは直
流バイアスE′の約172に低下させることができる。
Ct = Ca - Cb - Co / Ca - Cb + Ca = Co + Cb - C0 By substituting the capacitance values of Ca, Cb, and Co obtained by equation (1) into this equation, the combined capacitance C1 becomes approximately 0.169 F, and further Substituting the capacitance value of this composite capacitance Ct into equation (2), EO = 0.1610.3 x E' = 0.53E
', and the potential EO applied to the piezoelectric thin film resonator 2 can be lowered to about 172 of the DC bias E'.

この実施例のワンチップ発振器を高温連続動作試験行っ
たところ、1000時間経過しても安定した発振特性が
得られ、信頼性が向上したことが実証された。
When the one-chip oscillator of this example was subjected to a high-temperature continuous operation test, stable oscillation characteristics were obtained even after 1000 hours, demonstrating that reliability was improved.

この実施例で例えば圧電薄膜共振子2と集積回路3の接
地側のみは直接接続するような回路構成をとることもで
きる。
In this embodiment, for example, a circuit configuration may be adopted in which only the ground sides of the piezoelectric thin film resonator 2 and the integrated circuit 3 are directly connected.

なお、この発明は上記実施例に限定されるものでなく要
旨を変更しない範囲で種々変形して実施できる。
It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications without changing the gist.

例えばこの発明の技術を利用して圧電薄膜共振子の下部
電極に対して複数の上部電極を対向して設け、各電極対
向部間を弾性的に結合させたフィルタや、さらには共通
の下部電極に対して複数の上部電極を直交するように対
向させ、各電極対向部間を弾性的結合が無視できる程度
離すか、または各電極対向部間に溝や吸音手段を設ける
ことによって独立した複数の共振子が設けられた多素子
型共振子を構成することができる。
For example, by utilizing the technology of the present invention, a filter in which a plurality of upper electrodes are provided opposite to the lower electrode of a piezoelectric thin film resonator, and each electrode opposing portion is elastically coupled, or a common lower electrode A plurality of upper electrodes may be arranged perpendicularly to each other, and the opposing parts of each electrode may be spaced apart to the extent that elastic coupling can be ignored, or grooves or sound absorbing means may be provided between each opposing part of the electrodes. A multi-element resonator including resonators can be configured.

また圧電薄膜共振子の材質はznOに限らず、AI N
、Ta205 、Pb Ti 03等のC軸配向膜のも
のでも実施できる。
Furthermore, the material of the piezoelectric thin film resonator is not limited to znO, but also AI N
, Ta205, PbTi03, etc. can also be used.

[発明の効果] この発明によれば、圧電薄膜共振子と集積回路とを容量
結合させることにより、圧電薄膜共振子に加−おる直流
電位を低く抑えることができるので直流電位による絶縁
抵抗低下に基ずく共振子の特性劣化を防止でき、高い信
頼性を得ることができる。
[Effects of the Invention] According to the present invention, by capacitively coupling the piezoelectric thin film resonator and the integrated circuit, the direct current potential applied to the piezoelectric thin film resonator can be suppressed to a low level, thereby preventing a decrease in insulation resistance due to the direct current potential. Deterioration of the characteristics of the underlying resonator can be prevented and high reliability can be obtained.

別の効果として結合容量を設けることにより、仮に圧電
薄膜共振子の絶縁破壊が生じても、この結合容量により
絶縁が維持されて池の集積回路の破損を防止できる。
Another effect is that by providing a coupling capacitance, even if dielectric breakdown occurs in the piezoelectric thin film resonator, the coupling capacitance maintains insulation and prevents damage to the integrated circuit.

また直流をカットするための結合容量はパッシベーショ
ン膜をそのまま用いて形成でき、特別の工程や外付のコ
ンデンサ、抵抗が不要であるので、コストを低減させる
ことができると共に、回路素子のモノリシック化が一層
容易になるという効果もある。
In addition, the coupling capacitance for cutting DC can be formed using the passivation film as is, and there is no need for special processes or external capacitors or resistors, so it is possible to reduce costs and make the circuit elements monolithic. It also has the effect of making it easier.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(aHb)はこの発明による集積型圧電薄膜機能
素子の構−造を示す平面図と断面図、第2図は同実施例
の回路図である。 1・・・・・・半導体基板  2・・・・・・圧電薄膜
共振子3・・・・・・集積回路 4a、 4b、 5a、 5b・・・・・・配線バタン
6a、6b・・・・・・接続パッド 7・・・・・・パッシベーション膜 8a・・・・・・電源端子   8b・・・・・・接地
端子9a、 9b・・・・・・出力端子 Ca、Cb・・・・・・結合容量 代理人  弁理士 小 宮 幸 W士 第1図 第2図
FIG. 1 (aHb) is a plan view and a sectional view showing the structure of an integrated piezoelectric thin film functional element according to the present invention, and FIG. 2 is a circuit diagram of the same embodiment. 1...Semiconductor substrate 2...Piezoelectric thin film resonator 3...Integrated circuit 4a, 4b, 5a, 5b...Wiring button 6a, 6b... ... Connection pad 7 ... Passivation film 8a ... Power supply terminal 8b ... Ground terminal 9a, 9b ... Output terminal Ca, Cb ... ...Coupling Capacity Agent Patent Attorney Yuki Komiya Figure 1 Figure 2

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板上に半導体集積回路と圧電薄膜共振子
とが一体的に形成された集積型圧電薄膜機能素子におい
て、前記半導体集積回路と前記半導体基板上の少なくと
も一部に形成されたパッシベーション膜を介して、前記
半導体集積回路と前記圧電薄膜共振子とが容量結合によ
り接続されていることを特徴とする集積型圧電薄膜機能
素子。
(1) In an integrated piezoelectric thin film functional element in which a semiconductor integrated circuit and a piezoelectric thin film resonator are integrally formed on a semiconductor substrate, a passivation film is formed on at least a portion of the semiconductor integrated circuit and the semiconductor substrate. An integrated piezoelectric thin film functional element, wherein the semiconductor integrated circuit and the piezoelectric thin film resonator are connected through capacitive coupling.
(2)半導体基板上に圧電薄膜共振子と集積回路とを一
体的に形成すると共に、この圧電薄膜共振子と集積回路
とはパッシベーション膜を介して対向する接続パッドお
よび前記パッシベーション膜を誘電体層として形成され
る結合容量により容量結合されることを特徴とする集積
型圧電薄膜機能素子。
(2) A piezoelectric thin film resonator and an integrated circuit are integrally formed on a semiconductor substrate, and the piezoelectric thin film resonator and the integrated circuit are connected to connection pads that face each other via a passivation film, and the passivation film is formed on a dielectric layer. An integrated piezoelectric thin film functional element characterized in that it is capacitively coupled by a coupling capacitance formed as an integrated piezoelectric thin film functional element.
JP11836689A 1989-05-11 1989-05-11 Integrated type piezoelectric thin film functional element Pending JPH02298109A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11836689A JPH02298109A (en) 1989-05-11 1989-05-11 Integrated type piezoelectric thin film functional element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11836689A JPH02298109A (en) 1989-05-11 1989-05-11 Integrated type piezoelectric thin film functional element

Publications (1)

Publication Number Publication Date
JPH02298109A true JPH02298109A (en) 1990-12-10

Family

ID=14734929

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11836689A Pending JPH02298109A (en) 1989-05-11 1989-05-11 Integrated type piezoelectric thin film functional element

Country Status (1)

Country Link
JP (1) JPH02298109A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5212115A (en) * 1991-03-04 1993-05-18 Motorola, Inc. Method for microelectronic device packaging employing capacitively coupled connections

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5212115A (en) * 1991-03-04 1993-05-18 Motorola, Inc. Method for microelectronic device packaging employing capacitively coupled connections

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