JPH02292796A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor storage device whose access time is shortened by separating a storage element array to plural groups by providing a switching element at a bit line. CONSTITUTION:In a storage device comprised by connecting plural semiconductor storage elements to a common bit line in array shape and parallel relation, and also, connecting the bit line to a sense amplifier, the storage element array 1 can be separated to the plural groups by providing the switching element at the bit line. At such the case, when it is not required to make access to the storage element in the group on one side, the bit line length of a memory array can be shortened by setting the switching element separating the group at an off state with an appropriate signal, which reduces the capacity held by the bit line. Thereby, the access time can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which a bit line is provided with a MOS transistor that divides the bit line.

[Prior Art] A memory device in which a plurality of semiconductor memory elements are connected in an array has conventionally been constructed of semiconductor elements, and a plurality of memory cells for storing data are arranged in a lattice shape, as shown in FIG. a memory array 1 arranged in the memory cell, an output circuit 2 for sending data to be stored in the memory cell or amplifying the stored data read from the memory cell, and an address circuit for sending an address signal for selecting the memory cell. 3
, and an address decoder circuit 4 that decodes the address signal.
It is composed of.

For example, in FIG. 3, memory array 1 has 4 rows and 2 columns, totaling 8
memory cells 50 are arranged.

Of course, the arrangement is not limited to this, and more memory cells may be arranged. One word line (indicated by WL in the figure) 60a to 60d extends from address decoder circuit 4 in the row direction of memory array l. For example, in the memory cell 51a, a MOS transistor 5 that reads and writes data to the memory cell
and 6 are connected to the word line 60a.

The same applies to memory cells 52a to 54a.

Also, memory cells 51a, 52a, ... 54a (representatively indicated by 50) arranged in the same column of the memory array l
is connected to a pair of bit lines (denoted as BL in the figure) and an inverted bit line (denoted as BL in the figure) connected to the input/output circuit 2. For example, memory cell 51
In a, the source of MOS transistor 5 is connected to bit line 65a, and the drain of MOS transistor 6 is connected to inverted bit line 65b. Memory cells 51 to 54b in other columns are similarly configured. Each bit line BL, BL is connected to a sense amplifier (not shown), respectively.

Thus, in the conventional memory array I, a large number of memory cells are connected in parallel to a common bit line and an inverted bit line extending from the human output circuit 2.

In this example, since the memory cells are arranged in four rows, the address circuit 3 is provided with input terminals 7 and 8 to which 2-bit data is supplied in parallel;
are connected to address signal lines 11a and Ilb via series-connected inverters 9 and 10, respectively, and
Input terminals 7 and 8 are connected to address signal lines 12a and +2b via inverter 9, respectively.

In the address decoder circuit 4, the NAND circuit 13a
or +3d are arranged in parallel, for example, NAND circuit 1
Address signal lines 12a and +2b are connected to the input side of NAND circuit I3b, and address signal lines 11a and 12b are connected to the input side of NAND circuit I3b. The output sides of each of the NAND circuits 13a to 13d are connected to one inverter 14a to 14d, and the output sides of the inverters 14a to 14d are connected to word lines 60a to 60d, respectively.

In the semiconductor memory device configured as described above, when a digital signal is supplied to the input terminals 7 and 8, this digital signal is decoded by the address decoder circuit 4, and the memory cell specified by the digital signal is A signal is sent out from one of the inverters 14a to 14d via the forward line. On the other hand, a signal is supplied from the human output circuit 2 to the bit line to which the memory cell to be selected is connected. By selecting word lines and bit lines in this way, the...
One memory cell is selected, and data is written or read.

[Problems to be Solved by the Invention] As described above, in order to access any of the memory cells 50, the address decoder circuit 4 sends out the decoded address signal, and the input/output circuit 2 sends the decoded address signal to the bit lines 65a, 66a. , and inverted bit lines 65b, 66
It is necessary to supply a signal to b.

Address signal lines 1la, ll of address decoder circuit 4
b1 12a and 12b and bit lines 65a, 65b
, 66a and 66b are almost the same,
Half the number of NAND circuits 13a and the like of all the memory cells 50 are added to the address signal line 11a, etc.
The capacity of the ND circuit 13a etc. is larger than that of the inverter 1.
In order to drive 4a and the like, a large capacitance RAp is used.

On the other hand, MOS transistors 5, etc. provided in each memory cell are added to the bit line 65a, etc., but these MOS transistors 5, etc. are of small capacity in order to minimize the size of the memory cell 50. .

Therefore, the capacitance added to the address signal line 11a etc. is larger than the capacitance added to the bit line 658 etc.

This means that, for example, when accessing the memory cell 51a to write or read data, and when accessing the memory cell 54a, the above-mentioned additional capacitance causes the transmission of signals sent to the memory cell 50. The times are different, resulting in a phenomenon in which the time required to access memory cell 54a is longer than the time required to access memory cell 51a. Therefore, the access time of the semiconductor memory device as a whole is the access time of the memory cell that requires the longest access time.The present invention reduces the access time of the semiconductor memory device as a whole by shortening the access time to the memory cells. The purpose is to provide a semiconductor memory device.

[Means for Solving the Problems] The present invention provides a memory device in which a plurality of semiconductor memory elements are connected in parallel in an array to a common bit line, and the bit line is connected to a sense amplifier. The memory element array is characterized in that a switch element is provided in the memory element array to allow the storage element array to be separated into a plurality of groups.

[Function] In the above configuration, when there is no need to access the memory elements of one group, the switch elements dividing that group are turned off by an appropriate signal, and the bit line length of the memory array is shortened. Bitline's debt capacity will be reduced. This allows access time to be shortened.

[Embodiment] In FIG. 1 showing an embodiment of the semiconductor memory device of the present invention, the same components as in FIG. 3 are denoted by the same reference numerals, and the explanation thereof will be omitted.

The semiconductor memory device of the present invention also includes a memory array output circuit 2, an address circuit 3, and an address decoder circuit 4, like the conventional semiconductor memory device.

In the memory array l of this embodiment, for example, a total of eight memory cells 50 are arranged in eight rows and one column.

A source train of an N-channel MOS (hereinafter referred to as NMOS) MOS transistor 35 is connected in series to the bit line 30 between the source of the MOSMOS transistor 5 provided in the memory cell 54 and the source of the MOSMOS transistor 5 provided in the memory cell 55. connected at
Similarly, the bit line 3 between the drain of the MOS transistor 6 provided in the memory cell 54 and the drain of the MOS transistor 6 provided in the memory cell 55 is NMOS.
The source and drain of the MOS transistor 36 are connected in series.

The address circuit 3 is provided with three input terminals 7, 8, and 20 to which a 3-bit digital signal is supplied in parallel in order to select eight memory cells 50.

Similar to the address circuit 3 shown in the conventional example, the input terminals 7,
8 and 20 are connected to address signal lines via inverters 9 and 10. For example, input terminal 7 is connected to inverter 9
is connected to the address signal line 12a through the inverter 9 and the address signal line 12a connected in series.
1a. Input terminal 8 is also connected to address signal line +2b via inverter 9, and to address signal line zb via inverters 9 and 10 connected in series. Further, the input terminal 20 is connected to an address signal line 21a via an inverter 9, and is connected to an address signal line 22a via an inverter 9 and IO connected in series.

Predetermined three address signal lines selected from the above-mentioned six address signal lines are connected to the human power side of NAND circuits 13a to tab provided in the address decoder circuit 4 according to each NAND circuit. For example, NAND
The circuit 13a includes address signal lines 12a, 12b and 21.
address signal lines 11a1zb and 21a are connected to the NAND circuit 13d. These NAND circuits 13a to tah are connected to respective word lines 60a to 60h of memory array l via inverters 14a to 14h, respectively.

Further, the address signal line 22a is connected to the NMOSM connected to the bit lines 30 and 3l via an inverter 37.
OS} is connected to the gates of transistors 35 and 36.

The operation of the semiconductor memory device of this embodiment configured as described above will be described below.

The input terminal 7 of the address circuit 3 is supplied with the least significant bit, the input terminal 8 is supplied with the middle bit, and the input terminal 2
It is assumed that 0 is supplied with the most significant bit. For example 0
When a signal of 00 is supplied, the address signal line l2a - 1 2b % 2 1a is supplied to the NAND circuit 13a.
Since the word line 6 is connected, only the NAND circuit 13a sends out a low (L) level signal.
A high (1-1) level signal is supplied from the inverter 14a only to 0a. Therefore, only the memory cell 51 is in a state where data can be read.

Similarly, the NA is determined by the signal level supplied to the address signal lines connected to the NAND circuits 13a to 13h.
001 due to the logic operation of the ND circuits 13a to +3h.
When a signal of 011 is supplied to the input terminals 7, 8, and 20, only the memory cell 52 (not shown) is supplied, when a signal of 011 is supplied, only the memory cell 54 is supplied, and when a signal of 100 is supplied, the memory cell 55 is supplied. When the signal 111 is supplied to only the memory cells 58, only the memory cells 58 are in a state where the data stored therein can be read.

On the other hand, as described above, when the most significant bit data supplied to the input terminal 20 is 0, that is, when the memory cell 51
When any one of MOS transistors 35 and 54 is selected, the inverter 3 connected to the gates of MOS transistors 35 and 36
7 sends out an H level signal, the MOS transistors 35 and 36 are turned on. Therefore, the bit lines 30 and 3l are not divided, the input/output circuit 2 and the memory cells 51 to 54 are connected, and data can be read from these memory cells.

Further, when the data of the most significant bit supplied to the input terminal 20 is 1, that is, when one of the memory cells 55 to 58 is selected, an L level signal is supplied to the gates of the MOS transistors 35 and 36. As a result, MOS transistors 35 and 36 are turned off.

Therefore, bit lines 30 and 3l are disconnected between memory cells 54 and 55, and memory cell 5
Only the terminals 5 to 58 are connected to the human output circuit 2.

According to the semiconductor memory device of this embodiment, when data is read from the memory cells 54 to 58, the lengths of the bit lines 30 and 3l are halved by turning off the MOSMOS transistors 35 and 36. The additional capacitance of the bit lines 30 and 3l can be avoided. For example, as shown in FIG. 2, in the case of a conventional memory, the time required to access a memory cell increases sequentially from the time TI required to access a memory cell connected to word line 60a. , the time required to access the memory cell connected to the word line 60h is time T3. However, in the case of the semiconductor memory device of this embodiment, the time required to access the memory cell connected to the word line 60d from the word line 60a is the same as that of a conventional memory; Since the bit line is disconnected when accessing a memory cell, the time required to access a memory cell connected to word line 60e is shorter than word line 60e.
The time TI is the same as in case a, and the time required to access the memory cell connected to the word line 60h is the same time T2 as in the case of the word line 60d. In this way, the time required to read data can be shortened compared to the case where bit lines are not separated, and the access time of the semiconductor memory device as a whole can be shortened. Further, the on/off operations of the MOS transistors 35 and 36 can be automatically controlled by an address signal specifying a memory cell from which stored data is to be read.

In the above embodiment, the memory array is provided with eight memory cells in only one column, but the present invention is not limited to this, and the memory cells may be arranged in a lattice pattern.

Further, in the above embodiment, MOS transistors for separating the bit lines are provided at positions that equally divide the length of the bit lines, but the present invention is not limited to this. Further, a plurality of separation points may be provided in a pair of bit lines.

[Effects of the Invention] As detailed above, according to the present invention, signal transmission to the bit line to which the semiconductor memory element to which stored data is not read is connected is cut off, and the additional capacitance of the bit line is reduced. Therefore, the access time of the semiconductor memory device can be shortened.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block diagram showing a configuration example of the semiconductor memory device of the present invention, FIG. 2 is a graph showing the access time of the semiconductor memory device of the present invention, and FIG. 3 is a graph of a conventional semiconductor memory device. FIG. 2 is a block diagram showing the configuration of a storage device. ! ...Memory array, 2...Human output circuit, 3...
Address circuit, 4...Address decoder circuit, 35 and 36...MOSI-transistor, 50...Memory cell. Figure 2

Claims (1)

[Claims] (1) In a memory device in which a plurality of semiconductor memory elements are connected in parallel in an array to a common bit line and the bit line is connected to a sense amplifier, a switch element is provided on the bit line to connect the memory element array. A semiconductor memory device characterized by being separable into a plurality of groups.