JPH02281367A - Sate reproducing method - Google Patents

Sate reproducing method

Info

Publication number
JPH02281367A
JPH02281367A JP10408689A JP10408689A JPH02281367A JP H02281367 A JPH02281367 A JP H02281367A JP 10408689 A JP10408689 A JP 10408689A JP 10408689 A JP10408689 A JP 10408689A JP H02281367 A JPH02281367 A JP H02281367A
Authority
JP
Japan
Prior art keywords
cpu
sub
main cpu
sub cpu
restart
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10408689A
Other languages
Japanese (ja)
Inventor
Shigeo Izumi
泉 重夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Honda Motor Co Ltd
Alpine Electronics Inc
Original Assignee
Honda Motor Co Ltd
Alpine Electronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honda Motor Co Ltd, Alpine Electronics Inc filed Critical Honda Motor Co Ltd
Priority to JP10408689A priority Critical patent/JPH02281367A/en
Publication of JPH02281367A publication Critical patent/JPH02281367A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To restore a normal state with an inexpensive constitution by transferring data indicating the operation state from a main CPU to a sub-CPU at intervals of a prescribed time and reproducing the normal state before restart based on the data by the sub-CPU at the time of restart with respect to the state reproducing method for restart after runaway of a microcomputer. CONSTITUTION:A system consists of a main CPU 1 which performs a prescribed processing by the request from a sub-CPU 2, the sub-CPU 2 which detects a key input to transfer key data to the CPU 1 and receives the command sent from the CPU 1 to control the display, a serial transmission line 3, a key part 4, an LED 5 on which the operation mode is displayed, an encoder 6, a display driver 7, and a watchdog timer 8. In this constitution, a pulse PS is outputted to the timer 8 at intervals of a prescribed period when the CPU 2 is normally operated, but the pulse PS is not outputted and a reset signal RSS is outputted to initialize the CPU 2 when the CPU 2 runs away.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は状態再現方法に係わり、特にマイコン暴走後の
再起動時における状態再現方法に関する。
DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a state reproduction method, and particularly to a state reproduction method at the time of restarting a microcomputer after a runaway.

〈従来技術〉 メインの処理を行うCPU (メインCPU)と、メイ
ンCPUからの命令により所定の動作を行うサブCPU
を有し、これら両CPU間でシリアルI10インタフェ
ースに基づいてデータ授受し、全体として所望の処理を
実行するシステムがある。
<Prior art> A CPU that performs main processing (main CPU) and a sub CPU that performs predetermined operations based on instructions from the main CPU
There is a system in which data is exchanged between these two CPUs based on a serial I10 interface, and desired processing is executed as a whole.

かかるシステムにおいて、例えばサブCPUはキー人力
の検出を行ってメインCPUにキー人力を知らせ、メイ
ンCPUはキー人力に基づいて所定の処理を実行すると
共に、サブCPUに所定のコマンドを送信し、サブCP
Uは該コマンドに基づいて表示素子のオン/オフ制御等
を行ってメインCPUの動作状態を表示する。
In such a system, for example, the sub CPU detects key human power and informs the main CPU of the key human power, and the main CPU executes a predetermined process based on the key human power, and also sends a predetermined command to the sub CPU. C.P.
Based on the command, U performs on/off control of the display element, etc., and displays the operating state of the main CPU.

ところで、サブCPUが何らかの外乱を受けて暴走して
しまうことがある。かかる暴走がウォッチドッグタイマ
ー等により検出されると、サブCPUはリセットされ、
プログラムの最初から再起動する。そして、この際サブ
CPU側の各出力端子はイニシャル値に設定されてしま
い、再起動前の正常な状態を再現(動作状態の表示等)
することができない0例えば、メインCPUが所定のモ
ードに応じた処理を行っている場合、サブCPU側では
該モードに応じた表示が行われるが、暴走検出後の再起
動に際してイニシャライズされるため該モード表示を行
うことができない。
By the way, the sub CPU may run out of control due to some kind of disturbance. When such runaway is detected by a watchdog timer etc., the sub CPU is reset,
Restart the program from the beginning. At this time, each output terminal on the sub CPU side is set to the initial value, reproducing the normal state before restart (displaying the operating state, etc.)
For example, if the main CPU is performing processing according to a predetermined mode, the sub CPU side will display a display according to that mode, but since it will be initialized when restarting after detecting a runaway, Unable to display mode.

このため、従来はサブCPU側に不揮発性メモリを設け
、該不揮発性メモリに現動作状態を記憶させておき(バ
ックアップ)、暴走検出等によりサブCPUが再起動す
る時に該不揮発性メモリの記憶内容を参照して再起動前
の状態を再現し、これにより再起動後もメインCPUの
動作状態とサブCPU側の状態(例えば表示状態)を一
致するようにしている。
For this reason, conventionally, a non-volatile memory is provided on the sub-CPU side, the current operating state is stored in the non-volatile memory (backup), and when the sub-CPU is restarted due to runaway detection, etc., the storage contents of the non-volatile memory are The state before the restart is reproduced by referring to , so that the operating state of the main CPU and the state (for example, display state) on the sub CPU side are made to match even after the restart.

〈発明が解決しようとする課題〉 しかし、かかる従来方式では不揮発性メモリと現状態を
不揮発性メモリにバックアップするための処理が必要で
あり、構成が複雑、高価となると共に、暴走検出迄の間
に不揮発性メモリの内容が外乱の影響を受けて変化し、
メインCPUとサブCPU間に矛盾が生じるという問題
がある。
<Problems to be Solved by the Invention> However, this conventional method requires a non-volatile memory and processing for backing up the current state to the non-volatile memory, making the configuration complex and expensive, and the time required until runaway detection is The contents of non-volatile memory change under the influence of external disturbances,
There is a problem that a contradiction occurs between the main CPU and the sub CPU.

以上から本発明の目的は、不揮発性メモリを設けなくて
も再起動前の状態を正確に再現できる状態再現方法を提
供することである。
From the above, it is an object of the present invention to provide a state reproduction method that can accurately reproduce the state before rebooting without providing a nonvolatile memory.

く課題を解決するための手段〉 上記課題は本発明において、メインCPUよす所定時間
ごとに現動作状態を示すデータをサブCPU側に転送す
る手段と、再起動時においてメインCPUから送出され
てくる該データに基づいてサブCPUにおいて再起動前
の正常な状態を再現する手段により達成される。
Means for Solving the Problems> The above problems are solved in the present invention by means of transmitting data indicating the current operating state from the main CPU to the sub CPU at predetermined intervals, and by means of transmitting data from the main CPU to the sub CPU at predetermined intervals. This is achieved by means of reproducing the normal state before restart in the sub CPU based on the data received.

く作用〉 メインCPUはキー操作等により処理の動作モードが変
化する時サブCPU側に所定のデータを送出し、サブC
PUは該データに基づいてモード表示等の制御を行う、
また、メインCPUは所定時間ごとに現動作状態を示す
コマンドをサブCPU側に転送し、これによりサブCP
Uは暴走検出後等の再起動時において、メインCPUか
ら送出されてくる該コマンドに基づいて再起動前の正常
な状態(モード表示等)を再現する。
Function> When the processing operation mode changes due to key operation, etc., the main CPU sends predetermined data to the sub CPU side,
The PU controls mode display etc. based on the data.
In addition, the main CPU transfers a command indicating the current operating state to the sub CPU at predetermined intervals, and this causes the sub CPU to
When the U is restarted after detection of runaway, etc., it reproduces the normal state (mode display, etc.) before the restart based on the command sent from the main CPU.

〈実施例〉 第1図は本発明を適用できるシステムのブロック図であ
り、1はサブCPU側からの栗求により所定の処理を行
うメインCPU、2はキー人力を検出してキーデータを
メインCPUに転送し、かつメインCPUから送られて
くるコマンドを受信して表示制御等を行うサブCPU、
3はシリアル伝送ライン、4はキ一部、5は動作モード
その他の状態を表示するLED (発光ダイオード)等
を備えた表示部、6は押圧されたキーに応じたコードを
出力するエンコーダ、7は表示ドライバ、8はウォッチ
ドッグタイマーである。
<Embodiment> Fig. 1 is a block diagram of a system to which the present invention can be applied, in which 1 is a main CPU that performs predetermined processing based on requests from the sub-CPU side, and 2 is a main CPU that detects key human power and transfers key data to the main CPU. a sub-CPU that transfers commands to the CPU and receives commands sent from the main CPU to control display, etc.;
3 is a serial transmission line, 4 is a key part, 5 is a display unit equipped with an LED (light emitting diode), etc. that displays the operation mode and other statuses, 6 is an encoder that outputs a code according to the pressed key, 7 is a display driver, and 8 is a watchdog timer.

メインメモリlにおいて、11はタイマー 12はメイ
ンCPUの最新の動作状態等を記憶するメモリであり、
自動車ナビゲーションシステムの場合には(1)現動作
状態、(2)現表示縮尺レベル。
In the main memory l, 11 is a timer, 12 is a memory that stores the latest operating status of the main CPU, etc.
In the case of an automobile navigation system, (1) the current operating state, (2) the current display scale level.

(3)地図を表示するCRTの電源オン/オフ状態等が
記憶される。尚、動作状態としては、自動車の現在位置
表示モード、目的地までのルート設定モード、地図検索
中モード当がある。メインCPU1は最新の動作状態等
をメモリ12に記憶すると共に、所定時間毎に該状態を
示すコマンド(データ)をサブCPtJ2に転送する。
(3) The power on/off status of the CRT that displays the map, etc. is stored. The operating states include a current vehicle position display mode, a route setting mode to a destination, and a map search mode. The main CPU 1 stores the latest operating status etc. in the memory 12, and transfers commands (data) indicating the status to the sub CPtJ2 at predetermined intervals.

サブCPUの2の暴走はウォッチドッグタイマー8によ
り検出される。すなわち、サブCPU2は正常動作時に
は所定周期でウォッチドッグタイマー8にパルスPSを
出力する。このためウォッチドッグタイマー内蔵のクロ
ック計数用カウンタ(図示せず)の計数値はその都度リ
セットされてオーバフローパルス(リセット信号R85
)は出力されない、しかし、サブCPU2が暴走すると
パルスPSを出力できず、このためカウンタからオーバ
フローパルスすなわちリセット信号R5Sが発生して暴
走が検出される。尚、リセット信号R8SによりサブC
PU2はイニシャライズされる。
Runaway of sub CPU 2 is detected by watchdog timer 8. That is, during normal operation, the sub CPU 2 outputs a pulse PS to the watchdog timer 8 at a predetermined period. For this reason, the count value of a clock counting counter (not shown) with a built-in watchdog timer is reset each time an overflow pulse (reset signal R85
) is not output. However, if the sub CPU 2 goes out of control, the pulse PS cannot be output, and therefore an overflow pulse, that is, a reset signal R5S is generated from the counter, and the runaway is detected. Furthermore, the sub-C is activated by the reset signal R8S.
PU2 is initialized.

第2図は本発明の処理を示すタイムチャートであり、サ
ブCPU2が暴走して時刻tiにおいてパルスPSが発
生しなくなると、ウォッチドッグタイマー8から時刻t
3においてリセット併号R85(ローレベル)が発生す
る。これにより、サブCPU2はイニシャライズされ、
以後プログラムの先頭から処理を繰り返すが、時刻t3
においてメインCPUIから送出されてくる動作状態等
を示すコマンド(シリアルI10データ)に基づいて状
態表示等のオン/オフ制御を行う。
FIG. 2 is a time chart showing the processing of the present invention. When the sub CPU 2 goes out of control and the pulse PS is no longer generated at time ti, the watchdog timer 8 changes the pulse PS to time t.
3, a reset signal R85 (low level) is generated. As a result, sub CPU2 is initialized,
Thereafter, the process is repeated from the beginning of the program, but at time t3
On/off control such as status display is performed based on commands (serial I10 data) indicating operating status etc. sent from the main CPUI.

第3図はメインCPUの処理の流れ図である。FIG. 3 is a flowchart of the processing of the main CPU.

メインCPUIはキーデータの入力があったか監視して
おり(ステップ101)、キー操作が行われてサブCP
U2から該キーに応じたコードが送られてくると、該キ
ーコードに応じた処理を開始すると共に所定のコマンド
をサブCPU2に送信する(ステップ102)、尚、コ
マンドとしては、動作状態表示用のコマンド、キーコー
ド受領を確認させるブザー音発生用コマンド等がある。
The main CPU monitors whether key data has been input (step 101), and when a key operation is performed, the sub CPU
When a code corresponding to the key is sent from U2, processing according to the key code is started and a predetermined command is sent to the sub CPU 2 (step 102). command, and a command to generate a buzzer sound to confirm receipt of the key code.

ついで、メインCPUIはメモリ12に現動作状態を記
憶あるいは更新すると共に、処理を継続する(ステップ
103,104)。
Next, the main CPUI stores or updates the current operating state in the memory 12 and continues processing (steps 103 and 104).

そして、かかる処理と並行して、所定時間経過したか監
視しくステップ1o5)、「NO」であればステップ1
01以降の処理を繰返し、所定時間経過していればメモ
リ12に記憶しである最新の動作状態を示すコマンドを
サブCPU2に転送しくステップ106)、ステップ1
01以降の処理を繰り返す、尚、ステップ101でキー
データ入力がない場合にはステップ104に飛び、最新
のキー人力データに応じた処理を続行する。
In parallel with this process, it is monitored whether a predetermined period of time has elapsed (step 1o5), and if "NO", step 1
01 and subsequent steps are repeated, and if a predetermined period of time has elapsed, a command indicating the latest operating state stored in the memory 12 is transferred to the sub CPU 2 (Step 106), Step 1
The process from step 01 onward is repeated. If no key data is input in step 101, the process jumps to step 104 and continues the process according to the latest key manual data.

以後、上記処理が繰り返され、所定時間毎に最新の動作
状態がメインCPUIからサブCPU2に転送される。
Thereafter, the above process is repeated, and the latest operating state is transferred from the main CPUI to the sub CPU 2 at predetermined intervals.

そして、かかる状態においてサブCPU2が暴走して時
刻t工(第2図参照)においてパルスPSが発生しなく
なると、ウォッチドッグタイマー8から時刻t2におい
てリセット信号R8S (ローレベル)が発生し、サブ
CPU2はイニシャライズされる。
In such a state, when the sub CPU 2 goes out of control and the pulse PS is no longer generated at time t (see FIG. 2), a reset signal R8S (low level) is generated from the watchdog timer 8 at time t2, and the sub CPU 2 is initialized.

これにより、サブCPU2は自分のプログラムの先頭か
ら処理を繰り返しく再起動)、暴走が停止していれば第
2図の時刻1.において(第3図のステップ106にお
いて)、メインCPUIから転送されてくる動作状態を
示すコマンドに基づいて各種表示器のオン/オフ制御等
を行い、メインCPUとサブCPUの状態を一致させる
As a result, the sub CPU 2 restarts (repeating the process from the beginning of its own program), and if the runaway has stopped, the time 1. in FIG. 2 is reached. At step 106 in FIG. 3, on/off control of various displays is performed based on the command indicating the operating state transferred from the main CPUI, and the states of the main CPU and sub CPU are made to match.

〈発明の効果〉 以上本発明によれば、メインCPUより所定時間ごとに
動作状態を示すデータをサブCPU側に転送し、再起動
時においてメインCPUから送出されてくる該データに
基づいてサブCPUにおいて再起動前の正常な状態を再
現するするように構成したから、不揮発性メモリを設け
てバックアップ処理しなくてもよく、従って安価で、か
つ簡単な構成で再起動前の状態を再現できる。
<Effects of the Invention> According to the present invention, data indicating the operating state is transferred from the main CPU to the sub-CPU at predetermined intervals, and upon restart, the sub-CPU is transferred based on the data sent from the main CPU. Since the system is configured to reproduce the normal state before restart, there is no need to provide a non-volatile memory for backup processing, and therefore the state before restart can be reproduced with an inexpensive and simple configuration.

又、本発明によればメインCPUから動作状態を受信す
るようにしているからメインCPUとサブCPUの状態
を正確に一致させることができる。
Further, according to the present invention, since the operating state is received from the main CPU, the states of the main CPU and the sub-CPU can be accurately matched.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明を実現するシステムのブロック図、 第2図は本発明のタイムチャート、 第3図は本発明の処理の流れ図である。 1・・メインCPU 2・・サブCPU 4・・キ一部 5・・表示部 8・・ウォッチドッグタイマー 11・・タイマー 12・・状態記憶用メモリ FIG. 1 is a block diagram of a system that realizes the present invention. Figure 2 is a time chart of the present invention; FIG. 3 is a flowchart of the process of the present invention. 1. Main CPU 2...Sub CPU 4.Ki part 5.Display section 8.Watchdog timer 11...Timer 12...Memory for state storage

Claims (1)

【特許請求の範囲】  メインCPUとサブCPUを備えたシステムの状態再
現方法において、 メインCPUは、所定時間ごとに現動作状態を示すデー
タをサブCPU側に転送し、サブCPUは再起動時にお
いてメインCPUから送出されてくる該データに基づい
て再起動前の正常な状態を再現することを特徴とする状
態再現方法。
[Claims] In a state reproduction method for a system including a main CPU and a sub CPU, the main CPU transfers data indicating the current operating state to the sub CPU at predetermined intervals, and the sub CPU transfers data indicating the current operating state at predetermined intervals, and the sub CPU A state reproduction method characterized by reproducing a normal state before restart based on the data sent from the main CPU.
JP10408689A 1989-04-24 1989-04-24 Sate reproducing method Pending JPH02281367A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10408689A JPH02281367A (en) 1989-04-24 1989-04-24 Sate reproducing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10408689A JPH02281367A (en) 1989-04-24 1989-04-24 Sate reproducing method

Publications (1)

Publication Number Publication Date
JPH02281367A true JPH02281367A (en) 1990-11-19

Family

ID=14371320

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10408689A Pending JPH02281367A (en) 1989-04-24 1989-04-24 Sate reproducing method

Country Status (1)

Country Link
JP (1) JPH02281367A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6256781B1 (en) 1991-04-26 2001-07-03 Sharp Kabushiki Kaisha External reset and data transfer method and apparatus for a portable electronic device
US7073097B2 (en) 2000-09-13 2006-07-04 Funai Electric Co., Ltd. Two-MCU system and hang-up detecting method of MCU
JP2008131603A (en) * 2006-11-24 2008-06-05 Ricoh Co Ltd Image processor and image processing method
JP2010004979A (en) * 2008-06-25 2010-01-14 Fujifilm Corp Image processor and processor for endoscope

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55153021A (en) * 1979-05-16 1980-11-28 Hitachi Ltd Data transfer system of multiprocessor system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55153021A (en) * 1979-05-16 1980-11-28 Hitachi Ltd Data transfer system of multiprocessor system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6256781B1 (en) 1991-04-26 2001-07-03 Sharp Kabushiki Kaisha External reset and data transfer method and apparatus for a portable electronic device
US7073097B2 (en) 2000-09-13 2006-07-04 Funai Electric Co., Ltd. Two-MCU system and hang-up detecting method of MCU
JP2008131603A (en) * 2006-11-24 2008-06-05 Ricoh Co Ltd Image processor and image processing method
JP2010004979A (en) * 2008-06-25 2010-01-14 Fujifilm Corp Image processor and processor for endoscope

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